1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2001 MIPS Technologies, Inc. 8 */ 9#include <linux/kernel.h> 10#include <linux/sched.h> 11#include <linux/signal.h> 12#include <asm/branch.h> 13#include <asm/cpu.h> 14#include <asm/cpu-features.h> 15#include <asm/fpu.h> 16#include <asm/fpu_emulator.h> 17#include <asm/inst.h> 18#include <asm/ptrace.h> 19#include <asm/uaccess.h> 20 21/* 22 * Calculate and return exception epc in case of 23 * branch delay slot for microMIPS/MIPS16e 24 * It doesn't clear ISA mode bit. 25 */ 26int __isa_exception_epc(struct pt_regs *regs) 27{ 28 long epc; 29 union mips16e_instruction inst; 30 31 /* calc exception pc in branch delay slot */ 32 epc = regs->cp0_epc; 33 if (__get_user(inst.full, (u16 __user *) (epc & ~MIPS_ISA_MODE))) { 34 /* it should never happens... because delay slot was checked */ 35 force_sig(SIGSEGV, current); 36 return epc; 37 } 38 if (cpu_has_mips16) { 39 if (inst.ri.opcode == MIPS16e_jal_op) 40 epc += 4; 41 else 42 epc += 2; 43 } else if (mm_is16bit(inst.full)) 44 epc += 2; 45 else 46 epc += 4; 47 48 return epc; 49} 50 51/* 52 * Compute the return address and do emulate branch simulation in MIPS16e mode, 53 * if required. 54 * After exception only - doesn't do 'compact' branch/jumps and can't be used 55 * during interrupt (compact B/J doesn't do exception) 56 */ 57int __MIPS16e_compute_return_epc(struct pt_regs *regs) 58{ 59 u16 __user *addr; 60 union mips16e_instruction inst; 61 u16 inst2; 62 u32 fullinst; 63 long epc; 64 65 epc = regs->cp0_epc; 66 /* 67 * Read the instruction 68 */ 69 addr = (u16 __user *) (epc & ~MIPS_ISA_MODE); 70 if (__get_user(inst.full, addr)) { 71 force_sig(SIGSEGV, current); 72 return -EFAULT; 73 } 74 75 switch (inst.ri.opcode) { 76 case MIPS16e_extend_op: 77 regs->cp0_epc += 4; 78 return 0; 79 80 /* 81 * JAL and JALX in MIPS16e mode 82 */ 83 case MIPS16e_jal_op: 84 addr += 1; 85 if (__get_user(inst2, addr)) { 86 force_sig(SIGSEGV, current); 87 return -EFAULT; 88 } 89 fullinst = ((unsigned)inst.full << 16) | inst2; 90 regs->regs[31] = epc + 6; 91 epc += 4; 92 epc >>= 28; 93 epc <<= 28; 94 /* 95 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16 96 * 97 * ......TARGET[15:0].................TARGET[20:16]........... 98 * ......TARGET[25:21] 99 */ 100 epc |= 101 ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) | 102 ((fullinst & 0x1f0000) << 7); 103 if (!inst.jal.x) 104 epc |= MIPS_ISA_MODE; /* set ISA mode 1 */ 105 regs->cp0_epc = epc; 106 return 0; 107 108 /* 109 * J(AL)R(C) 110 */ 111 case MIPS16e_rr_op: 112 if (inst.rr.func == MIPS16e_jr_func) { 113 114 if (inst.rr.ra) 115 regs->cp0_epc = regs->regs[31]; 116 else 117 regs->cp0_epc = 118 regs->regs[mips16e_reg2gpr[inst.rr.rx]]; 119 120 if (inst.rr.l) { 121 if (inst.rr.nd) 122 regs->regs[31] = epc + 2; 123 else 124 regs->regs[31] = epc + 4; 125 } 126 return 0; 127 } 128 break; 129 } 130 131 /* all other cases have no branch delay slot and are 16bits, 132 and branches do not do exception */ 133 regs->cp0_epc += 2; 134 135 return 0; 136} 137 138/* 139 * Compute the return address and do emulate branch simulation in 140 * microMIPS mode, if required. 141 * After exception only - doesn't do 'compact' branch/jumps and can't be used 142 * during interrupt (compact B/J doesn't do exception) 143 */ 144int __microMIPS_compute_return_epc(struct pt_regs *regs) 145{ 146 u16 __user *pc16; 147 u16 halfword; 148 unsigned int word; 149 unsigned long contpc; 150 struct decoded_instn mminst = { 0 }; 151 152 mminst.micro_mips_mode = 1; 153 154 /* 155 * This load never faults. 156 */ 157 pc16 = (unsigned short __user *)(regs->cp0_epc & ~MIPS_ISA_MODE); 158 __get_user(halfword, pc16); 159 pc16++; 160 contpc = regs->cp0_epc + 2; 161 word = ((unsigned int)halfword << 16); 162 mminst.pc_inc = 2; 163 164 if (!mm_is16bit(halfword)) { 165 __get_user(halfword, pc16); 166 pc16++; 167 contpc = regs->cp0_epc + 4; 168 mminst.pc_inc = 4; 169 word |= halfword; 170 } 171 mminst.insn = word; 172 173 if (get_user(halfword, pc16)) 174 goto sigsegv; 175 mminst.next_pc_inc = 2; 176 word = ((unsigned int)halfword << 16); 177 178 if (!mm_is16bit(halfword)) { 179 pc16++; 180 if (get_user(halfword, pc16)) 181 goto sigsegv; 182 mminst.next_pc_inc = 4; 183 word |= halfword; 184 } 185 mminst.next_insn = word; 186 187 mm_isBranchInstr(regs, mminst, &contpc); 188 189 regs->cp0_epc = contpc; 190 191 return 0; 192 193sigsegv: 194 force_sig(SIGSEGV, current); 195 return -EFAULT; 196} 197 198/* 199 * Compute the return address and do emulate branch simulation, if required. 200 * This function should be called only in branch delay slot active. 201 */ 202int __compute_return_epc(struct pt_regs *regs) 203{ 204 unsigned int __user *addr; 205 unsigned int bit, fcr31, dspcontrol; 206 long epc; 207 union mips_instruction insn; 208 209 epc = regs->cp0_epc; 210 if (epc & 3) 211 goto unaligned; 212 213 /* 214 * Read the instruction 215 */ 216 addr = (unsigned int __user *) epc; 217 if (__get_user(insn.word, addr)) { 218 force_sig(SIGSEGV, current); 219 return -EFAULT; 220 } 221 222 switch (insn.i_format.opcode) { 223 /* 224 * jr and jalr are in r_format format. 225 */ 226 case spec_op: 227 switch (insn.r_format.func) { 228 case jalr_op: 229 regs->regs[insn.r_format.rd] = epc + 8; 230 /* Fall through */ 231 case jr_op: 232 regs->cp0_epc = regs->regs[insn.r_format.rs]; 233 break; 234 } 235 break; 236 237 /* 238 * This group contains: 239 * bltz_op, bgez_op, bltzl_op, bgezl_op, 240 * bltzal_op, bgezal_op, bltzall_op, bgezall_op. 241 */ 242 case bcond_op: 243 switch (insn.i_format.rt) { 244 case bltz_op: 245 case bltzl_op: 246 if ((long)regs->regs[insn.i_format.rs] < 0) 247 epc = epc + 4 + (insn.i_format.simmediate << 2); 248 else 249 epc += 8; 250 regs->cp0_epc = epc; 251 break; 252 253 case bgez_op: 254 case bgezl_op: 255 if ((long)regs->regs[insn.i_format.rs] >= 0) 256 epc = epc + 4 + (insn.i_format.simmediate << 2); 257 else 258 epc += 8; 259 regs->cp0_epc = epc; 260 break; 261 262 case bltzal_op: 263 case bltzall_op: 264 regs->regs[31] = epc + 8; 265 if ((long)regs->regs[insn.i_format.rs] < 0) 266 epc = epc + 4 + (insn.i_format.simmediate << 2); 267 else 268 epc += 8; 269 regs->cp0_epc = epc; 270 break; 271 272 case bgezal_op: 273 case bgezall_op: 274 regs->regs[31] = epc + 8; 275 if ((long)regs->regs[insn.i_format.rs] >= 0) 276 epc = epc + 4 + (insn.i_format.simmediate << 2); 277 else 278 epc += 8; 279 regs->cp0_epc = epc; 280 break; 281 case bposge32_op: 282 if (!cpu_has_dsp) 283 goto sigill; 284 285 dspcontrol = rddsp(0x01); 286 287 if (dspcontrol >= 32) { 288 epc = epc + 4 + (insn.i_format.simmediate << 2); 289 } else 290 epc += 8; 291 regs->cp0_epc = epc; 292 break; 293 } 294 break; 295 296 /* 297 * These are unconditional and in j_format. 298 */ 299 case jal_op: 300 regs->regs[31] = regs->cp0_epc + 8; 301 case j_op: 302 epc += 4; 303 epc >>= 28; 304 epc <<= 28; 305 epc |= (insn.j_format.target << 2); 306 regs->cp0_epc = epc; 307 if (insn.i_format.opcode == jalx_op) 308 regs->cp0_epc |= MIPS_ISA_MODE; 309 break; 310 311 /* 312 * These are conditional and in i_format. 313 */ 314 case beq_op: 315 case beql_op: 316 if (regs->regs[insn.i_format.rs] == 317 regs->regs[insn.i_format.rt]) 318 epc = epc + 4 + (insn.i_format.simmediate << 2); 319 else 320 epc += 8; 321 regs->cp0_epc = epc; 322 break; 323 324 case bne_op: 325 case bnel_op: 326 if (regs->regs[insn.i_format.rs] != 327 regs->regs[insn.i_format.rt]) 328 epc = epc + 4 + (insn.i_format.simmediate << 2); 329 else 330 epc += 8; 331 regs->cp0_epc = epc; 332 break; 333 334 case blez_op: /* not really i_format */ 335 case blezl_op: 336 /* rt field assumed to be zero */ 337 if ((long)regs->regs[insn.i_format.rs] <= 0) 338 epc = epc + 4 + (insn.i_format.simmediate << 2); 339 else 340 epc += 8; 341 regs->cp0_epc = epc; 342 break; 343 344 case bgtz_op: 345 case bgtzl_op: 346 /* rt field assumed to be zero */ 347 if ((long)regs->regs[insn.i_format.rs] > 0) 348 epc = epc + 4 + (insn.i_format.simmediate << 2); 349 else 350 epc += 8; 351 regs->cp0_epc = epc; 352 break; 353 354 /* 355 * And now the FPA/cp1 branch instructions. 356 */ 357 case cop1_op: 358 preempt_disable(); 359 if (is_fpu_owner()) 360 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 361 else 362 fcr31 = current->thread.fpu.fcr31; 363 preempt_enable(); 364 365 bit = (insn.i_format.rt >> 2); 366 bit += (bit != 0); 367 bit += 23; 368 switch (insn.i_format.rt & 3) { 369 case 0: /* bc1f */ 370 case 2: /* bc1fl */ 371 if (~fcr31 & (1 << bit)) 372 epc = epc + 4 + (insn.i_format.simmediate << 2); 373 else 374 epc += 8; 375 regs->cp0_epc = epc; 376 break; 377 378 case 1: /* bc1t */ 379 case 3: /* bc1tl */ 380 if (fcr31 & (1 << bit)) 381 epc = epc + 4 + (insn.i_format.simmediate << 2); 382 else 383 epc += 8; 384 regs->cp0_epc = epc; 385 break; 386 } 387 break; 388#ifdef CONFIG_CPU_CAVIUM_OCTEON 389 case lwc2_op: /* This is bbit0 on Octeon */ 390 if ((regs->regs[insn.i_format.rs] & (1ull << insn.i_format.rt)) 391 == 0) 392 epc = epc + 4 + (insn.i_format.simmediate << 2); 393 else 394 epc += 8; 395 regs->cp0_epc = epc; 396 break; 397 case ldc2_op: /* This is bbit032 on Octeon */ 398 if ((regs->regs[insn.i_format.rs] & 399 (1ull << (insn.i_format.rt + 32))) == 0) 400 epc = epc + 4 + (insn.i_format.simmediate << 2); 401 else 402 epc += 8; 403 regs->cp0_epc = epc; 404 break; 405 case swc2_op: /* This is bbit1 on Octeon */ 406 if (regs->regs[insn.i_format.rs] & (1ull << insn.i_format.rt)) 407 epc = epc + 4 + (insn.i_format.simmediate << 2); 408 else 409 epc += 8; 410 regs->cp0_epc = epc; 411 break; 412 case sdc2_op: /* This is bbit132 on Octeon */ 413 if (regs->regs[insn.i_format.rs] & 414 (1ull << (insn.i_format.rt + 32))) 415 epc = epc + 4 + (insn.i_format.simmediate << 2); 416 else 417 epc += 8; 418 regs->cp0_epc = epc; 419 break; 420#endif 421 } 422 423 return 0; 424 425unaligned: 426 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); 427 force_sig(SIGBUS, current); 428 return -EFAULT; 429 430sigill: 431 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm); 432 force_sig(SIGBUS, current); 433 return -EFAULT; 434} 435