1/* 2 * AMD Alchemy DBAu1200 Reference Board 3 * Board register defines. 4 * 5 * ######################################################################## 6 * 7 * This program is free software; you can distribute it and/or modify it 8 * under the terms of the GNU General Public License (Version 2) as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 * 20 * ######################################################################## 21 * 22 * 23 */ 24#ifndef __ASM_DB1200_H 25#define __ASM_DB1200_H 26 27#include <linux/types.h> 28#include <asm/mach-au1x00/au1000.h> 29#include <asm/mach-au1x00/au1xxx_psc.h> 30 31/* Bit positions for the different interrupt sources */ 32#define BCSR_INT_IDE 0x0001 33#define BCSR_INT_ETH 0x0002 34#define BCSR_INT_PC0 0x0004 35#define BCSR_INT_PC0STSCHG 0x0008 36#define BCSR_INT_PC1 0x0010 37#define BCSR_INT_PC1STSCHG 0x0020 38#define BCSR_INT_DC 0x0040 39#define BCSR_INT_FLASHBUSY 0x0080 40#define BCSR_INT_PC0INSERT 0x0100 41#define BCSR_INT_PC0EJECT 0x0200 42#define BCSR_INT_PC1INSERT 0x0400 43#define BCSR_INT_PC1EJECT 0x0800 44#define BCSR_INT_SD0INSERT 0x1000 45#define BCSR_INT_SD0EJECT 0x2000 46 47#define IDE_PHYS_ADDR 0x18800000 48#define IDE_REG_SHIFT 5 49#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 50#define IDE_RQSIZE 128 51 52#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR 53#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) 54#define DB1200_ETH_PHYS_ADDR 0x19000300 55#define DB1200_NAND_PHYS_ADDR 0x20000000 56 57/* 58 * External Interrupts for DBAu1200 as of 8/6/2004. 59 * Bit positions in the CPLD registers can be calculated by taking 60 * the interrupt define and subtracting the DB1200_INT_BEGIN value. 61 * 62 * Example: IDE bis pos is = 64 - 64 63 * ETH bit pos is = 65 - 64 64 */ 65enum external_db1200_ints { 66 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, 67 68 DB1200_IDE_INT = DB1200_INT_BEGIN, 69 DB1200_ETH_INT, 70 DB1200_PC0_INT, 71 DB1200_PC0_STSCHG_INT, 72 DB1200_PC1_INT, 73 DB1200_PC1_STSCHG_INT, 74 DB1200_DC_INT, 75 DB1200_FLASHBUSY_INT, 76 DB1200_PC0_INSERT_INT, 77 DB1200_PC0_EJECT_INT, 78 DB1200_PC1_INSERT_INT, 79 DB1200_PC1_EJECT_INT, 80 DB1200_SD0_INSERT_INT, 81 DB1200_SD0_EJECT_INT, 82 83 DB1200_INT_END = DB1200_INT_BEGIN + 15, 84}; 85 86#endif /* __ASM_DB1200_H */ 87