1/* 2 * Exception handling for Microblaze 3 * 4 * Rewriten interrupt handling 5 * 6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 7 * Copyright (C) 2008-2009 PetaLogix 8 * 9 * uClinux customisation (C) 2005 John Williams 10 * 11 * MMU code derived from arch/ppc/kernel/head_4xx.S: 12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org> 13 * Initial PowerPC version. 14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 15 * Rewritten for PReP 16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 17 * Low-level exception handers, MMU support, and rewrite. 18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net> 19 * PowerPC 8xx modifications. 20 * Copyright (C) 1998-1999 TiVo, Inc. 21 * PowerPC 403GCX modifications. 22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu> 23 * PowerPC 403GCX/405GP modifications. 24 * Copyright 2000 MontaVista Software Inc. 25 * PPC405 modifications 26 * PowerPC 403GCX/405GP modifications. 27 * Author: MontaVista Software, Inc. 28 * frank_rowand@mvista.com or source@mvista.com 29 * debbie_chu@mvista.com 30 * 31 * Original code 32 * Copyright (C) 2004 Xilinx, Inc. 33 * 34 * This program is free software; you can redistribute it and/or modify it 35 * under the terms of the GNU General Public License version 2 as published 36 * by the Free Software Foundation. 37 */ 38 39/* 40 * Here are the handlers which don't require enabling translation 41 * and calling other kernel code thus we can keep their design very simple 42 * and do all processing in real mode. All what they need is a valid current 43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case) 44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore 45 * these registers are saved/restored 46 * The handlers which require translation are in entry.S --KAA 47 * 48 * Microblaze HW Exception Handler 49 * - Non self-modifying exception handler for the following exception conditions 50 * - Unalignment 51 * - Instruction bus error 52 * - Data bus error 53 * - Illegal instruction opcode 54 * - Divide-by-zero 55 * 56 * - Privileged instruction exception (MMU) 57 * - Data storage exception (MMU) 58 * - Instruction storage exception (MMU) 59 * - Data TLB miss exception (MMU) 60 * - Instruction TLB miss exception (MMU) 61 * 62 * Note we disable interrupts during exception handling, otherwise we will 63 * possibly get multiple re-entrancy if interrupt handles themselves cause 64 * exceptions. JW 65 */ 66 67#include <asm/exceptions.h> 68#include <asm/unistd.h> 69#include <asm/page.h> 70 71#include <asm/entry.h> 72#include <asm/current.h> 73#include <linux/linkage.h> 74 75#include <asm/mmu.h> 76#include <asm/pgtable.h> 77#include <asm/signal.h> 78#include <asm/asm-offsets.h> 79 80/* Helpful Macros */ 81#define NUM_TO_REG(num) r ## num 82 83#ifdef CONFIG_MMU 84 #define RESTORE_STATE \ 85 lwi r5, r1, 0; \ 86 mts rmsr, r5; \ 87 nop; \ 88 lwi r3, r1, PT_R3; \ 89 lwi r4, r1, PT_R4; \ 90 lwi r5, r1, PT_R5; \ 91 lwi r6, r1, PT_R6; \ 92 lwi r11, r1, PT_R11; \ 93 lwi r31, r1, PT_R31; \ 94 lwi r1, r0, TOPHYS(r0_ram + 0); 95#endif /* CONFIG_MMU */ 96 97#define LWREG_NOP \ 98 bri ex_handler_unhandled; \ 99 nop; 100 101#define SWREG_NOP \ 102 bri ex_handler_unhandled; \ 103 nop; 104 105 106/* r3 is the source */ 107#define R3_TO_LWREG_V(regnum) \ 108 swi r3, r1, 4 * regnum; \ 109 bri ex_handler_done; 110 111/* r3 is the source */ 112#define R3_TO_LWREG(regnum) \ 113 or NUM_TO_REG (regnum), r0, r3; \ 114 bri ex_handler_done; 115 116/* r3 is the target */ 117#define SWREG_TO_R3_V(regnum) \ 118 lwi r3, r1, 4 * regnum; \ 119 bri ex_sw_tail; 120 121/* r3 is the target */ 122#define SWREG_TO_R3(regnum) \ 123 or r3, r0, NUM_TO_REG (regnum); \ 124 bri ex_sw_tail; 125 126#ifdef CONFIG_MMU 127 #define R3_TO_LWREG_VM_V(regnum) \ 128 brid ex_lw_end_vm; \ 129 swi r3, r7, 4 * regnum; 130 131 #define R3_TO_LWREG_VM(regnum) \ 132 brid ex_lw_end_vm; \ 133 or NUM_TO_REG (regnum), r0, r3; 134 135 #define SWREG_TO_R3_VM_V(regnum) \ 136 brid ex_sw_tail_vm; \ 137 lwi r3, r7, 4 * regnum; 138 139 #define SWREG_TO_R3_VM(regnum) \ 140 brid ex_sw_tail_vm; \ 141 or r3, r0, NUM_TO_REG (regnum); 142 143 /* Shift right instruction depending on available configuration */ 144 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0 145 #define BSRLI(rD, rA, imm) \ 146 bsrli rD, rA, imm 147 #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0 148 #define BSRLI(rD, rA, imm) \ 149 ori rD, r0, (1 << imm); \ 150 idivu rD, rD, rA 151 #else 152 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA) 153 /* Only the used shift constants defined here - add more if needed */ 154 #define BSRLI2(rD, rA) \ 155 srl rD, rA; /* << 1 */ \ 156 srl rD, rD; /* << 2 */ 157 #define BSRLI10(rD, rA) \ 158 srl rD, rA; /* << 1 */ \ 159 srl rD, rD; /* << 2 */ \ 160 srl rD, rD; /* << 3 */ \ 161 srl rD, rD; /* << 4 */ \ 162 srl rD, rD; /* << 5 */ \ 163 srl rD, rD; /* << 6 */ \ 164 srl rD, rD; /* << 7 */ \ 165 srl rD, rD; /* << 8 */ \ 166 srl rD, rD; /* << 9 */ \ 167 srl rD, rD /* << 10 */ 168 #define BSRLI20(rD, rA) \ 169 BSRLI10(rD, rA); \ 170 BSRLI10(rD, rD) 171 #endif 172#endif /* CONFIG_MMU */ 173 174.extern other_exception_handler /* Defined in exception.c */ 175 176/* 177 * hw_exception_handler - Handler for exceptions 178 * 179 * Exception handler notes: 180 * - Handles all exceptions 181 * - Does not handle unaligned exceptions during load into r17, r1, r0. 182 * - Does not handle unaligned exceptions during store from r17 (cannot be 183 * done) and r1 (slows down common case) 184 * 185 * Relevant register structures 186 * 187 * EAR - |----|----|----|----|----|----|----|----| 188 * - < ## 32 bit faulting address ## > 189 * 190 * ESR - |----|----|----|----|----| - | - |-----|-----| 191 * - W S REG EXC 192 * 193 * 194 * STACK FRAME STRUCTURE (for NO_MMU) 195 * --------------------------------- 196 * 197 * +-------------+ + 0 198 * | MSR | 199 * +-------------+ + 4 200 * | r1 | 201 * | . | 202 * | . | 203 * | . | 204 * | . | 205 * | r18 | 206 * +-------------+ + 76 207 * | . | 208 * | . | 209 * 210 * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S 211 * which is used for storing register values - old style was, that value were 212 * stored in stack but in case of failure you lost information about register. 213 * Currently you can see register value in memory in specific place. 214 * In compare to with previous solution the speed should be the same. 215 * 216 * MMU exception handler has different handling compare to no MMU kernel. 217 * Exception handler use jump table for directing of what happen. For MMU kernel 218 * is this approach better because MMU relate exception are handled by asm code 219 * in this file. In compare to with MMU expect of unaligned exception 220 * is everything handled by C code. 221 */ 222 223/* 224 * every of these handlers is entered having R3/4/5/6/11/current saved on stack 225 * and clobbered so care should be taken to restore them if someone is going to 226 * return from exception 227 */ 228 229/* wrappers to restore state before coming to entry.S */ 230 231#ifdef CONFIG_MMU 232.section .rodata 233.align 4 234_MB_HW_ExceptionVectorTable: 235/* 0 - Undefined */ 236 .long TOPHYS(ex_handler_unhandled) 237/* 1 - Unaligned data access exception */ 238 .long TOPHYS(handle_unaligned_ex) 239/* 2 - Illegal op-code exception */ 240 .long TOPHYS(full_exception_trapw) 241/* 3 - Instruction bus error exception */ 242 .long TOPHYS(full_exception_trapw) 243/* 4 - Data bus error exception */ 244 .long TOPHYS(full_exception_trapw) 245/* 5 - Divide by zero exception */ 246 .long TOPHYS(full_exception_trapw) 247/* 6 - Floating point unit exception */ 248 .long TOPHYS(full_exception_trapw) 249/* 7 - Privileged instruction exception */ 250 .long TOPHYS(full_exception_trapw) 251/* 8 - 15 - Undefined */ 252 .long TOPHYS(ex_handler_unhandled) 253 .long TOPHYS(ex_handler_unhandled) 254 .long TOPHYS(ex_handler_unhandled) 255 .long TOPHYS(ex_handler_unhandled) 256 .long TOPHYS(ex_handler_unhandled) 257 .long TOPHYS(ex_handler_unhandled) 258 .long TOPHYS(ex_handler_unhandled) 259 .long TOPHYS(ex_handler_unhandled) 260/* 16 - Data storage exception */ 261 .long TOPHYS(handle_data_storage_exception) 262/* 17 - Instruction storage exception */ 263 .long TOPHYS(handle_instruction_storage_exception) 264/* 18 - Data TLB miss exception */ 265 .long TOPHYS(handle_data_tlb_miss_exception) 266/* 19 - Instruction TLB miss exception */ 267 .long TOPHYS(handle_instruction_tlb_miss_exception) 268/* 20 - 31 - Undefined */ 269 .long TOPHYS(ex_handler_unhandled) 270 .long TOPHYS(ex_handler_unhandled) 271 .long TOPHYS(ex_handler_unhandled) 272 .long TOPHYS(ex_handler_unhandled) 273 .long TOPHYS(ex_handler_unhandled) 274 .long TOPHYS(ex_handler_unhandled) 275 .long TOPHYS(ex_handler_unhandled) 276 .long TOPHYS(ex_handler_unhandled) 277 .long TOPHYS(ex_handler_unhandled) 278 .long TOPHYS(ex_handler_unhandled) 279 .long TOPHYS(ex_handler_unhandled) 280 .long TOPHYS(ex_handler_unhandled) 281#endif 282 283.global _hw_exception_handler 284.section .text 285.align 4 286.ent _hw_exception_handler 287_hw_exception_handler: 288#ifndef CONFIG_MMU 289 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */ 290#else 291 swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */ 292 /* Save date to kernel memory. Here is the problem 293 * when you came from user space */ 294 ori r1, r0, TOPHYS(r0_ram + 28); 295#endif 296 swi r3, r1, PT_R3 297 swi r4, r1, PT_R4 298 swi r5, r1, PT_R5 299 swi r6, r1, PT_R6 300 301#ifdef CONFIG_MMU 302 swi r11, r1, PT_R11 303 swi r31, r1, PT_R31 304 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */ 305#endif 306 307 mfs r5, rmsr; 308 nop 309 swi r5, r1, 0; 310 mfs r4, resr 311 nop 312 mfs r3, rear; 313 nop 314 315#ifndef CONFIG_MMU 316 andi r5, r4, 0x1000; /* Check ESR[DS] */ 317 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */ 318 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */ 319 nop 320not_in_delay_slot: 321 swi r17, r1, PT_R17 322#endif 323 324 andi r5, r4, 0x1F; /* Extract ESR[EXC] */ 325 326#ifdef CONFIG_MMU 327 /* Calculate exception vector offset = r5 << 2 */ 328 addk r6, r5, r5; /* << 1 */ 329 addk r6, r6, r6; /* << 2 */ 330 331#ifdef DEBUG 332/* counting which exception happen */ 333 lwi r5, r0, 0x200 + TOPHYS(r0_ram) 334 addi r5, r5, 1 335 swi r5, r0, 0x200 + TOPHYS(r0_ram) 336 lwi r5, r6, 0x200 + TOPHYS(r0_ram) 337 addi r5, r5, 1 338 swi r5, r6, 0x200 + TOPHYS(r0_ram) 339#endif 340/* end */ 341 /* Load the HW Exception vector */ 342 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable) 343 bra r6 344 345full_exception_trapw: 346 RESTORE_STATE 347 bri full_exception_trap 348#else 349 /* Exceptions enabled here. This will allow nested exceptions */ 350 mfs r6, rmsr; 351 nop 352 swi r6, r1, 0; /* RMSR_OFFSET */ 353 ori r6, r6, 0x100; /* Turn ON the EE bit */ 354 andi r6, r6, ~2; /* Disable interrupts */ 355 mts rmsr, r6; 356 nop 357 358 xori r6, r5, 1; /* 00001 = Unaligned Exception */ 359 /* Jump to unalignment exception handler */ 360 beqi r6, handle_unaligned_ex; 361 362handle_other_ex: /* Handle Other exceptions here */ 363 /* Save other volatiles before we make procedure calls below */ 364 swi r7, r1, PT_R7 365 swi r8, r1, PT_R8 366 swi r9, r1, PT_R9 367 swi r10, r1, PT_R10 368 swi r11, r1, PT_R11 369 swi r12, r1, PT_R12 370 swi r14, r1, PT_R14 371 swi r15, r1, PT_R15 372 swi r18, r1, PT_R18 373 374 or r5, r1, r0 375 andi r6, r4, 0x1F; /* Load ESR[EC] */ 376 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */ 377 swi r7, r1, PT_MODE 378 mfs r7, rfsr 379 nop 380 addk r8, r17, r0; /* Load exception address */ 381 bralid r15, full_exception; /* Branch to the handler */ 382 nop; 383 mts rfsr, r0; /* Clear sticky fsr */ 384 nop 385 386 /* 387 * Trigger execution of the signal handler by enabling 388 * interrupts and calling an invalid syscall. 389 */ 390 mfs r5, rmsr; 391 nop 392 ori r5, r5, 2; 393 mts rmsr, r5; /* enable interrupt */ 394 nop 395 addi r12, r0, __NR_syscalls; 396 brki r14, 0x08; 397 mfs r5, rmsr; /* disable interrupt */ 398 nop 399 andi r5, r5, ~2; 400 mts rmsr, r5; 401 nop 402 403 lwi r7, r1, PT_R7 404 lwi r8, r1, PT_R8 405 lwi r9, r1, PT_R9 406 lwi r10, r1, PT_R10 407 lwi r11, r1, PT_R11 408 lwi r12, r1, PT_R12 409 lwi r14, r1, PT_R14 410 lwi r15, r1, PT_R15 411 lwi r18, r1, PT_R18 412 413 bri ex_handler_done; /* Complete exception handling */ 414#endif 415 416/* 0x01 - Unaligned data access exception 417 * This occurs when a word access is not aligned on a word boundary, 418 * or when a 16-bit access is not aligned on a 16-bit boundary. 419 * This handler perform the access, and returns, except for MMU when 420 * the unaligned address is last on a 4k page or the physical address is 421 * not found in the page table, in which case unaligned_data_trap is called. 422 */ 423handle_unaligned_ex: 424 /* Working registers already saved: R3, R4, R5, R6 425 * R4 = ESR 426 * R3 = EAR 427 */ 428#ifdef CONFIG_MMU 429 andi r6, r4, 0x1000 /* Check ESR[DS] */ 430 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */ 431 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */ 432 nop 433_no_delayslot: 434 /* jump to high level unaligned handler */ 435 RESTORE_STATE; 436 bri unaligned_data_trap 437#endif 438 andi r6, r4, 0x3E0; /* Mask and extract the register operand */ 439 srl r6, r6; /* r6 >> 5 */ 440 srl r6, r6; 441 srl r6, r6; 442 srl r6, r6; 443 srl r6, r6; 444 /* Store the register operand in a temporary location */ 445 sbi r6, r0, TOPHYS(ex_reg_op); 446 447 andi r6, r4, 0x400; /* Extract ESR[S] */ 448 bnei r6, ex_sw; 449ex_lw: 450 andi r6, r4, 0x800; /* Extract ESR[W] */ 451 beqi r6, ex_lhw; 452 lbui r5, r3, 0; /* Exception address in r3 */ 453 /* Load a word, byte-by-byte from destination address 454 and save it in tmp space */ 455 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0); 456 lbui r5, r3, 1; 457 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1); 458 lbui r5, r3, 2; 459 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2); 460 lbui r5, r3, 3; 461 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3); 462 /* Get the destination register value into r4 */ 463 lwi r4, r0, TOPHYS(ex_tmp_data_loc_0); 464 bri ex_lw_tail; 465ex_lhw: 466 lbui r5, r3, 0; /* Exception address in r3 */ 467 /* Load a half-word, byte-by-byte from destination 468 address and save it in tmp space */ 469 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0); 470 lbui r5, r3, 1; 471 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1); 472 /* Get the destination register value into r4 */ 473 lhui r4, r0, TOPHYS(ex_tmp_data_loc_0); 474ex_lw_tail: 475 /* Get the destination register number into r5 */ 476 lbui r5, r0, TOPHYS(ex_reg_op); 477 /* Form load_word jump table offset (lw_table + (8 * regnum)) */ 478 la r6, r0, TOPHYS(lw_table); 479 addk r5, r5, r5; 480 addk r5, r5, r5; 481 addk r5, r5, r5; 482 addk r5, r5, r6; 483 bra r5; 484ex_lw_end: /* Exception handling of load word, ends */ 485ex_sw: 486 /* Get the destination register number into r5 */ 487 lbui r5, r0, TOPHYS(ex_reg_op); 488 /* Form store_word jump table offset (sw_table + (8 * regnum)) */ 489 la r6, r0, TOPHYS(sw_table); 490 add r5, r5, r5; 491 add r5, r5, r5; 492 add r5, r5, r5; 493 add r5, r5, r6; 494 bra r5; 495ex_sw_tail: 496 mfs r6, resr; 497 nop 498 andi r6, r6, 0x800; /* Extract ESR[W] */ 499 beqi r6, ex_shw; 500 /* Get the word - delay slot */ 501 swi r4, r0, TOPHYS(ex_tmp_data_loc_0); 502 /* Store the word, byte-by-byte into destination address */ 503 lbui r4, r0, TOPHYS(ex_tmp_data_loc_0); 504 sbi r4, r3, 0; 505 lbui r4, r0, TOPHYS(ex_tmp_data_loc_1); 506 sbi r4, r3, 1; 507 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2); 508 sbi r4, r3, 2; 509 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3); 510 sbi r4, r3, 3; 511 bri ex_handler_done; 512 513ex_shw: 514 /* Store the lower half-word, byte-by-byte into destination address */ 515 swi r4, r0, TOPHYS(ex_tmp_data_loc_0); 516 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2); 517 sbi r4, r3, 0; 518 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3); 519 sbi r4, r3, 1; 520ex_sw_end: /* Exception handling of store word, ends. */ 521 522ex_handler_done: 523#ifndef CONFIG_MMU 524 lwi r5, r1, 0 /* RMSR */ 525 mts rmsr, r5 526 nop 527 lwi r3, r1, PT_R3 528 lwi r4, r1, PT_R4 529 lwi r5, r1, PT_R5 530 lwi r6, r1, PT_R6 531 lwi r17, r1, PT_R17 532 533 rted r17, 0 534 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */ 535#else 536 RESTORE_STATE; 537 rted r17, 0 538 nop 539#endif 540 541#ifdef CONFIG_MMU 542 /* Exception vector entry code. This code runs with address translation 543 * turned off (i.e. using physical addresses). */ 544 545 /* Exception vectors. */ 546 547 /* 0x10 - Data Storage Exception 548 * This happens for just a few reasons. U0 set (but we don't do that), 549 * or zone protection fault (user violation, write to protected page). 550 * If this is just an update of modified status, we do that quickly 551 * and exit. Otherwise, we call heavyweight functions to do the work. 552 */ 553 handle_data_storage_exception: 554 /* Working registers already saved: R3, R4, R5, R6 555 * R3 = ESR 556 */ 557 mfs r11, rpid 558 nop 559 /* If we are faulting a kernel address, we have to use the 560 * kernel page tables. 561 */ 562 ori r5, r0, CONFIG_KERNEL_START 563 cmpu r5, r3, r5 564 bgti r5, ex3 565 /* First, check if it was a zone fault (which means a user 566 * tried to access a kernel or read-protected page - always 567 * a SEGV). All other faults here must be stores, so no 568 * need to check ESR_S as well. */ 569 andi r4, r4, 0x800 /* ESR_Z - zone protection */ 570 bnei r4, ex2 571 572 ori r4, r0, swapper_pg_dir 573 mts rpid, r0 /* TLB will have 0 TID */ 574 nop 575 bri ex4 576 577 /* Get the PGD for the current thread. */ 578 ex3: 579 /* First, check if it was a zone fault (which means a user 580 * tried to access a kernel or read-protected page - always 581 * a SEGV). All other faults here must be stores, so no 582 * need to check ESR_S as well. */ 583 andi r4, r4, 0x800 /* ESR_Z */ 584 bnei r4, ex2 585 /* get current task address */ 586 addi r4 ,CURRENT_TASK, TOPHYS(0); 587 lwi r4, r4, TASK_THREAD+PGDIR 588 ex4: 589 tophys(r4,r4) 590 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 591 andi r5, r5, 0xffc 592/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 593 or r4, r4, r5 594 lwi r4, r4, 0 /* Get L1 entry */ 595 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 596 beqi r5, ex2 /* Bail if no table */ 597 598 tophys(r5,r5) 599 BSRLI(r6,r3,10) /* Compute PTE address */ 600 andi r6, r6, 0xffc 601 andi r5, r5, 0xfffff003 602 or r5, r5, r6 603 lwi r4, r5, 0 /* Get Linux PTE */ 604 605 andi r6, r4, _PAGE_RW /* Is it writeable? */ 606 beqi r6, ex2 /* Bail if not */ 607 608 /* Update 'changed' */ 609 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE 610 swi r4, r5, 0 /* Update Linux page table */ 611 612 /* Most of the Linux PTE is ready to load into the TLB LO. 613 * We set ZSEL, where only the LS-bit determines user access. 614 * We set execute, because we don't have the granularity to 615 * properly set this at the page level (Linux problem). 616 * If shared is set, we cause a zero PID->TID load. 617 * Many of these bits are software only. Bits we don't set 618 * here we (properly should) assume have the appropriate value. 619 */ 620 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 621 ori r4, r4, _PAGE_HWEXEC /* make it executable */ 622 623 /* find the TLB index that caused the fault. It has to be here*/ 624 mts rtlbsx, r3 625 nop 626 mfs r5, rtlbx /* DEBUG: TBD */ 627 nop 628 mts rtlblo, r4 /* Load TLB LO */ 629 nop 630 /* Will sync shadow TLBs */ 631 632 /* Done...restore registers and get out of here. */ 633 mts rpid, r11 634 nop 635 bri 4 636 637 RESTORE_STATE; 638 rted r17, 0 639 nop 640 ex2: 641 /* The bailout. Restore registers to pre-exception conditions 642 * and call the heavyweights to help us out. */ 643 mts rpid, r11 644 nop 645 bri 4 646 RESTORE_STATE; 647 bri page_fault_data_trap 648 649 650 /* 0x11 - Instruction Storage Exception 651 * This is caused by a fetch from non-execute or guarded pages. */ 652 handle_instruction_storage_exception: 653 /* Working registers already saved: R3, R4, R5, R6 654 * R3 = ESR 655 */ 656 657 RESTORE_STATE; 658 bri page_fault_instr_trap 659 660 /* 0x12 - Data TLB Miss Exception 661 * As the name implies, translation is not in the MMU, so search the 662 * page tables and fix it. The only purpose of this function is to 663 * load TLB entries from the page table if they exist. 664 */ 665 handle_data_tlb_miss_exception: 666 /* Working registers already saved: R3, R4, R5, R6 667 * R3 = EAR, R4 = ESR 668 */ 669 mfs r11, rpid 670 nop 671 672 /* If we are faulting a kernel address, we have to use the 673 * kernel page tables. */ 674 ori r6, r0, CONFIG_KERNEL_START 675 cmpu r4, r3, r6 676 bgti r4, ex5 677 ori r4, r0, swapper_pg_dir 678 mts rpid, r0 /* TLB will have 0 TID */ 679 nop 680 bri ex6 681 682 /* Get the PGD for the current thread. */ 683 ex5: 684 /* get current task address */ 685 addi r4 ,CURRENT_TASK, TOPHYS(0); 686 lwi r4, r4, TASK_THREAD+PGDIR 687 ex6: 688 tophys(r4,r4) 689 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 690 andi r5, r5, 0xffc 691/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 692 or r4, r4, r5 693 lwi r4, r4, 0 /* Get L1 entry */ 694 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 695 beqi r5, ex7 /* Bail if no table */ 696 697 tophys(r5,r5) 698 BSRLI(r6,r3,10) /* Compute PTE address */ 699 andi r6, r6, 0xffc 700 andi r5, r5, 0xfffff003 701 or r5, r5, r6 702 lwi r4, r5, 0 /* Get Linux PTE */ 703 704 andi r6, r4, _PAGE_PRESENT 705 beqi r6, ex7 706 707 ori r4, r4, _PAGE_ACCESSED 708 swi r4, r5, 0 709 710 /* Most of the Linux PTE is ready to load into the TLB LO. 711 * We set ZSEL, where only the LS-bit determines user access. 712 * We set execute, because we don't have the granularity to 713 * properly set this at the page level (Linux problem). 714 * If shared is set, we cause a zero PID->TID load. 715 * Many of these bits are software only. Bits we don't set 716 * here we (properly should) assume have the appropriate value. 717 */ 718 brid finish_tlb_load 719 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 720 ex7: 721 /* The bailout. Restore registers to pre-exception conditions 722 * and call the heavyweights to help us out. 723 */ 724 mts rpid, r11 725 nop 726 bri 4 727 RESTORE_STATE; 728 bri page_fault_data_trap 729 730 /* 0x13 - Instruction TLB Miss Exception 731 * Nearly the same as above, except we get our information from 732 * different registers and bailout to a different point. 733 */ 734 handle_instruction_tlb_miss_exception: 735 /* Working registers already saved: R3, R4, R5, R6 736 * R3 = ESR 737 */ 738 mfs r11, rpid 739 nop 740 741 /* If we are faulting a kernel address, we have to use the 742 * kernel page tables. 743 */ 744 ori r4, r0, CONFIG_KERNEL_START 745 cmpu r4, r3, r4 746 bgti r4, ex8 747 ori r4, r0, swapper_pg_dir 748 mts rpid, r0 /* TLB will have 0 TID */ 749 nop 750 bri ex9 751 752 /* Get the PGD for the current thread. */ 753 ex8: 754 /* get current task address */ 755 addi r4 ,CURRENT_TASK, TOPHYS(0); 756 lwi r4, r4, TASK_THREAD+PGDIR 757 ex9: 758 tophys(r4,r4) 759 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 760 andi r5, r5, 0xffc 761/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 762 or r4, r4, r5 763 lwi r4, r4, 0 /* Get L1 entry */ 764 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 765 beqi r5, ex10 /* Bail if no table */ 766 767 tophys(r5,r5) 768 BSRLI(r6,r3,10) /* Compute PTE address */ 769 andi r6, r6, 0xffc 770 andi r5, r5, 0xfffff003 771 or r5, r5, r6 772 lwi r4, r5, 0 /* Get Linux PTE */ 773 774 andi r6, r4, _PAGE_PRESENT 775 beqi r6, ex10 776 777 ori r4, r4, _PAGE_ACCESSED 778 swi r4, r5, 0 779 780 /* Most of the Linux PTE is ready to load into the TLB LO. 781 * We set ZSEL, where only the LS-bit determines user access. 782 * We set execute, because we don't have the granularity to 783 * properly set this at the page level (Linux problem). 784 * If shared is set, we cause a zero PID->TID load. 785 * Many of these bits are software only. Bits we don't set 786 * here we (properly should) assume have the appropriate value. 787 */ 788 brid finish_tlb_load 789 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 790 ex10: 791 /* The bailout. Restore registers to pre-exception conditions 792 * and call the heavyweights to help us out. 793 */ 794 mts rpid, r11 795 nop 796 bri 4 797 RESTORE_STATE; 798 bri page_fault_instr_trap 799 800/* Both the instruction and data TLB miss get to this point to load the TLB. 801 * r3 - EA of fault 802 * r4 - TLB LO (info from Linux PTE) 803 * r5, r6 - available to use 804 * PID - loaded with proper value when we get here 805 * Upon exit, we reload everything and RFI. 806 * A common place to load the TLB. 807 */ 808 tlb_index: 809 .long 1 /* MS: storing last used tlb index */ 810 finish_tlb_load: 811 /* MS: load the last used TLB index. */ 812 lwi r5, r0, TOPHYS(tlb_index) 813 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */ 814 815 andi r5, r5, (MICROBLAZE_TLB_SIZE-1) 816 ori r6, r0, 1 817 cmp r31, r5, r6 818 blti r31, ex12 819 addik r5, r6, 1 820 ex12: 821 /* MS: save back current TLB index */ 822 swi r5, r0, TOPHYS(tlb_index) 823 824 ori r4, r4, _PAGE_HWEXEC /* make it executable */ 825 mts rtlbx, r5 /* MS: save current TLB */ 826 nop 827 mts rtlblo, r4 /* MS: save to TLB LO */ 828 nop 829 830 /* Create EPN. This is the faulting address plus a static 831 * set of bits. These are size, valid, E, U0, and ensure 832 * bits 20 and 21 are zero. 833 */ 834 andi r3, r3, 0xfffff000 835 ori r3, r3, 0x0c0 836 mts rtlbhi, r3 /* Load TLB HI */ 837 nop 838 839 /* Done...restore registers and get out of here. */ 840 mts rpid, r11 841 nop 842 bri 4 843 RESTORE_STATE; 844 rted r17, 0 845 nop 846 847 /* extern void giveup_fpu(struct task_struct *prev) 848 * 849 * The MicroBlaze processor may have an FPU, so this should not just 850 * return: TBD. 851 */ 852 .globl giveup_fpu; 853 .align 4; 854 giveup_fpu: 855 bralid r15,0 /* TBD */ 856 nop 857 858 /* At present, this routine just hangs. - extern void abort(void) */ 859 .globl abort; 860 .align 4; 861 abort: 862 br r0 863 864 .globl set_context; 865 .align 4; 866 set_context: 867 mts rpid, r5 /* Shadow TLBs are automatically */ 868 nop 869 bri 4 /* flushed by changing PID */ 870 rtsd r15,8 871 nop 872 873#endif 874.end _hw_exception_handler 875 876#ifdef CONFIG_MMU 877/* Unaligned data access exception last on a 4k page for MMU. 878 * When this is called, we are in virtual mode with exceptions enabled 879 * and registers 1-13,15,17,18 saved. 880 * 881 * R3 = ESR 882 * R4 = EAR 883 * R7 = pointer to saved registers (struct pt_regs *regs) 884 * 885 * This handler perform the access, and returns via ret_from_exc. 886 */ 887.global _unaligned_data_exception 888.ent _unaligned_data_exception 889_unaligned_data_exception: 890 andi r8, r3, 0x3E0; /* Mask and extract the register operand */ 891 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */ 892 andi r6, r3, 0x400; /* Extract ESR[S] */ 893 bneid r6, ex_sw_vm; 894 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */ 895ex_lw_vm: 896 beqid r6, ex_lhw_vm; 897load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */ 898/* Load a word, byte-by-byte from destination address and save it in tmp space*/ 899 la r6, r0, ex_tmp_data_loc_0; 900 sbi r5, r6, 0; 901load2: lbui r5, r4, 1; 902 sbi r5, r6, 1; 903load3: lbui r5, r4, 2; 904 sbi r5, r6, 2; 905load4: lbui r5, r4, 3; 906 sbi r5, r6, 3; 907 brid ex_lw_tail_vm; 908/* Get the destination register value into r3 - delay slot */ 909 lwi r3, r6, 0; 910ex_lhw_vm: 911 /* Load a half-word, byte-by-byte from destination address and 912 * save it in tmp space */ 913 la r6, r0, ex_tmp_data_loc_0; 914 sbi r5, r6, 0; 915load5: lbui r5, r4, 1; 916 sbi r5, r6, 1; 917 lhui r3, r6, 0; /* Get the destination register value into r3 */ 918ex_lw_tail_vm: 919 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */ 920 addik r5, r8, lw_table_vm; 921 bra r5; 922ex_lw_end_vm: /* Exception handling of load word, ends */ 923 brai ret_from_exc; 924ex_sw_vm: 925/* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */ 926 addik r5, r8, sw_table_vm; 927 bra r5; 928ex_sw_tail_vm: 929 la r5, r0, ex_tmp_data_loc_0; 930 beqid r6, ex_shw_vm; 931 swi r3, r5, 0; /* Get the word - delay slot */ 932 /* Store the word, byte-by-byte into destination address */ 933 lbui r3, r5, 0; 934store1: sbi r3, r4, 0; 935 lbui r3, r5, 1; 936store2: sbi r3, r4, 1; 937 lbui r3, r5, 2; 938store3: sbi r3, r4, 2; 939 lbui r3, r5, 3; 940 brid ret_from_exc; 941store4: sbi r3, r4, 3; /* Delay slot */ 942ex_shw_vm: 943 /* Store the lower half-word, byte-by-byte into destination address */ 944 lbui r3, r5, 2; 945store5: sbi r3, r4, 0; 946 lbui r3, r5, 3; 947 brid ret_from_exc; 948store6: sbi r3, r4, 1; /* Delay slot */ 949ex_sw_end_vm: /* Exception handling of store word, ends. */ 950 951/* We have to prevent cases that get/put_user macros get unaligned pointer 952 * to bad page area. We have to find out which origin instruction caused it 953 * and called fixup for that origin instruction not instruction in unaligned 954 * handler */ 955ex_unaligned_fixup: 956 ori r5, r7, 0 /* setup pointer to pt_regs */ 957 lwi r6, r7, PT_PC; /* faulting address is one instruction above */ 958 addik r6, r6, -4 /* for finding proper fixup */ 959 swi r6, r7, PT_PC; /* a save back it to PT_PC */ 960 addik r7, r0, SIGSEGV 961 /* call bad_page_fault for finding aligned fixup, fixup address is saved 962 * in PT_PC which is used as return address from exception */ 963 la r15, r0, ret_from_exc-8 /* setup return address */ 964 brid bad_page_fault 965 nop 966 967/* We prevent all load/store because it could failed any attempt to access */ 968.section __ex_table,"a"; 969 .word load1,ex_unaligned_fixup; 970 .word load2,ex_unaligned_fixup; 971 .word load3,ex_unaligned_fixup; 972 .word load4,ex_unaligned_fixup; 973 .word load5,ex_unaligned_fixup; 974 .word store1,ex_unaligned_fixup; 975 .word store2,ex_unaligned_fixup; 976 .word store3,ex_unaligned_fixup; 977 .word store4,ex_unaligned_fixup; 978 .word store5,ex_unaligned_fixup; 979 .word store6,ex_unaligned_fixup; 980.previous; 981.end _unaligned_data_exception 982#endif /* CONFIG_MMU */ 983 984.global ex_handler_unhandled 985ex_handler_unhandled: 986 bri 0 987 988/* 989 * hw_exception_handler Jump Table 990 * - Contains code snippets for each register that caused the unalign exception 991 * - Hence exception handler is NOT self-modifying 992 * - Separate table for load exceptions and store exceptions. 993 * - Each table is of size: (8 * 32) = 256 bytes 994 */ 995 996.section .text 997.align 4 998lw_table: 999lw_r0: R3_TO_LWREG (0); 1000lw_r1: LWREG_NOP; 1001lw_r2: R3_TO_LWREG (2); 1002lw_r3: R3_TO_LWREG_V (3); 1003lw_r4: R3_TO_LWREG_V (4); 1004lw_r5: R3_TO_LWREG_V (5); 1005lw_r6: R3_TO_LWREG_V (6); 1006lw_r7: R3_TO_LWREG (7); 1007lw_r8: R3_TO_LWREG (8); 1008lw_r9: R3_TO_LWREG (9); 1009lw_r10: R3_TO_LWREG (10); 1010lw_r11: R3_TO_LWREG (11); 1011lw_r12: R3_TO_LWREG (12); 1012lw_r13: R3_TO_LWREG (13); 1013lw_r14: R3_TO_LWREG (14); 1014lw_r15: R3_TO_LWREG (15); 1015lw_r16: R3_TO_LWREG (16); 1016lw_r17: LWREG_NOP; 1017lw_r18: R3_TO_LWREG (18); 1018lw_r19: R3_TO_LWREG (19); 1019lw_r20: R3_TO_LWREG (20); 1020lw_r21: R3_TO_LWREG (21); 1021lw_r22: R3_TO_LWREG (22); 1022lw_r23: R3_TO_LWREG (23); 1023lw_r24: R3_TO_LWREG (24); 1024lw_r25: R3_TO_LWREG (25); 1025lw_r26: R3_TO_LWREG (26); 1026lw_r27: R3_TO_LWREG (27); 1027lw_r28: R3_TO_LWREG (28); 1028lw_r29: R3_TO_LWREG (29); 1029lw_r30: R3_TO_LWREG (30); 1030#ifdef CONFIG_MMU 1031lw_r31: R3_TO_LWREG_V (31); 1032#else 1033lw_r31: R3_TO_LWREG (31); 1034#endif 1035 1036sw_table: 1037sw_r0: SWREG_TO_R3 (0); 1038sw_r1: SWREG_NOP; 1039sw_r2: SWREG_TO_R3 (2); 1040sw_r3: SWREG_TO_R3_V (3); 1041sw_r4: SWREG_TO_R3_V (4); 1042sw_r5: SWREG_TO_R3_V (5); 1043sw_r6: SWREG_TO_R3_V (6); 1044sw_r7: SWREG_TO_R3 (7); 1045sw_r8: SWREG_TO_R3 (8); 1046sw_r9: SWREG_TO_R3 (9); 1047sw_r10: SWREG_TO_R3 (10); 1048sw_r11: SWREG_TO_R3 (11); 1049sw_r12: SWREG_TO_R3 (12); 1050sw_r13: SWREG_TO_R3 (13); 1051sw_r14: SWREG_TO_R3 (14); 1052sw_r15: SWREG_TO_R3 (15); 1053sw_r16: SWREG_TO_R3 (16); 1054sw_r17: SWREG_NOP; 1055sw_r18: SWREG_TO_R3 (18); 1056sw_r19: SWREG_TO_R3 (19); 1057sw_r20: SWREG_TO_R3 (20); 1058sw_r21: SWREG_TO_R3 (21); 1059sw_r22: SWREG_TO_R3 (22); 1060sw_r23: SWREG_TO_R3 (23); 1061sw_r24: SWREG_TO_R3 (24); 1062sw_r25: SWREG_TO_R3 (25); 1063sw_r26: SWREG_TO_R3 (26); 1064sw_r27: SWREG_TO_R3 (27); 1065sw_r28: SWREG_TO_R3 (28); 1066sw_r29: SWREG_TO_R3 (29); 1067sw_r30: SWREG_TO_R3 (30); 1068#ifdef CONFIG_MMU 1069sw_r31: SWREG_TO_R3_V (31); 1070#else 1071sw_r31: SWREG_TO_R3 (31); 1072#endif 1073 1074#ifdef CONFIG_MMU 1075lw_table_vm: 1076lw_r0_vm: R3_TO_LWREG_VM (0); 1077lw_r1_vm: R3_TO_LWREG_VM_V (1); 1078lw_r2_vm: R3_TO_LWREG_VM_V (2); 1079lw_r3_vm: R3_TO_LWREG_VM_V (3); 1080lw_r4_vm: R3_TO_LWREG_VM_V (4); 1081lw_r5_vm: R3_TO_LWREG_VM_V (5); 1082lw_r6_vm: R3_TO_LWREG_VM_V (6); 1083lw_r7_vm: R3_TO_LWREG_VM_V (7); 1084lw_r8_vm: R3_TO_LWREG_VM_V (8); 1085lw_r9_vm: R3_TO_LWREG_VM_V (9); 1086lw_r10_vm: R3_TO_LWREG_VM_V (10); 1087lw_r11_vm: R3_TO_LWREG_VM_V (11); 1088lw_r12_vm: R3_TO_LWREG_VM_V (12); 1089lw_r13_vm: R3_TO_LWREG_VM_V (13); 1090lw_r14_vm: R3_TO_LWREG_VM (14); 1091lw_r15_vm: R3_TO_LWREG_VM_V (15); 1092lw_r16_vm: R3_TO_LWREG_VM (16); 1093lw_r17_vm: R3_TO_LWREG_VM_V (17); 1094lw_r18_vm: R3_TO_LWREG_VM_V (18); 1095lw_r19_vm: R3_TO_LWREG_VM (19); 1096lw_r20_vm: R3_TO_LWREG_VM (20); 1097lw_r21_vm: R3_TO_LWREG_VM (21); 1098lw_r22_vm: R3_TO_LWREG_VM (22); 1099lw_r23_vm: R3_TO_LWREG_VM (23); 1100lw_r24_vm: R3_TO_LWREG_VM (24); 1101lw_r25_vm: R3_TO_LWREG_VM (25); 1102lw_r26_vm: R3_TO_LWREG_VM (26); 1103lw_r27_vm: R3_TO_LWREG_VM (27); 1104lw_r28_vm: R3_TO_LWREG_VM (28); 1105lw_r29_vm: R3_TO_LWREG_VM (29); 1106lw_r30_vm: R3_TO_LWREG_VM (30); 1107lw_r31_vm: R3_TO_LWREG_VM_V (31); 1108 1109sw_table_vm: 1110sw_r0_vm: SWREG_TO_R3_VM (0); 1111sw_r1_vm: SWREG_TO_R3_VM_V (1); 1112sw_r2_vm: SWREG_TO_R3_VM_V (2); 1113sw_r3_vm: SWREG_TO_R3_VM_V (3); 1114sw_r4_vm: SWREG_TO_R3_VM_V (4); 1115sw_r5_vm: SWREG_TO_R3_VM_V (5); 1116sw_r6_vm: SWREG_TO_R3_VM_V (6); 1117sw_r7_vm: SWREG_TO_R3_VM_V (7); 1118sw_r8_vm: SWREG_TO_R3_VM_V (8); 1119sw_r9_vm: SWREG_TO_R3_VM_V (9); 1120sw_r10_vm: SWREG_TO_R3_VM_V (10); 1121sw_r11_vm: SWREG_TO_R3_VM_V (11); 1122sw_r12_vm: SWREG_TO_R3_VM_V (12); 1123sw_r13_vm: SWREG_TO_R3_VM_V (13); 1124sw_r14_vm: SWREG_TO_R3_VM (14); 1125sw_r15_vm: SWREG_TO_R3_VM_V (15); 1126sw_r16_vm: SWREG_TO_R3_VM (16); 1127sw_r17_vm: SWREG_TO_R3_VM_V (17); 1128sw_r18_vm: SWREG_TO_R3_VM_V (18); 1129sw_r19_vm: SWREG_TO_R3_VM (19); 1130sw_r20_vm: SWREG_TO_R3_VM (20); 1131sw_r21_vm: SWREG_TO_R3_VM (21); 1132sw_r22_vm: SWREG_TO_R3_VM (22); 1133sw_r23_vm: SWREG_TO_R3_VM (23); 1134sw_r24_vm: SWREG_TO_R3_VM (24); 1135sw_r25_vm: SWREG_TO_R3_VM (25); 1136sw_r26_vm: SWREG_TO_R3_VM (26); 1137sw_r27_vm: SWREG_TO_R3_VM (27); 1138sw_r28_vm: SWREG_TO_R3_VM (28); 1139sw_r29_vm: SWREG_TO_R3_VM (29); 1140sw_r30_vm: SWREG_TO_R3_VM (30); 1141sw_r31_vm: SWREG_TO_R3_VM_V (31); 1142#endif /* CONFIG_MMU */ 1143 1144/* Temporary data structures used in the handler */ 1145.section .data 1146.align 4 1147ex_tmp_data_loc_0: 1148 .byte 0 1149ex_tmp_data_loc_1: 1150 .byte 0 1151ex_tmp_data_loc_2: 1152 .byte 0 1153ex_tmp_data_loc_3: 1154 .byte 0 1155ex_reg_op: 1156 .byte 0 1157