1/* 2 * arch/m68k/q40/config.c 3 * 4 * Copyright (C) 1999 Richard Zidlicky 5 * 6 * originally based on: 7 * 8 * linux/bvme/config.c 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file README.legal in the main directory of this archive 12 * for more details. 13 */ 14 15#include <linux/types.h> 16#include <linux/kernel.h> 17#include <linux/mm.h> 18#include <linux/tty.h> 19#include <linux/console.h> 20#include <linux/linkage.h> 21#include <linux/init.h> 22#include <linux/major.h> 23#include <linux/serial_reg.h> 24#include <linux/rtc.h> 25#include <linux/vt_kern.h> 26#include <linux/bcd.h> 27 28#include <asm/io.h> 29#include <asm/rtc.h> 30#include <asm/bootinfo.h> 31#include <asm/system.h> 32#include <asm/pgtable.h> 33#include <asm/setup.h> 34#include <asm/irq.h> 35#include <asm/traps.h> 36#include <asm/machdep.h> 37#include <asm/q40_master.h> 38 39extern void q40_init_IRQ(void); 40static void q40_get_model(char *model); 41extern void q40_sched_init(irq_handler_t handler); 42 43static unsigned long q40_gettimeoffset(void); 44static int q40_hwclk(int, struct rtc_time *); 45static unsigned int q40_get_ss(void); 46static int q40_set_clock_mmss(unsigned long); 47static int q40_get_rtc_pll(struct rtc_pll_info *pll); 48static int q40_set_rtc_pll(struct rtc_pll_info *pll); 49 50extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/); 51 52static void q40_mem_console_write(struct console *co, const char *b, 53 unsigned int count); 54 55extern int ql_ticks; 56 57static struct console q40_console_driver = { 58 .name = "debug", 59 .write = q40_mem_console_write, 60 .flags = CON_PRINTBUFFER, 61 .index = -1, 62}; 63 64 65/* early debugging function:*/ 66extern char *q40_mem_cptr; /*=(char *)0xff020000;*/ 67static int _cpleft; 68 69static void q40_mem_console_write(struct console *co, const char *s, 70 unsigned int count) 71{ 72 const char *p = s; 73 74 if (count < _cpleft) { 75 while (count-- > 0) { 76 *q40_mem_cptr = *p++; 77 q40_mem_cptr += 4; 78 _cpleft--; 79 } 80 } 81} 82 83static int __init q40_debug_setup(char *arg) 84{ 85 /* useful for early debugging stages - writes kernel messages into SRAM */ 86 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) { 87 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/ 88 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4; 89 register_console(&q40_console_driver); 90 } 91 return 0; 92} 93 94early_param("debug", q40_debug_setup); 95 96 97static int halted; 98 99#ifdef CONFIG_HEARTBEAT 100static void q40_heartbeat(int on) 101{ 102 if (halted) 103 return; 104 105 if (on) 106 Q40_LED_ON(); 107 else 108 Q40_LED_OFF(); 109} 110#endif 111 112static void q40_reset(void) 113{ 114 halted = 1; 115 printk("\n\n*******************************************\n" 116 "Called q40_reset : press the RESET button!!\n" 117 "*******************************************\n"); 118 Q40_LED_ON(); 119 while (1) 120 ; 121} 122 123static void q40_halt(void) 124{ 125 halted = 1; 126 printk("\n\n*******************\n" 127 " Called q40_halt\n" 128 "*******************\n"); 129 Q40_LED_ON(); 130 while (1) 131 ; 132} 133 134static void q40_get_model(char *model) 135{ 136 sprintf(model, "Q40"); 137} 138 139static unsigned int serports[] = 140{ 141 0x3f8,0x2f8,0x3e8,0x2e8,0 142}; 143 144static void q40_disable_irqs(void) 145{ 146 unsigned i, j; 147 148 j = 0; 149 while ((i = serports[j++])) 150 outb(0, i + UART_IER); 151 master_outb(0, EXT_ENABLE_REG); 152 master_outb(0, KEY_IRQ_ENABLE_REG); 153} 154 155void __init config_q40(void) 156{ 157 mach_sched_init = q40_sched_init; 158 159 mach_init_IRQ = q40_init_IRQ; 160 mach_gettimeoffset = q40_gettimeoffset; 161 mach_hwclk = q40_hwclk; 162 mach_get_ss = q40_get_ss; 163 mach_get_rtc_pll = q40_get_rtc_pll; 164 mach_set_rtc_pll = q40_set_rtc_pll; 165 mach_set_clock_mmss = q40_set_clock_mmss; 166 167 mach_reset = q40_reset; 168 mach_get_model = q40_get_model; 169 170#if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE) 171 mach_beep = q40_mksound; 172#endif 173#ifdef CONFIG_HEARTBEAT 174 mach_heartbeat = q40_heartbeat; 175#endif 176 mach_halt = q40_halt; 177 178 /* disable a few things that SMSQ might have left enabled */ 179 q40_disable_irqs(); 180 181 /* no DMA at all, but ide-scsi requires it.. make sure 182 * all physical RAM fits into the boundary - otherwise 183 * allocator may play costly and useless tricks */ 184 mach_max_dma_address = 1024*1024*1024; 185} 186 187 188int q40_parse_bootinfo(const struct bi_record *rec) 189{ 190 return 1; 191} 192 193 194static unsigned long q40_gettimeoffset(void) 195{ 196 return 5000 * (ql_ticks != 0); 197} 198 199 200/* 201 * Looks like op is non-zero for setting the clock, and zero for 202 * reading the clock. 203 * 204 * struct hwclk_time { 205 * unsigned sec; 0..59 206 * unsigned min; 0..59 207 * unsigned hour; 0..23 208 * unsigned day; 1..31 209 * unsigned mon; 0..11 210 * unsigned year; 00... 211 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set 212 * }; 213 */ 214 215static int q40_hwclk(int op, struct rtc_time *t) 216{ 217 if (op) { 218 /* Write.... */ 219 Q40_RTC_CTRL |= Q40_RTC_WRITE; 220 221 Q40_RTC_SECS = bin2bcd(t->tm_sec); 222 Q40_RTC_MINS = bin2bcd(t->tm_min); 223 Q40_RTC_HOUR = bin2bcd(t->tm_hour); 224 Q40_RTC_DATE = bin2bcd(t->tm_mday); 225 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1); 226 Q40_RTC_YEAR = bin2bcd(t->tm_year%100); 227 if (t->tm_wday >= 0) 228 Q40_RTC_DOW = bin2bcd(t->tm_wday+1); 229 230 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 231 } else { 232 /* Read.... */ 233 Q40_RTC_CTRL |= Q40_RTC_READ; 234 235 t->tm_year = bcd2bin (Q40_RTC_YEAR); 236 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1; 237 t->tm_mday = bcd2bin (Q40_RTC_DATE); 238 t->tm_hour = bcd2bin (Q40_RTC_HOUR); 239 t->tm_min = bcd2bin (Q40_RTC_MINS); 240 t->tm_sec = bcd2bin (Q40_RTC_SECS); 241 242 Q40_RTC_CTRL &= ~(Q40_RTC_READ); 243 244 if (t->tm_year < 70) 245 t->tm_year += 100; 246 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1; 247 } 248 249 return 0; 250} 251 252static unsigned int q40_get_ss(void) 253{ 254 return bcd2bin(Q40_RTC_SECS); 255} 256 257/* 258 * Set the minutes and seconds from seconds value 'nowtime'. Fail if 259 * clock is out by > 30 minutes. Logic lifted from atari code. 260 */ 261 262static int q40_set_clock_mmss(unsigned long nowtime) 263{ 264 int retval = 0; 265 short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60; 266 267 int rtc_minutes; 268 269 rtc_minutes = bcd2bin(Q40_RTC_MINS); 270 271 if ((rtc_minutes < real_minutes ? 272 real_minutes - rtc_minutes : 273 rtc_minutes - real_minutes) < 30) { 274 Q40_RTC_CTRL |= Q40_RTC_WRITE; 275 Q40_RTC_MINS = bin2bcd(real_minutes); 276 Q40_RTC_SECS = bin2bcd(real_seconds); 277 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 278 } else 279 retval = -1; 280 281 return retval; 282} 283 284 285/* get and set PLL calibration of RTC clock */ 286#define Q40_RTC_PLL_MASK ((1<<5)-1) 287#define Q40_RTC_PLL_SIGN (1<<5) 288 289static int q40_get_rtc_pll(struct rtc_pll_info *pll) 290{ 291 int tmp = Q40_RTC_CTRL; 292 293 pll->pll_value = tmp & Q40_RTC_PLL_MASK; 294 if (tmp & Q40_RTC_PLL_SIGN) 295 pll->pll_value = -pll->pll_value; 296 pll->pll_max = 31; 297 pll->pll_min = -31; 298 pll->pll_posmult = 512; 299 pll->pll_negmult = 256; 300 pll->pll_clock = 125829120; 301 302 return 0; 303} 304 305static int q40_set_rtc_pll(struct rtc_pll_info *pll) 306{ 307 if (!pll->pll_ctrl) { 308 /* the docs are a bit unclear so I am doublesetting */ 309 /* RTC_WRITE here ... */ 310 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | 311 Q40_RTC_WRITE; 312 Q40_RTC_CTRL |= Q40_RTC_WRITE; 313 Q40_RTC_CTRL = tmp; 314 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 315 return 0; 316 } else 317 return -EINVAL; 318} 319