1#ifndef __iop_sw_cpu_defs_h 2#define __iop_sw_cpu_defs_h 3 4/* 5 * This file is autogenerated from 6 * file: iop_sw_cpu.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13/* Main access macros */ 14#ifndef REG_RD 15#define REG_RD( scope, inst, reg ) \ 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 18#endif 19 20#ifndef REG_WR 21#define REG_WR( scope, inst, reg, val ) \ 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 24#endif 25 26#ifndef REG_RD_VECT 27#define REG_RD_VECT( scope, inst, reg, index ) \ 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) 31#endif 32 33#ifndef REG_WR_VECT 34#define REG_WR_VECT( scope, inst, reg, index, val ) \ 35 REG_WRITE( reg_##scope##_##reg, \ 36 (inst) + REG_WR_ADDR_##scope##_##reg + \ 37 (index) * STRIDE_##scope##_##reg, (val) ) 38#endif 39 40#ifndef REG_RD_INT 41#define REG_RD_INT( scope, inst, reg ) \ 42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 43#endif 44 45#ifndef REG_WR_INT 46#define REG_WR_INT( scope, inst, reg, val ) \ 47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 48#endif 49 50#ifndef REG_RD_INT_VECT 51#define REG_RD_INT_VECT( scope, inst, reg, index ) \ 52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 53 (index) * STRIDE_##scope##_##reg ) 54#endif 55 56#ifndef REG_WR_INT_VECT 57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 59 (index) * STRIDE_##scope##_##reg, (val) ) 60#endif 61 62#ifndef REG_TYPE_CONV 63#define REG_TYPE_CONV( type, orgtype, val ) \ 64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 65#endif 66 67#ifndef reg_page_size 68#define reg_page_size 8192 69#endif 70 71#ifndef REG_ADDR 72#define REG_ADDR( scope, inst, reg ) \ 73 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 74#endif 75 76#ifndef REG_ADDR_VECT 77#define REG_ADDR_VECT( scope, inst, reg, index ) \ 78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 79 (index) * STRIDE_##scope##_##reg ) 80#endif 81 82/* C-code for register scope iop_sw_cpu */ 83 84/* Register r_mpu_trace, scope iop_sw_cpu, type r */ 85typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; 86#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 87 88/* Register r_spu_trace, scope iop_sw_cpu, type r */ 89typedef unsigned int reg_iop_sw_cpu_r_spu_trace; 90#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 91 92/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ 93typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; 94#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 95 96/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ 97typedef struct { 98 unsigned int keep_owner : 1; 99 unsigned int cmd : 2; 100 unsigned int size : 3; 101 unsigned int wr_spu_mem : 1; 102 unsigned int dummy1 : 25; 103} reg_iop_sw_cpu_rw_mc_ctrl; 104#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 105#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 106 107/* Register rw_mc_data, scope iop_sw_cpu, type rw */ 108typedef struct { 109 unsigned int val : 32; 110} reg_iop_sw_cpu_rw_mc_data; 111#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 112#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 113 114/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ 115typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; 116#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 117#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 118 119/* Register rs_mc_data, scope iop_sw_cpu, type rs */ 120typedef unsigned int reg_iop_sw_cpu_rs_mc_data; 121#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 122 123/* Register r_mc_data, scope iop_sw_cpu, type r */ 124typedef unsigned int reg_iop_sw_cpu_r_mc_data; 125#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 126 127/* Register r_mc_stat, scope iop_sw_cpu, type r */ 128typedef struct { 129 unsigned int busy_cpu : 1; 130 unsigned int busy_mpu : 1; 131 unsigned int busy_spu : 1; 132 unsigned int owned_by_cpu : 1; 133 unsigned int owned_by_mpu : 1; 134 unsigned int owned_by_spu : 1; 135 unsigned int dummy1 : 26; 136} reg_iop_sw_cpu_r_mc_stat; 137#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 138 139/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ 140typedef struct { 141 unsigned int byte0 : 8; 142 unsigned int byte1 : 8; 143 unsigned int byte2 : 8; 144 unsigned int byte3 : 8; 145} reg_iop_sw_cpu_rw_bus_clr_mask; 146#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 147#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 148 149/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ 150typedef struct { 151 unsigned int byte0 : 8; 152 unsigned int byte1 : 8; 153 unsigned int byte2 : 8; 154 unsigned int byte3 : 8; 155} reg_iop_sw_cpu_rw_bus_set_mask; 156#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 157#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 158 159/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ 160typedef struct { 161 unsigned int byte0 : 1; 162 unsigned int byte1 : 1; 163 unsigned int byte2 : 1; 164 unsigned int byte3 : 1; 165 unsigned int dummy1 : 28; 166} reg_iop_sw_cpu_rw_bus_oe_clr_mask; 167#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 168#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 169 170/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ 171typedef struct { 172 unsigned int byte0 : 1; 173 unsigned int byte1 : 1; 174 unsigned int byte2 : 1; 175 unsigned int byte3 : 1; 176 unsigned int dummy1 : 28; 177} reg_iop_sw_cpu_rw_bus_oe_set_mask; 178#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 179#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 180 181/* Register r_bus_in, scope iop_sw_cpu, type r */ 182typedef unsigned int reg_iop_sw_cpu_r_bus_in; 183#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 184 185/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ 186typedef struct { 187 unsigned int val : 32; 188} reg_iop_sw_cpu_rw_gio_clr_mask; 189#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 190#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 191 192/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ 193typedef struct { 194 unsigned int val : 32; 195} reg_iop_sw_cpu_rw_gio_set_mask; 196#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 197#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 198 199/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ 200typedef struct { 201 unsigned int val : 32; 202} reg_iop_sw_cpu_rw_gio_oe_clr_mask; 203#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 204#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 205 206/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ 207typedef struct { 208 unsigned int val : 32; 209} reg_iop_sw_cpu_rw_gio_oe_set_mask; 210#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 211#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 212 213/* Register r_gio_in, scope iop_sw_cpu, type r */ 214typedef unsigned int reg_iop_sw_cpu_r_gio_in; 215#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 216 217/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ 218typedef struct { 219 unsigned int mpu_0 : 1; 220 unsigned int mpu_1 : 1; 221 unsigned int mpu_2 : 1; 222 unsigned int mpu_3 : 1; 223 unsigned int mpu_4 : 1; 224 unsigned int mpu_5 : 1; 225 unsigned int mpu_6 : 1; 226 unsigned int mpu_7 : 1; 227 unsigned int mpu_8 : 1; 228 unsigned int mpu_9 : 1; 229 unsigned int mpu_10 : 1; 230 unsigned int mpu_11 : 1; 231 unsigned int mpu_12 : 1; 232 unsigned int mpu_13 : 1; 233 unsigned int mpu_14 : 1; 234 unsigned int mpu_15 : 1; 235 unsigned int spu_0 : 1; 236 unsigned int spu_1 : 1; 237 unsigned int spu_2 : 1; 238 unsigned int spu_3 : 1; 239 unsigned int spu_4 : 1; 240 unsigned int spu_5 : 1; 241 unsigned int spu_6 : 1; 242 unsigned int spu_7 : 1; 243 unsigned int spu_8 : 1; 244 unsigned int spu_9 : 1; 245 unsigned int spu_10 : 1; 246 unsigned int spu_11 : 1; 247 unsigned int spu_12 : 1; 248 unsigned int spu_13 : 1; 249 unsigned int spu_14 : 1; 250 unsigned int spu_15 : 1; 251} reg_iop_sw_cpu_rw_intr0_mask; 252#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 253#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 254 255/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ 256typedef struct { 257 unsigned int mpu_0 : 1; 258 unsigned int mpu_1 : 1; 259 unsigned int mpu_2 : 1; 260 unsigned int mpu_3 : 1; 261 unsigned int mpu_4 : 1; 262 unsigned int mpu_5 : 1; 263 unsigned int mpu_6 : 1; 264 unsigned int mpu_7 : 1; 265 unsigned int mpu_8 : 1; 266 unsigned int mpu_9 : 1; 267 unsigned int mpu_10 : 1; 268 unsigned int mpu_11 : 1; 269 unsigned int mpu_12 : 1; 270 unsigned int mpu_13 : 1; 271 unsigned int mpu_14 : 1; 272 unsigned int mpu_15 : 1; 273 unsigned int spu_0 : 1; 274 unsigned int spu_1 : 1; 275 unsigned int spu_2 : 1; 276 unsigned int spu_3 : 1; 277 unsigned int spu_4 : 1; 278 unsigned int spu_5 : 1; 279 unsigned int spu_6 : 1; 280 unsigned int spu_7 : 1; 281 unsigned int spu_8 : 1; 282 unsigned int spu_9 : 1; 283 unsigned int spu_10 : 1; 284 unsigned int spu_11 : 1; 285 unsigned int spu_12 : 1; 286 unsigned int spu_13 : 1; 287 unsigned int spu_14 : 1; 288 unsigned int spu_15 : 1; 289} reg_iop_sw_cpu_rw_ack_intr0; 290#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 291#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 292 293/* Register r_intr0, scope iop_sw_cpu, type r */ 294typedef struct { 295 unsigned int mpu_0 : 1; 296 unsigned int mpu_1 : 1; 297 unsigned int mpu_2 : 1; 298 unsigned int mpu_3 : 1; 299 unsigned int mpu_4 : 1; 300 unsigned int mpu_5 : 1; 301 unsigned int mpu_6 : 1; 302 unsigned int mpu_7 : 1; 303 unsigned int mpu_8 : 1; 304 unsigned int mpu_9 : 1; 305 unsigned int mpu_10 : 1; 306 unsigned int mpu_11 : 1; 307 unsigned int mpu_12 : 1; 308 unsigned int mpu_13 : 1; 309 unsigned int mpu_14 : 1; 310 unsigned int mpu_15 : 1; 311 unsigned int spu_0 : 1; 312 unsigned int spu_1 : 1; 313 unsigned int spu_2 : 1; 314 unsigned int spu_3 : 1; 315 unsigned int spu_4 : 1; 316 unsigned int spu_5 : 1; 317 unsigned int spu_6 : 1; 318 unsigned int spu_7 : 1; 319 unsigned int spu_8 : 1; 320 unsigned int spu_9 : 1; 321 unsigned int spu_10 : 1; 322 unsigned int spu_11 : 1; 323 unsigned int spu_12 : 1; 324 unsigned int spu_13 : 1; 325 unsigned int spu_14 : 1; 326 unsigned int spu_15 : 1; 327} reg_iop_sw_cpu_r_intr0; 328#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 329 330/* Register r_masked_intr0, scope iop_sw_cpu, type r */ 331typedef struct { 332 unsigned int mpu_0 : 1; 333 unsigned int mpu_1 : 1; 334 unsigned int mpu_2 : 1; 335 unsigned int mpu_3 : 1; 336 unsigned int mpu_4 : 1; 337 unsigned int mpu_5 : 1; 338 unsigned int mpu_6 : 1; 339 unsigned int mpu_7 : 1; 340 unsigned int mpu_8 : 1; 341 unsigned int mpu_9 : 1; 342 unsigned int mpu_10 : 1; 343 unsigned int mpu_11 : 1; 344 unsigned int mpu_12 : 1; 345 unsigned int mpu_13 : 1; 346 unsigned int mpu_14 : 1; 347 unsigned int mpu_15 : 1; 348 unsigned int spu_0 : 1; 349 unsigned int spu_1 : 1; 350 unsigned int spu_2 : 1; 351 unsigned int spu_3 : 1; 352 unsigned int spu_4 : 1; 353 unsigned int spu_5 : 1; 354 unsigned int spu_6 : 1; 355 unsigned int spu_7 : 1; 356 unsigned int spu_8 : 1; 357 unsigned int spu_9 : 1; 358 unsigned int spu_10 : 1; 359 unsigned int spu_11 : 1; 360 unsigned int spu_12 : 1; 361 unsigned int spu_13 : 1; 362 unsigned int spu_14 : 1; 363 unsigned int spu_15 : 1; 364} reg_iop_sw_cpu_r_masked_intr0; 365#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 366 367/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ 368typedef struct { 369 unsigned int mpu_16 : 1; 370 unsigned int mpu_17 : 1; 371 unsigned int mpu_18 : 1; 372 unsigned int mpu_19 : 1; 373 unsigned int mpu_20 : 1; 374 unsigned int mpu_21 : 1; 375 unsigned int mpu_22 : 1; 376 unsigned int mpu_23 : 1; 377 unsigned int mpu_24 : 1; 378 unsigned int mpu_25 : 1; 379 unsigned int mpu_26 : 1; 380 unsigned int mpu_27 : 1; 381 unsigned int mpu_28 : 1; 382 unsigned int mpu_29 : 1; 383 unsigned int mpu_30 : 1; 384 unsigned int mpu_31 : 1; 385 unsigned int dmc_in : 1; 386 unsigned int dmc_out : 1; 387 unsigned int fifo_in : 1; 388 unsigned int fifo_out : 1; 389 unsigned int fifo_in_extra : 1; 390 unsigned int fifo_out_extra : 1; 391 unsigned int trigger_grp0 : 1; 392 unsigned int trigger_grp1 : 1; 393 unsigned int trigger_grp2 : 1; 394 unsigned int trigger_grp3 : 1; 395 unsigned int trigger_grp4 : 1; 396 unsigned int trigger_grp5 : 1; 397 unsigned int trigger_grp6 : 1; 398 unsigned int trigger_grp7 : 1; 399 unsigned int timer_grp0 : 1; 400 unsigned int timer_grp1 : 1; 401} reg_iop_sw_cpu_rw_intr1_mask; 402#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 403#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 404 405/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ 406typedef struct { 407 unsigned int mpu_16 : 1; 408 unsigned int mpu_17 : 1; 409 unsigned int mpu_18 : 1; 410 unsigned int mpu_19 : 1; 411 unsigned int mpu_20 : 1; 412 unsigned int mpu_21 : 1; 413 unsigned int mpu_22 : 1; 414 unsigned int mpu_23 : 1; 415 unsigned int mpu_24 : 1; 416 unsigned int mpu_25 : 1; 417 unsigned int mpu_26 : 1; 418 unsigned int mpu_27 : 1; 419 unsigned int mpu_28 : 1; 420 unsigned int mpu_29 : 1; 421 unsigned int mpu_30 : 1; 422 unsigned int mpu_31 : 1; 423 unsigned int dummy1 : 16; 424} reg_iop_sw_cpu_rw_ack_intr1; 425#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 426#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 427 428/* Register r_intr1, scope iop_sw_cpu, type r */ 429typedef struct { 430 unsigned int mpu_16 : 1; 431 unsigned int mpu_17 : 1; 432 unsigned int mpu_18 : 1; 433 unsigned int mpu_19 : 1; 434 unsigned int mpu_20 : 1; 435 unsigned int mpu_21 : 1; 436 unsigned int mpu_22 : 1; 437 unsigned int mpu_23 : 1; 438 unsigned int mpu_24 : 1; 439 unsigned int mpu_25 : 1; 440 unsigned int mpu_26 : 1; 441 unsigned int mpu_27 : 1; 442 unsigned int mpu_28 : 1; 443 unsigned int mpu_29 : 1; 444 unsigned int mpu_30 : 1; 445 unsigned int mpu_31 : 1; 446 unsigned int dmc_in : 1; 447 unsigned int dmc_out : 1; 448 unsigned int fifo_in : 1; 449 unsigned int fifo_out : 1; 450 unsigned int fifo_in_extra : 1; 451 unsigned int fifo_out_extra : 1; 452 unsigned int trigger_grp0 : 1; 453 unsigned int trigger_grp1 : 1; 454 unsigned int trigger_grp2 : 1; 455 unsigned int trigger_grp3 : 1; 456 unsigned int trigger_grp4 : 1; 457 unsigned int trigger_grp5 : 1; 458 unsigned int trigger_grp6 : 1; 459 unsigned int trigger_grp7 : 1; 460 unsigned int timer_grp0 : 1; 461 unsigned int timer_grp1 : 1; 462} reg_iop_sw_cpu_r_intr1; 463#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 464 465/* Register r_masked_intr1, scope iop_sw_cpu, type r */ 466typedef struct { 467 unsigned int mpu_16 : 1; 468 unsigned int mpu_17 : 1; 469 unsigned int mpu_18 : 1; 470 unsigned int mpu_19 : 1; 471 unsigned int mpu_20 : 1; 472 unsigned int mpu_21 : 1; 473 unsigned int mpu_22 : 1; 474 unsigned int mpu_23 : 1; 475 unsigned int mpu_24 : 1; 476 unsigned int mpu_25 : 1; 477 unsigned int mpu_26 : 1; 478 unsigned int mpu_27 : 1; 479 unsigned int mpu_28 : 1; 480 unsigned int mpu_29 : 1; 481 unsigned int mpu_30 : 1; 482 unsigned int mpu_31 : 1; 483 unsigned int dmc_in : 1; 484 unsigned int dmc_out : 1; 485 unsigned int fifo_in : 1; 486 unsigned int fifo_out : 1; 487 unsigned int fifo_in_extra : 1; 488 unsigned int fifo_out_extra : 1; 489 unsigned int trigger_grp0 : 1; 490 unsigned int trigger_grp1 : 1; 491 unsigned int trigger_grp2 : 1; 492 unsigned int trigger_grp3 : 1; 493 unsigned int trigger_grp4 : 1; 494 unsigned int trigger_grp5 : 1; 495 unsigned int trigger_grp6 : 1; 496 unsigned int trigger_grp7 : 1; 497 unsigned int timer_grp0 : 1; 498 unsigned int timer_grp1 : 1; 499} reg_iop_sw_cpu_r_masked_intr1; 500#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 501 502 503/* Constants */ 504enum { 505 regk_iop_sw_cpu_copy = 0x00000000, 506 regk_iop_sw_cpu_no = 0x00000000, 507 regk_iop_sw_cpu_rd = 0x00000002, 508 regk_iop_sw_cpu_reg_copy = 0x00000001, 509 regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, 510 regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, 511 regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, 512 regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, 513 regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, 514 regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, 515 regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, 516 regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, 517 regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, 518 regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, 519 regk_iop_sw_cpu_wr = 0x00000003, 520 regk_iop_sw_cpu_yes = 0x00000001 521}; 522#endif /* __iop_sw_cpu_defs_h */ 523