1/* 2 * the simple DMA Implementation for Blackfin 3 * 4 * Copyright 2008 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9#include <linux/module.h> 10 11#include <asm/blackfin.h> 12#include <asm/dma.h> 13 14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 18 (struct dma_register *) DMA3_NEXT_DESC_PTR, 19 (struct dma_register *) DMA4_NEXT_DESC_PTR, 20 (struct dma_register *) DMA5_NEXT_DESC_PTR, 21 (struct dma_register *) DMA6_NEXT_DESC_PTR, 22 (struct dma_register *) DMA7_NEXT_DESC_PTR, 23 (struct dma_register *) DMA8_NEXT_DESC_PTR, 24 (struct dma_register *) DMA9_NEXT_DESC_PTR, 25 (struct dma_register *) DMA10_NEXT_DESC_PTR, 26 (struct dma_register *) DMA11_NEXT_DESC_PTR, 27 (struct dma_register *) DMA12_NEXT_DESC_PTR, 28 (struct dma_register *) DMA13_NEXT_DESC_PTR, 29 (struct dma_register *) DMA14_NEXT_DESC_PTR, 30 (struct dma_register *) DMA15_NEXT_DESC_PTR, 31 (struct dma_register *) DMA16_NEXT_DESC_PTR, 32 (struct dma_register *) DMA17_NEXT_DESC_PTR, 33 (struct dma_register *) DMA18_NEXT_DESC_PTR, 34 (struct dma_register *) DMA19_NEXT_DESC_PTR, 35 (struct dma_register *) MDMA0_D0_NEXT_DESC_PTR, 36 (struct dma_register *) MDMA0_S0_NEXT_DESC_PTR, 37 (struct dma_register *) MDMA0_D1_NEXT_DESC_PTR, 38 (struct dma_register *) MDMA0_S1_NEXT_DESC_PTR, 39 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, 40 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, 41 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, 42 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, 43}; 44EXPORT_SYMBOL(dma_io_base_addr); 45 46int channel2irq(unsigned int channel) 47{ 48 int ret_irq = -1; 49 50 switch (channel) { 51 case CH_PPI: 52 ret_irq = IRQ_PPI; 53 break; 54 55 case CH_UART0_RX: 56 ret_irq = IRQ_UART0_RX; 57 break; 58 59 case CH_UART0_TX: 60 ret_irq = IRQ_UART0_TX; 61 break; 62 63 case CH_UART1_RX: 64 ret_irq = IRQ_UART1_RX; 65 break; 66 67 case CH_UART1_TX: 68 ret_irq = IRQ_UART1_TX; 69 break; 70 71 case CH_UART2_RX: 72 ret_irq = IRQ_UART2_RX; 73 break; 74 75 case CH_UART2_TX: 76 ret_irq = IRQ_UART2_TX; 77 break; 78 79 case CH_SPORT0_RX: 80 ret_irq = IRQ_SPORT0_RX; 81 break; 82 83 case CH_SPORT0_TX: 84 ret_irq = IRQ_SPORT0_TX; 85 break; 86 87 case CH_SPORT1_RX: 88 ret_irq = IRQ_SPORT1_RX; 89 break; 90 91 case CH_SPORT1_TX: 92 ret_irq = IRQ_SPORT1_TX; 93 break; 94 95 case CH_SPORT2_RX: 96 ret_irq = IRQ_SPORT2_RX; 97 break; 98 99 case CH_SPORT2_TX: 100 ret_irq = IRQ_SPORT2_TX; 101 break; 102 103 case CH_SPORT3_RX: 104 ret_irq = IRQ_SPORT3_RX; 105 break; 106 107 case CH_SPORT3_TX: 108 ret_irq = IRQ_SPORT3_TX; 109 break; 110 111 case CH_SPI0: 112 ret_irq = IRQ_SPI0; 113 break; 114 115 case CH_SPI1: 116 ret_irq = IRQ_SPI1; 117 break; 118 119 case CH_SPI2: 120 ret_irq = IRQ_SPI2; 121 break; 122 123 case CH_MEM_STREAM0_SRC: 124 case CH_MEM_STREAM0_DEST: 125 ret_irq = IRQ_MEM0_DMA0; 126 break; 127 case CH_MEM_STREAM1_SRC: 128 case CH_MEM_STREAM1_DEST: 129 ret_irq = IRQ_MEM0_DMA1; 130 break; 131 case CH_MEM_STREAM2_SRC: 132 case CH_MEM_STREAM2_DEST: 133 ret_irq = IRQ_MEM1_DMA0; 134 break; 135 case CH_MEM_STREAM3_SRC: 136 case CH_MEM_STREAM3_DEST: 137 ret_irq = IRQ_MEM1_DMA1; 138 break; 139 } 140 return ret_irq; 141} 142