1/* 2 * DO NOT EDIT THIS FILE 3 * This file is under version control at 4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ 5 * and can be replaced with that version at any time 6 * DO NOT EDIT THIS FILE 7 * 8 * Copyright 2004-2010 Analog Devices Inc. 9 * Licensed under the ADI BSD license. 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 11 */ 12 13/* This file should be up to date with: 14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List 15 * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List 16 */ 17 18#ifndef _MACH_ANOMALY_H_ 19#define _MACH_ANOMALY_H_ 20 21/* We do not support old silicon - sorry */ 22#if __SILICON_REVISION__ < 0 23# error will not work on BF526/BF527 silicon version 24#endif 25 26#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) 27# define ANOMALY_BF526 1 28#else 29# define ANOMALY_BF526 0 30#endif 31#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) 32# define ANOMALY_BF527 1 33#else 34# define ANOMALY_BF527 0 35#endif 36 37#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526) 38#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) 39#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) 40 41/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 42#define ANOMALY_05000074 (1) 43/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 44#define ANOMALY_05000119 (1) 45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 46#define ANOMALY_05000122 (1) 47/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 48#define ANOMALY_05000245 (1) 49/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 50#define ANOMALY_05000254 (1) 51/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 52#define ANOMALY_05000265 (1) 53/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 54#define ANOMALY_05000310 (1) 55/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 56#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2)) 57/* Incorrect Access of OTP_STATUS During otp_write() Function */ 58#define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) 59/* Host DMA Boot Modes Are Not Functional */ 60#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) 61/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 62#define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) 63/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 64#define ANOMALY_05000341 (_ANOMALY_BF527(< 2)) 65/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ 66#define ANOMALY_05000342 (_ANOMALY_BF527(< 2)) 67/* USB Calibration Value Is Not Initialized */ 68#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2)) 69/* USB Calibration Value to use */ 70#define ANOMALY_05000346_value 0xE510 71/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ 72#define ANOMALY_05000347 (_ANOMALY_BF527(< 2)) 73/* Security Features Are Not Functional */ 74#define ANOMALY_05000348 (_ANOMALY_BF527(< 1)) 75/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ 76#define ANOMALY_05000353 (_ANOMALY_BF526(< 1)) 77/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ 78#define ANOMALY_05000355 (_ANOMALY_BF527(< 2)) 79/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 80#define ANOMALY_05000357 (_ANOMALY_BF527(< 2)) 81/* Incorrect Revision Number in DSPID Register */ 82#define ANOMALY_05000364 (_ANOMALY_BF527(== 1)) 83/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 84#define ANOMALY_05000366 (1) 85/* Incorrect Default CSEL Value in PLL_DIV */ 86#define ANOMALY_05000368 (_ANOMALY_BF527(< 2)) 87/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 88#define ANOMALY_05000371 (_ANOMALY_BF527(< 2)) 89/* Authentication Fails To Initiate */ 90#define ANOMALY_05000376 (_ANOMALY_BF527(< 2)) 91/* Data Read From L3 Memory by USB DMA May be Corrupted */ 92#define ANOMALY_05000380 (_ANOMALY_BF527(< 2)) 93/* 8-Bit NAND Flash Boot Mode Not Functional */ 94#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2)) 95/* Boot from OTP Memory Not Functional */ 96#define ANOMALY_05000385 (_ANOMALY_BF527(< 2)) 97/* bfrom_SysControl() Firmware Routine Not Functional */ 98#define ANOMALY_05000386 (_ANOMALY_BF527(< 2)) 99/* Programmable Preboot Settings Not Functional */ 100#define ANOMALY_05000387 (_ANOMALY_BF527(< 2)) 101/* CRC32 Checksum Support Not Functional */ 102#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2)) 103/* Reset Vector Must Not Be in SDRAM Memory Space */ 104#define ANOMALY_05000389 (_ANOMALY_BF527(< 2)) 105/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ 106#define ANOMALY_05000392 (_ANOMALY_BF527(< 2)) 107/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ 108#define ANOMALY_05000393 (_ANOMALY_BF527(< 2)) 109/* Log Buffer Not Functional */ 110#define ANOMALY_05000394 (_ANOMALY_BF527(< 2)) 111/* Hook Routine Not Functional */ 112#define ANOMALY_05000395 (_ANOMALY_BF527(< 2)) 113/* Header Indirect Bit Not Functional */ 114#define ANOMALY_05000396 (_ANOMALY_BF527(< 2)) 115/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ 116#define ANOMALY_05000397 (_ANOMALY_BF527(< 2)) 117/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ 118#define ANOMALY_05000398 (_ANOMALY_BF527(< 2)) 119/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ 120#define ANOMALY_05000399 (_ANOMALY_BF527(< 2)) 121/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ 122#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2)) 123/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 124#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2)) 125/* Lockbox SESR Disallows Certain User Interrupts */ 126#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2)) 127/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ 128#define ANOMALY_05000405 (1) 129/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ 130#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2)) 131/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ 132#define ANOMALY_05000408 (1) 133/* Lockbox firmware leaves MDMA0 channel enabled */ 134#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2)) 135/* Incorrect Default Internal Voltage Regulator Setting */ 136#define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) 137/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ 138#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) 139/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ 140#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) 141/* DEB2_URGENT Bit Not Functional */ 142#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2)) 143/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 144#define ANOMALY_05000416 (1) 145/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ 146#define ANOMALY_05000417 (_ANOMALY_BF527(< 2)) 147/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ 148#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2)) 149/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ 150#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2)) 151/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ 152#define ANOMALY_05000421 (1) 153/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ 154#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1)) 155/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ 156#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2)) 157/* Internal Voltage Regulator Not Trimmed */ 158#define ANOMALY_05000424 (_ANOMALY_BF527(< 2)) 159/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ 160#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2)) 161/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 162#define ANOMALY_05000426 (1) 163/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ 164#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2)) 165/* Software System Reset Corrupts PLL_LOCKCNT Register */ 166#define ANOMALY_05000430 (_ANOMALY_BF527(> 1)) 167/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ 168#define ANOMALY_05000431 (1) 169/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ 170#define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) 171/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ 172#define ANOMALY_05000434 (1) 173/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 174#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) 175/* Preboot Cannot be Used to Alter the PLL_DIV Register */ 176#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0)) 177/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ 178#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0)) 179/* OTP Write Accesses Not Supported */ 180#define ANOMALY_05000442 (_ANOMALY_BF527(< 1)) 181/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 182#define ANOMALY_05000443 (1) 183/* The WURESET Bit in the SYSCR Register is not Functional */ 184#define ANOMALY_05000445 (1) 185/* USB DMA Mode 1 Short Packet Data Corruption */ 186#define ANOMALY_05000450 (1) 187/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ 188#define ANOMALY_05000451 (1) 189/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ 190#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) 191/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 192#define ANOMALY_05000456 (1) 193/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ 194#define ANOMALY_05000457 (1) 195/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ 196#define ANOMALY_05000460 (1) 197/* False Hardware Error when RETI Points to Invalid Memory */ 198#define ANOMALY_05000461 (1) 199/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 200#define ANOMALY_05000462 (1) 201/* USB Rx DMA hang */ 202#define ANOMALY_05000465 (1) 203/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ 204#define ANOMALY_05000466 (1) 205/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ 206#define ANOMALY_05000467 (1) 207/* PLL Latches Incorrect Settings During Reset */ 208#define ANOMALY_05000469 (1) 209/* Incorrect Default MSEL Value in PLL_CTL */ 210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) 211/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 212#define ANOMALY_05000473 (1) 213/* Possible Lockup Condition whem Modifying PLL from External Memory */ 214#define ANOMALY_05000475 (1) 215/* TESTSET Instruction Cannot Be Interrupted */ 216#define ANOMALY_05000477 (1) 217/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 218#define ANOMALY_05000481 (1) 219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ 220#define ANOMALY_05000483 (1) 221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) 223/* IFLUSH sucks at life */ 224#define ANOMALY_05000491 (1) 225 226/* Anomalies that don't exist on this proc */ 227#define ANOMALY_05000099 (0) 228#define ANOMALY_05000120 (0) 229#define ANOMALY_05000125 (0) 230#define ANOMALY_05000149 (0) 231#define ANOMALY_05000158 (0) 232#define ANOMALY_05000171 (0) 233#define ANOMALY_05000179 (0) 234#define ANOMALY_05000182 (0) 235#define ANOMALY_05000183 (0) 236#define ANOMALY_05000189 (0) 237#define ANOMALY_05000198 (0) 238#define ANOMALY_05000202 (0) 239#define ANOMALY_05000215 (0) 240#define ANOMALY_05000219 (0) 241#define ANOMALY_05000220 (0) 242#define ANOMALY_05000227 (0) 243#define ANOMALY_05000230 (0) 244#define ANOMALY_05000231 (0) 245#define ANOMALY_05000233 (0) 246#define ANOMALY_05000234 (0) 247#define ANOMALY_05000242 (0) 248#define ANOMALY_05000244 (0) 249#define ANOMALY_05000248 (0) 250#define ANOMALY_05000250 (0) 251#define ANOMALY_05000257 (0) 252#define ANOMALY_05000261 (0) 253#define ANOMALY_05000263 (0) 254#define ANOMALY_05000266 (0) 255#define ANOMALY_05000273 (0) 256#define ANOMALY_05000274 (0) 257#define ANOMALY_05000278 (0) 258#define ANOMALY_05000281 (0) 259#define ANOMALY_05000283 (0) 260#define ANOMALY_05000285 (0) 261#define ANOMALY_05000287 (0) 262#define ANOMALY_05000301 (0) 263#define ANOMALY_05000305 (0) 264#define ANOMALY_05000307 (0) 265#define ANOMALY_05000311 (0) 266#define ANOMALY_05000312 (0) 267#define ANOMALY_05000315 (0) 268#define ANOMALY_05000323 (0) 269#define ANOMALY_05000362 (1) 270#define ANOMALY_05000363 (0) 271#define ANOMALY_05000400 (0) 272#define ANOMALY_05000402 (0) 273#define ANOMALY_05000412 (0) 274#define ANOMALY_05000447 (0) 275#define ANOMALY_05000448 (0) 276#define ANOMALY_05000474 (0) 277 278#endif 279