1/* 2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. 3 * - Platform specific register memory map 4 * 5 * Copyright 2005-2007 Motorola, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17#ifndef __MACH_MXC91231_H__ 18#define __MACH_MXC91231_H__ 19 20/* 21 * L2CC 22 */ 23#define MXC91231_L2CC_BASE_ADDR 0x30000000 24#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 25#define MXC91231_L2CC_SIZE SZ_64K 26 27/* 28 * AIPS 1 29 */ 30#define MXC91231_AIPS1_BASE_ADDR 0x43F00000 31#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 32#define MXC91231_AIPS1_SIZE SZ_1M 33 34#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR 35#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000) 36#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000) 37#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000) 38#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000) 39#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000) 40#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000) 41#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000) 42#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000) 43#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000) 44#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000) 45#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000) 46#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000) 47#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000) 48#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000) 49#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000) 50#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000) 51 52/* 53 * AIPS 2 54 */ 55#define MXC91231_AIPS2_BASE_ADDR 0x53F00000 56#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 57#define MXC91231_AIPS2_SIZE SZ_1M 58 59#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) 60#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000) 61#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000) 62#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000) 63#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000) 64#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000) 65#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000) 66#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000) 67#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000) 68#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000) 69#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000) 70#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000) 71#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000) 72#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000) 73#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000) 74#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000) 75#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000) 76#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000) 77 78/* 79 * SPBA global module 0 80 */ 81#define MXC91231_SPBA0_BASE_ADDR 0x50000000 82#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 83#define MXC91231_SPBA0_SIZE SZ_1M 84 85#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) 86#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000) 87#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000) 88#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000) 89#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000) 90#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000) 91#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000) 92#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000) 93#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000) 94#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000) 95#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000) 96#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000) 97#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000) 98#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000) 99#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000) 100#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000) 101#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000) 102#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000) 103#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000) 104#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) 105#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) 106#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000) 107 108/* 109 * SPBA global module 1 110 */ 111#define MXC91231_SPBA1_BASE_ADDR 0x52000000 112#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 113#define MXC91231_SPBA1_SIZE SZ_1M 114 115#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) 116#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000) 117 118/*! 119 * Defines for SPBA modules 120 */ 121#define MXC91231_SPBA_SDHC1 0x04 122#define MXC91231_SPBA_SDHC2 0x08 123#define MXC91231_SPBA_UART3 0x0C 124#define MXC91231_SPBA_CSPI2 0x10 125#define MXC91231_SPBA_SSI2 0x14 126#define MXC91231_SPBA_SIM 0x18 127#define MXC91231_SPBA_IIM 0x1C 128#define MXC91231_SPBA_CTI_SDMA 0x20 129#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24 130#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28 131#define MXC91231_SPBA_CSPI1 0x30 132#define MXC91231_SPBA_MQSPI 0x34 133#define MXC91231_SPBA_EL1T 0x38 134#define MXC91231_SPBA_IOMUX 0x40 135#define MXC91231_SPBA_CRM_COM 0x44 136#define MXC91231_SPBA_CRM_AP 0x48 137#define MXC91231_SPBA_PLL0 0x4C 138#define MXC91231_SPBA_PLL1 0x50 139#define MXC91231_SPBA_PLL2 0x54 140#define MXC91231_SPBA_GPIO4 0x58 141#define MXC91231_SPBA_SAHARA 0x5C 142 143/* 144 * ROMP and AVIC 145 */ 146#define MXC91231_ROMP_BASE_ADDR 0x60000000 147#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 148#define MXC91231_ROMP_SIZE SZ_64K 149 150#define MXC91231_AVIC_BASE_ADDR 0x68000000 151#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 152#define MXC91231_AVIC_SIZE SZ_64K 153 154/* 155 * NAND, SDRAM, WEIM, M3IF, EMI controllers 156 */ 157#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 158#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 159#define MXC91231_X_MEMC_SIZE SZ_64K 160 161#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) 162#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000) 163#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000) 164#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000) 165#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000) 166 167/* 168 * Memory regions and CS 169 * CPLD is connected on CS4 170 * CS5 is TP1021 or it is not connected 171 * */ 172#define MXC91231_FB_RAM_BASE_ADDR 0x78000000 173#define MXC91231_FB_RAM_SIZE SZ_256K 174#define MXC91231_CSD0_BASE_ADDR 0x80000000 175#define MXC91231_CSD1_BASE_ADDR 0x90000000 176#define MXC91231_CS0_BASE_ADDR 0xA0000000 177#define MXC91231_CS1_BASE_ADDR 0xA8000000 178#define MXC91231_CS2_BASE_ADDR 0xB0000000 179#define MXC91231_CS3_BASE_ADDR 0xB2000000 180#define MXC91231_CS4_BASE_ADDR 0xB4000000 181#define MXC91231_CS5_BASE_ADDR 0xB6000000 182 183/* 184 * This macro defines the physical to virtual address mapping for all the 185 * peripheral modules. It is used by passing in the physical address as x 186 * and returning the virtual address. If the physical address is not mapped, 187 * it returns 0. 188 */ 189 190#define MXC91231_IO_ADDRESS(x) ( \ 191 IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ 192 IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ 193 IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ 194 IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ 195 IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ 196 IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ 197 IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ 198 IMX_IO_ADDRESS(x, MXC91231_AIPS2)) 199 200/* 201 * Interrupt numbers 202 */ 203#define MXC91231_INT_GPIO3 0 204#define MXC91231_INT_EL1T_CI 1 205#define MXC91231_INT_EL1T_RFCI 2 206#define MXC91231_INT_EL1T_RFI 3 207#define MXC91231_INT_EL1T_MCU 4 208#define MXC91231_INT_EL1T_IPI 5 209#define MXC91231_INT_MU_GEN 6 210#define MXC91231_INT_GPIO4 7 211#define MXC91231_INT_MMC_SDHC2 8 212#define MXC91231_INT_MMC_SDHC1 9 213#define MXC91231_INT_I2C 10 214#define MXC91231_INT_SSI2 11 215#define MXC91231_INT_SSI1 12 216#define MXC91231_INT_CSPI2 13 217#define MXC91231_INT_CSPI1 14 218#define MXC91231_INT_RTIC 15 219#define MXC91231_INT_SAHARA 15 220#define MXC91231_INT_HAC 15 221#define MXC91231_INT_UART3_RX 16 222#define MXC91231_INT_UART3_TX 17 223#define MXC91231_INT_UART3_MINT 18 224#define MXC91231_INT_ECT 19 225#define MXC91231_INT_SIM_IPB 20 226#define MXC91231_INT_SIM_DATA 21 227#define MXC91231_INT_RNGA 22 228#define MXC91231_INT_DSM_AP 23 229#define MXC91231_INT_KPP 24 230#define MXC91231_INT_RTC 25 231#define MXC91231_INT_PWM 26 232#define MXC91231_INT_GEMK_AP 27 233#define MXC91231_INT_EPIT 28 234#define MXC91231_INT_GPT 29 235#define MXC91231_INT_UART2_RX 30 236#define MXC91231_INT_UART2_TX 31 237#define MXC91231_INT_UART2_MINT 32 238#define MXC91231_INT_NANDFC 33 239#define MXC91231_INT_SDMA 34 240#define MXC91231_INT_USB_WAKEUP 35 241#define MXC91231_INT_USB_SOF 36 242#define MXC91231_INT_PMU_EVTMON 37 243#define MXC91231_INT_USB_FUNC 38 244#define MXC91231_INT_USB_DMA 39 245#define MXC91231_INT_USB_CTRL 40 246#define MXC91231_INT_IPU_ERR 41 247#define MXC91231_INT_IPU_SYN 42 248#define MXC91231_INT_UART1_RX 43 249#define MXC91231_INT_UART1_TX 44 250#define MXC91231_INT_UART1_MINT 45 251#define MXC91231_INT_IIM 46 252#define MXC91231_INT_MU_RX_OR 47 253#define MXC91231_INT_MU_TX_OR 48 254#define MXC91231_INT_SCC_SCM 49 255#define MXC91231_INT_SCC_SMN 50 256#define MXC91231_INT_GPIO2 51 257#define MXC91231_INT_GPIO1 52 258#define MXC91231_INT_MQSPI1 53 259#define MXC91231_INT_MQSPI2 54 260#define MXC91231_INT_WDOG2 55 261#define MXC91231_INT_EXT_INT7 56 262#define MXC91231_INT_EXT_INT6 57 263#define MXC91231_INT_EXT_INT5 58 264#define MXC91231_INT_EXT_INT4 59 265#define MXC91231_INT_EXT_INT3 60 266#define MXC91231_INT_EXT_INT2 61 267#define MXC91231_INT_EXT_INT1 62 268#define MXC91231_INT_EXT_INT0 63 269 270#define MXC91231_MAX_INT_LINES 63 271#define MXC91231_MAX_EXT_LINES 8 272 273#endif /* __MACH_MXC91231_H__ */ 274