1/* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */ 2/* 3 * linux/arch/arm/mm/cache-v7.S 4 * 5 * Copyright (C) 2001 Deep Blue Solutions Ltd. 6 * Copyright (C) 2005 ARM Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This is the "shell" of the ARMv7 processor support. 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16#include <asm/assembler.h> 17#include <asm/unwind.h> 18 19#include "proc-macros.S" 20 21 .section .text.fastpath, "a" 22 23/* 24 * v7_flush_dcache_all() 25 * 26 * Flush the whole D-cache. 27 * 28 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 29 * 30 * - mm - mm_struct describing address space 31 */ 32ENTRY(v7_flush_dcache_all) 33 dmb @ ensure ordering with previous memory accesses 34 mrc p15, 1, r0, c0, c0, 1 @ read clidr 35 ands r3, r0, #0x7000000 @ extract loc from clidr 36 mov r3, r3, lsr #23 @ left align loc bit field 37 beq finished @ if loc is 0, then no need to clean 38 mov r10, #0 @ start clean at cache level 0 39loop1: 40 add r2, r10, r10, lsr #1 @ work out 3x current cache level 41 mov r1, r0, lsr r2 @ extract cache type bits from clidr 42 and r1, r1, #7 @ mask of the bits for current cache only 43 cmp r1, #2 @ see what cache we have at this level 44 blt skip @ skip if no cache, or just i-cache 45 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 46 isb @ isb to sych the new cssr&csidr 47 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 48 and r2, r1, #7 @ extract the length of the cache lines 49 add r2, r2, #4 @ add 4 (line length offset) 50 ldr r4, =0x3ff 51 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 52 clz r5, r4 @ find bit position of way size increment 53 ldr r7, =0x7fff 54 ands r7, r7, r1, lsr #13 @ extract max number of the index size 55loop2: 56 mov r9, r4 @ create working copy of max way size 57loop3: 58 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 59 THUMB( lsl r6, r9, r5 ) 60 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 61 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 62 THUMB( lsl r6, r7, r2 ) 63 THUMB( orr r11, r11, r6 ) @ factor index number into r11 64 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 65 subs r9, r9, #1 @ decrement the way 66 bge loop3 67 subs r7, r7, #1 @ decrement the index 68 bge loop2 69skip: 70 add r10, r10, #2 @ increment cache number 71 cmp r3, r10 72 bgt loop1 73finished: 74 mov r10, #0 @ swith back to cache level 0 75 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 76 dsb 77 isb 78 mov pc, lr 79ENDPROC(v7_flush_dcache_all) 80 81/* 82 * v7_flush_cache_all() 83 * 84 * Flush the entire cache system. 85 * The data cache flush is now achieved using atomic clean / invalidates 86 * working outwards from L1 cache. This is done using Set/Way based cache 87 * maintainance instructions. 88 * The instruction cache can still be invalidated back to the point of 89 * unification in a single instruction. 90 * 91 */ 92ENTRY(v7_flush_kern_cache_all) 93 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 94 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 95 bl v7_flush_dcache_all 96 mov r0, #0 97#ifdef CONFIG_SMP 98 mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable 99#else 100 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 101#endif 102 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 103 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 104 mov pc, lr 105ENDPROC(v7_flush_kern_cache_all) 106 107/* 108 * v7_flush_cache_all() 109 * 110 * Flush all TLB entries in a particular address space 111 * 112 * - mm - mm_struct describing address space 113 */ 114ENTRY(v7_flush_user_cache_all) 115 /*FALLTHROUGH*/ 116 117/* 118 * v7_flush_cache_range(start, end, flags) 119 * 120 * Flush a range of TLB entries in the specified address space. 121 * 122 * - start - start address (may not be aligned) 123 * - end - end address (exclusive, may not be aligned) 124 * - flags - vm_area_struct flags describing address space 125 * 126 * It is assumed that: 127 * - we have a VIPT cache. 128 */ 129ENTRY(v7_flush_user_cache_range) 130 mov pc, lr 131ENDPROC(v7_flush_user_cache_all) 132ENDPROC(v7_flush_user_cache_range) 133 134/* 135 * v7_coherent_kern_range(start,end) 136 * 137 * Ensure that the I and D caches are coherent within specified 138 * region. This is typically used when code has been written to 139 * a memory region, and will be executed. 140 * 141 * - start - virtual start address of region 142 * - end - virtual end address of region 143 * 144 * It is assumed that: 145 * - the Icache does not read data from the write buffer 146 */ 147ENTRY(v7_coherent_kern_range) 148 /* FALLTHROUGH */ 149 150/* 151 * v7_coherent_user_range(start,end) 152 * 153 * Ensure that the I and D caches are coherent within specified 154 * region. This is typically used when code has been written to 155 * a memory region, and will be executed. 156 * 157 * - start - virtual start address of region 158 * - end - virtual end address of region 159 * 160 * It is assumed that: 161 * - the Icache does not read data from the write buffer 162 */ 163ENTRY(v7_coherent_user_range) 164 UNWIND(.fnstart ) 165 dcache_line_size r2, r3 166 sub r3, r2, #1 167 bic r0, r0, r3 1681: 169 USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification 170 dsb 171 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line 172 add r0, r0, r2 1732: 174 cmp r0, r1 175 blo 1b 176 mov r0, #0 177#ifdef CONFIG_SMP 178 mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable 179#else 180 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 181#endif 182 dsb 183 isb 184 mov pc, lr 185 186/* 187 * Fault handling for the cache operation above. If the virtual address in r0 188 * isn't mapped, just try the next page. 189 */ 1909001: 191 mov r0, r0, lsr #12 192 mov r0, r0, lsl #12 193 add r0, r0, #4096 194 b 2b 195 UNWIND(.fnend ) 196ENDPROC(v7_coherent_kern_range) 197ENDPROC(v7_coherent_user_range) 198 199/* 200 * v7_flush_kern_dcache_area(void *addr, size_t size) 201 * 202 * Ensure that the data held in the page kaddr is written back 203 * to the page in question. 204 * 205 * - addr - kernel address 206 * - size - region size 207 */ 208ENTRY(v7_flush_kern_dcache_area) 209 dcache_line_size r2, r3 210 add r1, r0, r1 2111: 212 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 213 add r0, r0, r2 214 cmp r0, r1 215 blo 1b 216 dsb 217 mov pc, lr 218ENDPROC(v7_flush_kern_dcache_area) 219 220/* 221 * v7_dma_inv_range(start,end) 222 * 223 * Invalidate the data cache within the specified region; we will 224 * be performing a DMA operation in this region and we want to 225 * purge old data in the cache. 226 * 227 * - start - virtual start address of region 228 * - end - virtual end address of region 229 */ 230v7_dma_inv_range: 231 dcache_line_size r2, r3 232 sub r3, r2, #1 233 tst r0, r3 234 bic r0, r0, r3 235 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 236 237 tst r1, r3 238 bic r1, r1, r3 239 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 2401: 241 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 242 add r0, r0, r2 243 cmp r0, r1 244 blo 1b 245 dsb 246 mov pc, lr 247ENDPROC(v7_dma_inv_range) 248 249/* 250 * v7_dma_clean_range(start,end) 251 * - start - virtual start address of region 252 * - end - virtual end address of region 253 */ 254v7_dma_clean_range: 255 dcache_line_size r2, r3 256 sub r3, r2, #1 257 bic r0, r0, r3 2581: 259 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 260 add r0, r0, r2 261 cmp r0, r1 262 blo 1b 263 dsb 264 mov pc, lr 265ENDPROC(v7_dma_clean_range) 266 267/* 268 * v7_dma_flush_range(start,end) 269 * - start - virtual start address of region 270 * - end - virtual end address of region 271 */ 272ENTRY(v7_dma_flush_range) 273 dcache_line_size r2, r3 274 sub r3, r2, #1 275 bic r0, r0, r3 2761: 277 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 278 add r0, r0, r2 279 cmp r0, r1 280 blo 1b 281 dsb 282 mov pc, lr 283ENDPROC(v7_dma_flush_range) 284 285/* 286 * dma_map_area(start, size, dir) 287 * - start - kernel virtual start address 288 * - size - size of region 289 * - dir - DMA direction 290 */ 291ENTRY(v7_dma_map_area) 292 add r1, r1, r0 293 teq r2, #DMA_FROM_DEVICE 294 beq v7_dma_inv_range 295 b v7_dma_clean_range 296ENDPROC(v7_dma_map_area) 297 298/* 299 * dma_unmap_area(start, size, dir) 300 * - start - kernel virtual start address 301 * - size - size of region 302 * - dir - DMA direction 303 */ 304ENTRY(v7_dma_unmap_area) 305 add r1, r1, r0 306 teq r2, #DMA_TO_DEVICE 307 bne v7_dma_inv_range 308 mov pc, lr 309ENDPROC(v7_dma_unmap_area) 310 311 __INITDATA 312 313 .type v7_cache_fns, #object 314ENTRY(v7_cache_fns) 315 .long v7_flush_kern_cache_all 316 .long v7_flush_user_cache_all 317 .long v7_flush_user_cache_range 318 .long v7_coherent_kern_range 319 .long v7_coherent_user_range 320 .long v7_flush_kern_dcache_area 321 .long v7_dma_map_area 322 .long v7_dma_unmap_area 323 .long v7_dma_flush_range 324 .long v7_dma_inv_range 325 .size v7_cache_fns, . - v7_cache_fns 326