1/* 2 * linux/arch/arm/mach-realview/realview_pba8.c 3 * 4 * Copyright (C) 2008 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22#include <linux/init.h> 23#include <linux/platform_device.h> 24#include <linux/sysdev.h> 25#include <linux/amba/bus.h> 26#include <linux/amba/pl061.h> 27#include <linux/amba/mmci.h> 28#include <linux/amba/pl022.h> 29#include <linux/io.h> 30 31#include <asm/irq.h> 32#include <asm/leds.h> 33#include <asm/mach-types.h> 34#include <asm/pmu.h> 35#include <asm/pgtable.h> 36#include <asm/hardware/gic.h> 37 38#include <asm/mach/arch.h> 39#include <asm/mach/map.h> 40#include <asm/mach/time.h> 41 42#include <mach/hardware.h> 43#include <mach/board-pba8.h> 44#include <mach/irqs.h> 45 46#include "core.h" 47 48static struct map_desc realview_pba8_io_desc[] __initdata = { 49 { 50 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), 51 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), 52 .length = SZ_4K, 53 .type = MT_DEVICE, 54 }, { 55 .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_CPU_BASE), 56 .pfn = __phys_to_pfn(REALVIEW_PBA8_GIC_CPU_BASE), 57 .length = SZ_4K, 58 .type = MT_DEVICE, 59 }, { 60 .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_DIST_BASE), 61 .pfn = __phys_to_pfn(REALVIEW_PBA8_GIC_DIST_BASE), 62 .length = SZ_4K, 63 .type = MT_DEVICE, 64 }, { 65 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), 66 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), 67 .length = SZ_4K, 68 .type = MT_DEVICE, 69 }, { 70 .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER0_1_BASE), 71 .pfn = __phys_to_pfn(REALVIEW_PBA8_TIMER0_1_BASE), 72 .length = SZ_4K, 73 .type = MT_DEVICE, 74 }, { 75 .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER2_3_BASE), 76 .pfn = __phys_to_pfn(REALVIEW_PBA8_TIMER2_3_BASE), 77 .length = SZ_4K, 78 .type = MT_DEVICE, 79 }, 80#ifdef CONFIG_PCI 81 { 82 .virtual = PCIX_UNIT_BASE, 83 .pfn = __phys_to_pfn(REALVIEW_PBA8_PCI_BASE), 84 .length = REALVIEW_PBA8_PCI_BASE_SIZE, 85 .type = MT_DEVICE 86 }, 87#endif 88#ifdef CONFIG_DEBUG_LL 89 { 90 .virtual = IO_ADDRESS(REALVIEW_PBA8_UART0_BASE), 91 .pfn = __phys_to_pfn(REALVIEW_PBA8_UART0_BASE), 92 .length = SZ_4K, 93 .type = MT_DEVICE, 94 }, 95#endif 96}; 97 98static void __init realview_pba8_map_io(void) 99{ 100 iotable_init(realview_pba8_io_desc, ARRAY_SIZE(realview_pba8_io_desc)); 101} 102 103static struct pl061_platform_data gpio0_plat_data = { 104 .gpio_base = 0, 105 .irq_base = -1, 106}; 107 108static struct pl061_platform_data gpio1_plat_data = { 109 .gpio_base = 8, 110 .irq_base = -1, 111}; 112 113static struct pl061_platform_data gpio2_plat_data = { 114 .gpio_base = 16, 115 .irq_base = -1, 116}; 117 118static struct pl022_ssp_controller ssp0_plat_data = { 119 .bus_id = 0, 120 .enable_dma = 0, 121 .num_chipselect = 1, 122}; 123 124/* 125 * RealView PBA8Core AMBA devices 126 */ 127 128#define GPIO2_IRQ { IRQ_PBA8_GPIO2, NO_IRQ } 129#define GPIO2_DMA { 0, 0 } 130#define GPIO3_IRQ { IRQ_PBA8_GPIO3, NO_IRQ } 131#define GPIO3_DMA { 0, 0 } 132#define AACI_IRQ { IRQ_PBA8_AACI, NO_IRQ } 133#define AACI_DMA { 0x80, 0x81 } 134#define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B } 135#define MMCI0_DMA { 0x84, 0 } 136#define KMI0_IRQ { IRQ_PBA8_KMI0, NO_IRQ } 137#define KMI0_DMA { 0, 0 } 138#define KMI1_IRQ { IRQ_PBA8_KMI1, NO_IRQ } 139#define KMI1_DMA { 0, 0 } 140#define PBA8_SMC_IRQ { NO_IRQ, NO_IRQ } 141#define PBA8_SMC_DMA { 0, 0 } 142#define MPMC_IRQ { NO_IRQ, NO_IRQ } 143#define MPMC_DMA { 0, 0 } 144#define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD, NO_IRQ } 145#define PBA8_CLCD_DMA { 0, 0 } 146#define DMAC_IRQ { IRQ_PBA8_DMAC, NO_IRQ } 147#define DMAC_DMA { 0, 0 } 148#define SCTL_IRQ { NO_IRQ, NO_IRQ } 149#define SCTL_DMA { 0, 0 } 150#define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG, NO_IRQ } 151#define PBA8_WATCHDOG_DMA { 0, 0 } 152#define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0, NO_IRQ } 153#define PBA8_GPIO0_DMA { 0, 0 } 154#define GPIO1_IRQ { IRQ_PBA8_GPIO1, NO_IRQ } 155#define GPIO1_DMA { 0, 0 } 156#define PBA8_RTC_IRQ { IRQ_PBA8_RTC, NO_IRQ } 157#define PBA8_RTC_DMA { 0, 0 } 158#define SCI_IRQ { IRQ_PBA8_SCI, NO_IRQ } 159#define SCI_DMA { 7, 6 } 160#define PBA8_UART0_IRQ { IRQ_PBA8_UART0, NO_IRQ } 161#define PBA8_UART0_DMA { 15, 14 } 162#define PBA8_UART1_IRQ { IRQ_PBA8_UART1, NO_IRQ } 163#define PBA8_UART1_DMA { 13, 12 } 164#define PBA8_UART2_IRQ { IRQ_PBA8_UART2, NO_IRQ } 165#define PBA8_UART2_DMA { 11, 10 } 166#define PBA8_UART3_IRQ { IRQ_PBA8_UART3, NO_IRQ } 167#define PBA8_UART3_DMA { 0x86, 0x87 } 168#define PBA8_SSP_IRQ { IRQ_PBA8_SSP, NO_IRQ } 169#define PBA8_SSP_DMA { 9, 8 } 170 171/* FPGA Primecells */ 172AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); 173AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); 174AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); 175AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); 176AMBA_DEVICE(uart3, "fpga:uart3", PBA8_UART3, NULL); 177 178/* DevChip Primecells */ 179AMBA_DEVICE(smc, "dev:smc", PBA8_SMC, NULL); 180AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL); 181AMBA_DEVICE(wdog, "dev:wdog", PBA8_WATCHDOG, NULL); 182AMBA_DEVICE(gpio0, "dev:gpio0", PBA8_GPIO0, &gpio0_plat_data); 183AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data); 184AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data); 185AMBA_DEVICE(rtc, "dev:rtc", PBA8_RTC, NULL); 186AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); 187AMBA_DEVICE(uart0, "dev:uart0", PBA8_UART0, NULL); 188AMBA_DEVICE(uart1, "dev:uart1", PBA8_UART1, NULL); 189AMBA_DEVICE(uart2, "dev:uart2", PBA8_UART2, NULL); 190AMBA_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, &ssp0_plat_data); 191 192/* Primecells on the NEC ISSP chip */ 193AMBA_DEVICE(clcd, "issp:clcd", PBA8_CLCD, &clcd_plat_data); 194AMBA_DEVICE(dmac, "issp:dmac", DMAC, NULL); 195 196static struct amba_device *amba_devs[] __initdata = { 197 &dmac_device, 198 &uart0_device, 199 &uart1_device, 200 &uart2_device, 201 &uart3_device, 202 &smc_device, 203 &clcd_device, 204 &sctl_device, 205 &wdog_device, 206 &gpio0_device, 207 &gpio1_device, 208 &gpio2_device, 209 &rtc_device, 210 &sci0_device, 211 &ssp0_device, 212 &aaci_device, 213 &mmc0_device, 214 &kmi0_device, 215 &kmi1_device, 216}; 217 218/* 219 * RealView PB-A8 platform devices 220 */ 221static struct resource realview_pba8_flash_resource[] = { 222 [0] = { 223 .start = REALVIEW_PBA8_FLASH0_BASE, 224 .end = REALVIEW_PBA8_FLASH0_BASE + REALVIEW_PBA8_FLASH0_SIZE - 1, 225 .flags = IORESOURCE_MEM, 226 }, 227 [1] = { 228 .start = REALVIEW_PBA8_FLASH1_BASE, 229 .end = REALVIEW_PBA8_FLASH1_BASE + REALVIEW_PBA8_FLASH1_SIZE - 1, 230 .flags = IORESOURCE_MEM, 231 }, 232}; 233 234static struct resource realview_pba8_smsc911x_resources[] = { 235 [0] = { 236 .start = REALVIEW_PBA8_ETH_BASE, 237 .end = REALVIEW_PBA8_ETH_BASE + SZ_64K - 1, 238 .flags = IORESOURCE_MEM, 239 }, 240 [1] = { 241 .start = IRQ_PBA8_ETH, 242 .end = IRQ_PBA8_ETH, 243 .flags = IORESOURCE_IRQ, 244 }, 245}; 246 247static struct resource realview_pba8_isp1761_resources[] = { 248 [0] = { 249 .start = REALVIEW_PBA8_USB_BASE, 250 .end = REALVIEW_PBA8_USB_BASE + SZ_128K - 1, 251 .flags = IORESOURCE_MEM, 252 }, 253 [1] = { 254 .start = IRQ_PBA8_USB, 255 .end = IRQ_PBA8_USB, 256 .flags = IORESOURCE_IRQ, 257 }, 258}; 259 260static struct resource pmu_resource = { 261 .start = IRQ_PBA8_PMU, 262 .end = IRQ_PBA8_PMU, 263 .flags = IORESOURCE_IRQ, 264}; 265 266static struct platform_device pmu_device = { 267 .name = "arm-pmu", 268 .id = ARM_PMU_DEVICE_CPU, 269 .num_resources = 1, 270 .resource = &pmu_resource, 271}; 272 273static void __init gic_init_irq(void) 274{ 275 /* ARM PB-A8 on-board GIC */ 276 gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE); 277 gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START); 278 gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE)); 279} 280 281static void __init realview_pba8_timer_init(void) 282{ 283 timer0_va_base = __io_address(REALVIEW_PBA8_TIMER0_1_BASE); 284 timer1_va_base = __io_address(REALVIEW_PBA8_TIMER0_1_BASE) + 0x20; 285 timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE); 286 timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20; 287 288 realview_timer_init(IRQ_PBA8_TIMER0_1); 289} 290 291static struct sys_timer realview_pba8_timer = { 292 .init = realview_pba8_timer_init, 293}; 294 295static void realview_pba8_reset(char mode) 296{ 297 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); 298 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK); 299 300 /* 301 * To reset, we hit the on-board reset register 302 * in the system FPGA 303 */ 304 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl); 305 __raw_writel(0x0000, reset_ctrl); 306 __raw_writel(0x0004, reset_ctrl); 307} 308 309static void __init realview_pba8_init(void) 310{ 311 int i; 312 313 realview_flash_register(realview_pba8_flash_resource, 314 ARRAY_SIZE(realview_pba8_flash_resource)); 315 realview_eth_register(NULL, realview_pba8_smsc911x_resources); 316 platform_device_register(&realview_i2c_device); 317 platform_device_register(&realview_cf_device); 318 realview_usb_register(realview_pba8_isp1761_resources); 319 platform_device_register(&pmu_device); 320 321 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 322 struct amba_device *d = amba_devs[i]; 323 amba_device_register(d, &iomem_resource); 324 } 325 326#ifdef CONFIG_LEDS 327 leds_event = realview_leds_event; 328#endif 329 realview_reset = realview_pba8_reset; 330} 331 332MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") 333 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 334 .phys_io = REALVIEW_PBA8_UART0_BASE & SECTION_MASK, 335 .io_pg_offst = (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc, 336 .boot_params = PHYS_OFFSET + 0x00000100, 337 .fixup = realview_fixup, 338 .map_io = realview_pba8_map_io, 339 .init_irq = gic_init_irq, 340 .timer = &realview_pba8_timer, 341 .init_machine = realview_pba8_init, 342MACHINE_END 343