1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H 2#define __ARCH_ARM_MACH_OMAP2_PRM_H 3 4/* 5 * OMAP2/3 Power/Reset Management (PRM) register definitions 6 * 7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 8 * Copyright (C) 2009 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17#include "prcm-common.h" 18 19#define OMAP2420_PRM_REGADDR(module, reg) \ 20 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) 21#define OMAP2430_PRM_REGADDR(module, reg) \ 22 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) 23#define OMAP34XX_PRM_REGADDR(module, reg) \ 24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) 25#define OMAP44XX_PRM_REGADDR(module, reg) \ 26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) 27#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \ 28 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg)) 29 30#include "prm44xx.h" 31 32/* 33 * Architecture-specific global PRM registers 34 * Use __raw_{read,write}l() with these registers. 35 * 36 * With a few exceptions, these are the register names beginning with 37 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the 38 * IRQSTATUS and IRQENABLE bits.) 39 * 40 */ 41 42#define OMAP2_PRCM_REVISION_OFFSET 0x0000 43#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) 44#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 45#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) 46 47#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 48#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) 49#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c 50#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) 51 52#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 53#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) 54#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 55#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) 56#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 57#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) 58#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 59#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) 60#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 61#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) 62#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 63#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) 64#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 65#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) 66#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 67#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) 68#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 69#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) 70#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 71#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) 72 73#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) 74#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) 75 76#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) 77#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) 78 79#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) 80#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) 81#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) 82#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) 83#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) 84#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) 85#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) 86#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) 87#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) 88#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) 89 90#define OMAP3_PRM_REVISION_OFFSET 0x0004 91#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) 92#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 93#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) 94 95#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 96#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) 97#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c 98#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) 99 100 101#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 102#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) 103#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 104#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) 105#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 106#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) 107#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c 108#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) 109#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 110#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) 111#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 112#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) 113#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 114#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) 115#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c 116#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) 117#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 118#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) 119#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 120#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) 121#define OMAP3_PRM_RSTST_OFFSET 0x0058 122#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) 123#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 124#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) 125#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 126#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) 127#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 128#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) 129#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 130#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) 131#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 132#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) 133#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 134#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) 135#define OMAP3_PRM_POLCTRL_OFFSET 0x009c 136#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) 137#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 138#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) 139#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 140#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) 141#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 142#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) 143#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 144#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) 145#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc 146#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) 147#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 148#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) 149#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 150#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) 151#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 152#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) 153#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 154#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) 155#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 156#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) 157#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc 158#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) 159#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 160#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) 161#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 162#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) 163 164#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 165#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) 166#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 167#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 168 169/* 170 * Module specific PRM registers from PRM_BASE + domain offset 171 * 172 * Use prm_{read,write}_mod_reg() with these registers. 173 * 174 * With a few exceptions, these are the register names beginning with 175 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS 176 * and IRQENABLE bits.) 177 * 178 */ 179 180/* Registers appearing on both 24xx and 34xx */ 181 182#define OMAP2_RM_RSTCTRL 0x0050 183#define OMAP2_RM_RSTTIME 0x0054 184#define OMAP2_RM_RSTST 0x0058 185#define OMAP2_PM_PWSTCTRL 0x00e0 186#define OMAP2_PM_PWSTST 0x00e4 187 188#define PM_WKEN 0x00a0 189#define PM_WKEN1 PM_WKEN 190#define PM_WKST 0x00b0 191#define PM_WKST1 PM_WKST 192#define PM_WKDEP 0x00c8 193#define PM_EVGENCTRL 0x00d4 194#define PM_EVGENONTIM 0x00d8 195#define PM_EVGENOFFTIM 0x00dc 196 197/* Omap2 specific registers */ 198#define OMAP24XX_PM_WKEN2 0x00a4 199#define OMAP24XX_PM_WKST2 0x00b4 200 201#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ 202#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ 203#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 204#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc 205 206/* Omap3 specific registers */ 207#define OMAP3430ES2_PM_WKEN3 0x00f0 208#define OMAP3430ES2_PM_WKST3 0x00b8 209 210#define OMAP3430_PM_MPUGRPSEL 0x00a4 211#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL 212#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 213 214#define OMAP3430_PM_IVAGRPSEL 0x00a8 215#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL 216#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 217 218#define OMAP3430_PM_PREPWSTST 0x00e8 219 220#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 221#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc 222 223/* Omap4 specific registers */ 224#define OMAP4_RM_RSTCTRL 0x0000 225#define OMAP4_RM_RSTTIME 0x0004 226#define OMAP4_RM_RSTST 0x0008 227#define OMAP4_PM_PWSTCTRL 0x0000 228#define OMAP4_PM_PWSTST 0x0004 229 230 231#ifndef __ASSEMBLER__ 232 233/* Power/reset management domain register get/set */ 234extern u32 prm_read_mod_reg(s16 module, u16 idx); 235extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); 236extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 237 238/* Read-modify-write bits in a PRM register (by domain) */ 239static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 240{ 241 return prm_rmw_mod_reg_bits(bits, bits, module, idx); 242} 243 244static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) 245{ 246 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); 247} 248 249#endif 250 251/* 252 * Bits common to specific registers 253 * 254 * The 3430 register and bit names are generally used, 255 * since they tend to make more sense 256 */ 257 258/* PM_EVGENONTIM_MPU */ 259/* Named PM_EVEGENONTIM_MPU on the 24XX */ 260#define OMAP_ONTIMEVAL_SHIFT 0 261#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) 262 263/* PM_EVGENOFFTIM_MPU */ 264/* Named PM_EVEGENOFFTIM_MPU on the 24XX */ 265#define OMAP_OFFTIMEVAL_SHIFT 0 266#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) 267 268/* PRM_CLKSETUP and PRCM_VOLTSETUP */ 269/* Named PRCM_CLKSSETUP on the 24XX */ 270#define OMAP_SETUP_TIME_SHIFT 0 271#define OMAP_SETUP_TIME_MASK (0xffff << 0) 272 273/* PRM_CLKSRC_CTRL */ 274/* Named PRCM_CLKSRC_CTRL on the 24XX */ 275#define OMAP_SYSCLKDIV_SHIFT 6 276#define OMAP_SYSCLKDIV_MASK (0x3 << 6) 277#define OMAP_AUTOEXTCLKMODE_SHIFT 3 278#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) 279#define OMAP_SYSCLKSEL_SHIFT 0 280#define OMAP_SYSCLKSEL_MASK (0x3 << 0) 281 282/* PM_EVGENCTRL_MPU */ 283#define OMAP_OFFLOADMODE_SHIFT 3 284#define OMAP_OFFLOADMODE_MASK (0x3 << 3) 285#define OMAP_ONLOADMODE_SHIFT 1 286#define OMAP_ONLOADMODE_MASK (0x3 << 1) 287#define OMAP_ENABLE_MASK (1 << 0) 288 289/* PRM_RSTTIME */ 290/* Named RM_RSTTIME_WKUP on the 24xx */ 291#define OMAP_RSTTIME2_SHIFT 8 292#define OMAP_RSTTIME2_MASK (0x1f << 8) 293#define OMAP_RSTTIME1_SHIFT 0 294#define OMAP_RSTTIME1_MASK (0xff << 0) 295 296/* PRM_RSTCTRL */ 297/* Named RM_RSTCTRL_WKUP on the 24xx */ 298/* 2420 calls RST_DPLL3 'RST_DPLL' */ 299#define OMAP_RST_DPLL3_MASK (1 << 2) 300#define OMAP_RST_GS_MASK (1 << 1) 301 302 303/* 304 * Bits common to module-shared registers 305 * 306 * Not all registers of a particular type support all of these bits - 307 * check TRM if you are unsure 308 */ 309 310/* 311 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP 312 * 313 * 2430: PM_PWSTST_MDM 314 * 315 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, 316 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 317 * PM_PWSTST_NEON 318 */ 319#define OMAP_INTRANSITION_MASK (1 << 20) 320 321 322/* 323 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP 324 * 325 * 2430: PM_PWSTST_MDM 326 * 327 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, 328 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 329 * PM_PWSTST_NEON 330 */ 331#define OMAP_POWERSTATEST_SHIFT 0 332#define OMAP_POWERSTATEST_MASK (0x3 << 0) 333 334/* 335 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is 336 * called 'COREWKUP_RST' 337 * 338 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, 339 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON 340 */ 341#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) 342 343/* 344 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP 345 * 346 * 2430: RM_RSTST_MDM 347 * 348 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 349 */ 350#define OMAP_DOMAINWKUP_RST_MASK (1 << 2) 351 352/* 353 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP 354 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. 355 * 356 * 2430: RM_RSTST_MDM 357 * 358 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 359 */ 360#define OMAP_GLOBALWARM_RST_MASK (1 << 1) 361#define OMAP_GLOBALCOLD_RST_MASK (1 << 0) 362 363/* 364 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP 365 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" 366 * 367 * 2430: PM_WKDEP_MDM 368 * 369 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, 370 * PM_WKDEP_PER 371 */ 372#define OMAP_EN_WKUP_SHIFT 4 373#define OMAP_EN_WKUP_MASK (1 << 4) 374 375/* 376 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 377 * PM_PWSTCTRL_DSP 378 * 379 * 2430: PM_PWSTCTRL_MDM 380 * 381 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 382 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 383 * PM_PWSTCTRL_NEON 384 */ 385#define OMAP_LOGICRETSTATE_MASK (1 << 2) 386 387/* 388 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 389 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU 390 * 391 * 2430: PM_PWSTCTRL_MDM shared bits 392 * 393 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, 394 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 395 * PM_PWSTCTRL_NEON shared bits 396 */ 397#define OMAP_POWERSTATE_SHIFT 0 398#define OMAP_POWERSTATE_MASK (0x3 << 0) 399 400 401#endif 402