1/* 2 * linux/arch/arm/mach-omap2/devices.c 3 * 4 * OMAP2 platform device setup/initialization 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/init.h> 15#include <linux/platform_device.h> 16#include <linux/io.h> 17#include <linux/clk.h> 18 19#include <mach/hardware.h> 20#include <mach/irqs.h> 21#include <asm/mach-types.h> 22#include <asm/mach/map.h> 23#include <asm/pmu.h> 24 25#include <plat/control.h> 26#include <plat/tc.h> 27#include <plat/board.h> 28#include <mach/gpio.h> 29#include <plat/mmc.h> 30#include <plat/dma.h> 31 32#include "mux.h" 33 34#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 35 36static struct resource cam_resources[] = { 37 { 38 .start = OMAP24XX_CAMERA_BASE, 39 .end = OMAP24XX_CAMERA_BASE + 0xfff, 40 .flags = IORESOURCE_MEM, 41 }, 42 { 43 .start = INT_24XX_CAM_IRQ, 44 .flags = IORESOURCE_IRQ, 45 } 46}; 47 48static struct platform_device omap_cam_device = { 49 .name = "omap24xxcam", 50 .id = -1, 51 .num_resources = ARRAY_SIZE(cam_resources), 52 .resource = cam_resources, 53}; 54 55static inline void omap_init_camera(void) 56{ 57 platform_device_register(&omap_cam_device); 58} 59 60#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) 61 62static struct resource omap3isp_resources[] = { 63 { 64 .start = OMAP3430_ISP_BASE, 65 .end = OMAP3430_ISP_END, 66 .flags = IORESOURCE_MEM, 67 }, 68 { 69 .start = OMAP3430_ISP_CBUFF_BASE, 70 .end = OMAP3430_ISP_CBUFF_END, 71 .flags = IORESOURCE_MEM, 72 }, 73 { 74 .start = OMAP3430_ISP_CCP2_BASE, 75 .end = OMAP3430_ISP_CCP2_END, 76 .flags = IORESOURCE_MEM, 77 }, 78 { 79 .start = OMAP3430_ISP_CCDC_BASE, 80 .end = OMAP3430_ISP_CCDC_END, 81 .flags = IORESOURCE_MEM, 82 }, 83 { 84 .start = OMAP3430_ISP_HIST_BASE, 85 .end = OMAP3430_ISP_HIST_END, 86 .flags = IORESOURCE_MEM, 87 }, 88 { 89 .start = OMAP3430_ISP_H3A_BASE, 90 .end = OMAP3430_ISP_H3A_END, 91 .flags = IORESOURCE_MEM, 92 }, 93 { 94 .start = OMAP3430_ISP_PREV_BASE, 95 .end = OMAP3430_ISP_PREV_END, 96 .flags = IORESOURCE_MEM, 97 }, 98 { 99 .start = OMAP3430_ISP_RESZ_BASE, 100 .end = OMAP3430_ISP_RESZ_END, 101 .flags = IORESOURCE_MEM, 102 }, 103 { 104 .start = OMAP3430_ISP_SBL_BASE, 105 .end = OMAP3430_ISP_SBL_END, 106 .flags = IORESOURCE_MEM, 107 }, 108 { 109 .start = OMAP3430_ISP_CSI2A_BASE, 110 .end = OMAP3430_ISP_CSI2A_END, 111 .flags = IORESOURCE_MEM, 112 }, 113 { 114 .start = OMAP3430_ISP_CSI2PHY_BASE, 115 .end = OMAP3430_ISP_CSI2PHY_END, 116 .flags = IORESOURCE_MEM, 117 }, 118 { 119 .start = INT_34XX_CAM_IRQ, 120 .flags = IORESOURCE_IRQ, 121 } 122}; 123 124static struct platform_device omap3isp_device = { 125 .name = "omap3isp", 126 .id = -1, 127 .num_resources = ARRAY_SIZE(omap3isp_resources), 128 .resource = omap3isp_resources, 129}; 130 131static inline void omap_init_camera(void) 132{ 133 platform_device_register(&omap3isp_device); 134} 135#else 136static inline void omap_init_camera(void) 137{ 138} 139#endif 140 141#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 142 143#define MBOX_REG_SIZE 0x120 144 145#ifdef CONFIG_ARCH_OMAP2 146static struct resource omap2_mbox_resources[] = { 147 { 148 .start = OMAP24XX_MAILBOX_BASE, 149 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, 150 .flags = IORESOURCE_MEM, 151 }, 152 { 153 .start = INT_24XX_MAIL_U0_MPU, 154 .flags = IORESOURCE_IRQ, 155 .name = "dsp", 156 }, 157 { 158 .start = INT_24XX_MAIL_U3_MPU, 159 .flags = IORESOURCE_IRQ, 160 .name = "iva", 161 }, 162}; 163static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); 164#else 165#define omap2_mbox_resources NULL 166#define omap2_mbox_resources_sz 0 167#endif 168 169#ifdef CONFIG_ARCH_OMAP3 170static struct resource omap3_mbox_resources[] = { 171 { 172 .start = OMAP34XX_MAILBOX_BASE, 173 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, 174 .flags = IORESOURCE_MEM, 175 }, 176 { 177 .start = INT_24XX_MAIL_U0_MPU, 178 .flags = IORESOURCE_IRQ, 179 .name = "dsp", 180 }, 181}; 182static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); 183#else 184#define omap3_mbox_resources NULL 185#define omap3_mbox_resources_sz 0 186#endif 187 188#ifdef CONFIG_ARCH_OMAP4 189 190#define OMAP4_MBOX_REG_SIZE 0x130 191static struct resource omap4_mbox_resources[] = { 192 { 193 .start = OMAP44XX_MAILBOX_BASE, 194 .end = OMAP44XX_MAILBOX_BASE + 195 OMAP4_MBOX_REG_SIZE - 1, 196 .flags = IORESOURCE_MEM, 197 }, 198 { 199 .start = OMAP44XX_IRQ_MAIL_U0, 200 .flags = IORESOURCE_IRQ, 201 .name = "mbox", 202 }, 203}; 204static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); 205#else 206#define omap4_mbox_resources NULL 207#define omap4_mbox_resources_sz 0 208#endif 209 210static struct platform_device mbox_device = { 211 .name = "omap-mailbox", 212 .id = -1, 213}; 214 215static inline void omap_init_mbox(void) 216{ 217 if (cpu_is_omap24xx()) { 218 mbox_device.resource = omap2_mbox_resources; 219 mbox_device.num_resources = omap2_mbox_resources_sz; 220 } else if (cpu_is_omap34xx()) { 221 mbox_device.resource = omap3_mbox_resources; 222 mbox_device.num_resources = omap3_mbox_resources_sz; 223 } else if (cpu_is_omap44xx()) { 224 mbox_device.resource = omap4_mbox_resources; 225 mbox_device.num_resources = omap4_mbox_resources_sz; 226 } else { 227 pr_err("%s: platform not supported\n", __func__); 228 return; 229 } 230 platform_device_register(&mbox_device); 231} 232#else 233static inline void omap_init_mbox(void) { } 234#endif /* CONFIG_OMAP_MBOX_FWK */ 235 236static inline void omap_init_sti(void) {} 237 238#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) 239 240#include <plat/mcspi.h> 241 242#define OMAP2_MCSPI1_BASE 0x48098000 243#define OMAP2_MCSPI2_BASE 0x4809a000 244#define OMAP2_MCSPI3_BASE 0x480b8000 245#define OMAP2_MCSPI4_BASE 0x480ba000 246 247#define OMAP4_MCSPI1_BASE 0x48098100 248#define OMAP4_MCSPI2_BASE 0x4809a100 249#define OMAP4_MCSPI3_BASE 0x480b8100 250#define OMAP4_MCSPI4_BASE 0x480ba100 251 252static struct omap2_mcspi_platform_config omap2_mcspi1_config = { 253 .num_cs = 4, 254}; 255 256static struct resource omap2_mcspi1_resources[] = { 257 { 258 .start = OMAP2_MCSPI1_BASE, 259 .end = OMAP2_MCSPI1_BASE + 0xff, 260 .flags = IORESOURCE_MEM, 261 }, 262}; 263 264static struct platform_device omap2_mcspi1 = { 265 .name = "omap2_mcspi", 266 .id = 1, 267 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), 268 .resource = omap2_mcspi1_resources, 269 .dev = { 270 .platform_data = &omap2_mcspi1_config, 271 }, 272}; 273 274static struct omap2_mcspi_platform_config omap2_mcspi2_config = { 275 .num_cs = 2, 276}; 277 278static struct resource omap2_mcspi2_resources[] = { 279 { 280 .start = OMAP2_MCSPI2_BASE, 281 .end = OMAP2_MCSPI2_BASE + 0xff, 282 .flags = IORESOURCE_MEM, 283 }, 284}; 285 286static struct platform_device omap2_mcspi2 = { 287 .name = "omap2_mcspi", 288 .id = 2, 289 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), 290 .resource = omap2_mcspi2_resources, 291 .dev = { 292 .platform_data = &omap2_mcspi2_config, 293 }, 294}; 295 296#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ 297 defined(CONFIG_ARCH_OMAP4) 298static struct omap2_mcspi_platform_config omap2_mcspi3_config = { 299 .num_cs = 2, 300}; 301 302static struct resource omap2_mcspi3_resources[] = { 303 { 304 .start = OMAP2_MCSPI3_BASE, 305 .end = OMAP2_MCSPI3_BASE + 0xff, 306 .flags = IORESOURCE_MEM, 307 }, 308}; 309 310static struct platform_device omap2_mcspi3 = { 311 .name = "omap2_mcspi", 312 .id = 3, 313 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), 314 .resource = omap2_mcspi3_resources, 315 .dev = { 316 .platform_data = &omap2_mcspi3_config, 317 }, 318}; 319#endif 320 321#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 322static struct omap2_mcspi_platform_config omap2_mcspi4_config = { 323 .num_cs = 1, 324}; 325 326static struct resource omap2_mcspi4_resources[] = { 327 { 328 .start = OMAP2_MCSPI4_BASE, 329 .end = OMAP2_MCSPI4_BASE + 0xff, 330 .flags = IORESOURCE_MEM, 331 }, 332}; 333 334static struct platform_device omap2_mcspi4 = { 335 .name = "omap2_mcspi", 336 .id = 4, 337 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), 338 .resource = omap2_mcspi4_resources, 339 .dev = { 340 .platform_data = &omap2_mcspi4_config, 341 }, 342}; 343#endif 344 345#ifdef CONFIG_ARCH_OMAP4 346static inline void omap4_mcspi_fixup(void) 347{ 348 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; 349 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; 350 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; 351 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; 352 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; 353 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; 354 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; 355 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; 356} 357#else 358static inline void omap4_mcspi_fixup(void) 359{ 360} 361#endif 362 363#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ 364 defined(CONFIG_ARCH_OMAP4) 365static inline void omap2_mcspi3_init(void) 366{ 367 platform_device_register(&omap2_mcspi3); 368} 369#else 370static inline void omap2_mcspi3_init(void) 371{ 372} 373#endif 374 375#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 376static inline void omap2_mcspi4_init(void) 377{ 378 platform_device_register(&omap2_mcspi4); 379} 380#else 381static inline void omap2_mcspi4_init(void) 382{ 383} 384#endif 385 386static void omap_init_mcspi(void) 387{ 388 if (cpu_is_omap44xx()) 389 omap4_mcspi_fixup(); 390 391 platform_device_register(&omap2_mcspi1); 392 platform_device_register(&omap2_mcspi2); 393 394 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) 395 omap2_mcspi3_init(); 396 397 if (cpu_is_omap343x() || cpu_is_omap44xx()) 398 omap2_mcspi4_init(); 399} 400 401#else 402static inline void omap_init_mcspi(void) {} 403#endif 404 405static struct resource omap2_pmu_resource = { 406 .start = 3, 407 .end = 3, 408 .flags = IORESOURCE_IRQ, 409}; 410 411static struct resource omap3_pmu_resource = { 412 .start = INT_34XX_BENCH_MPU_EMUL, 413 .end = INT_34XX_BENCH_MPU_EMUL, 414 .flags = IORESOURCE_IRQ, 415}; 416 417static struct platform_device omap_pmu_device = { 418 .name = "arm-pmu", 419 .id = ARM_PMU_DEVICE_CPU, 420 .num_resources = 1, 421}; 422 423static void omap_init_pmu(void) 424{ 425 if (cpu_is_omap24xx()) 426 omap_pmu_device.resource = &omap2_pmu_resource; 427 else if (cpu_is_omap34xx()) 428 omap_pmu_device.resource = &omap3_pmu_resource; 429 else 430 return; 431 432 platform_device_register(&omap_pmu_device); 433} 434 435 436#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) 437 438#ifdef CONFIG_ARCH_OMAP2 439static struct resource omap2_sham_resources[] = { 440 { 441 .start = OMAP24XX_SEC_SHA1MD5_BASE, 442 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, 443 .flags = IORESOURCE_MEM, 444 }, 445 { 446 .start = INT_24XX_SHA1MD5, 447 .flags = IORESOURCE_IRQ, 448 } 449}; 450static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); 451#else 452#define omap2_sham_resources NULL 453#define omap2_sham_resources_sz 0 454#endif 455 456#ifdef CONFIG_ARCH_OMAP3 457static struct resource omap3_sham_resources[] = { 458 { 459 .start = OMAP34XX_SEC_SHA1MD5_BASE, 460 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, 461 .flags = IORESOURCE_MEM, 462 }, 463 { 464 .start = INT_34XX_SHA1MD52_IRQ, 465 .flags = IORESOURCE_IRQ, 466 }, 467 { 468 .start = OMAP34XX_DMA_SHA1MD5_RX, 469 .flags = IORESOURCE_DMA, 470 } 471}; 472static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); 473#else 474#define omap3_sham_resources NULL 475#define omap3_sham_resources_sz 0 476#endif 477 478static struct platform_device sham_device = { 479 .name = "omap-sham", 480 .id = -1, 481}; 482 483static void omap_init_sham(void) 484{ 485 if (cpu_is_omap24xx()) { 486 sham_device.resource = omap2_sham_resources; 487 sham_device.num_resources = omap2_sham_resources_sz; 488 } else if (cpu_is_omap34xx()) { 489 sham_device.resource = omap3_sham_resources; 490 sham_device.num_resources = omap3_sham_resources_sz; 491 } else { 492 pr_err("%s: platform not supported\n", __func__); 493 return; 494 } 495 platform_device_register(&sham_device); 496} 497#else 498static inline void omap_init_sham(void) { } 499#endif 500 501/*-------------------------------------------------------------------------*/ 502 503#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 504 505#define MMCHS_SYSCONFIG 0x0010 506#define MMCHS_SYSCONFIG_SWRESET (1 << 1) 507#define MMCHS_SYSSTATUS 0x0014 508#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 509 510static struct platform_device dummy_pdev = { 511 .dev = { 512 .bus = &platform_bus_type, 513 }, 514}; 515 516/** 517 * omap_hsmmc_reset() - Full reset of each HS-MMC controller 518 * 519 * Ensure that each MMC controller is fully reset. Controllers 520 * left in an unknown state (by bootloader) may prevent retention 521 * or OFF-mode. This is especially important in cases where the 522 * MMC driver is not enabled, _or_ built as a module. 523 * 524 * In order for reset to work, interface, functional and debounce 525 * clocks must be enabled. The debounce clock comes from func_32k_clk 526 * and is not under SW control, so we only enable i- and f-clocks. 527 **/ 528static void __init omap_hsmmc_reset(void) 529{ 530 u32 i, nr_controllers; 531 532 if (cpu_is_omap242x()) 533 return; 534 535 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : 536 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); 537 538 for (i = 0; i < nr_controllers; i++) { 539 u32 v, base = 0; 540 struct clk *iclk, *fclk; 541 struct device *dev = &dummy_pdev.dev; 542 543 switch (i) { 544 case 0: 545 base = OMAP2_MMC1_BASE; 546 break; 547 case 1: 548 base = OMAP2_MMC2_BASE; 549 break; 550 case 2: 551 base = OMAP3_MMC3_BASE; 552 break; 553 case 3: 554 if (!cpu_is_omap44xx()) 555 return; 556 base = OMAP4_MMC4_BASE; 557 break; 558 case 4: 559 if (!cpu_is_omap44xx()) 560 return; 561 base = OMAP4_MMC5_BASE; 562 break; 563 } 564 565 if (cpu_is_omap44xx()) 566 base += OMAP4_MMC_REG_OFFSET; 567 568 dummy_pdev.id = i; 569 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); 570 iclk = clk_get(dev, "ick"); 571 if (iclk && clk_enable(iclk)) 572 iclk = NULL; 573 574 fclk = clk_get(dev, "fck"); 575 if (fclk && clk_enable(fclk)) 576 fclk = NULL; 577 578 if (!iclk || !fclk) { 579 printk(KERN_WARNING 580 "%s: Unable to enable clocks for MMC%d, " 581 "cannot reset.\n", __func__, i); 582 break; 583 } 584 585 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); 586 v = omap_readl(base + MMCHS_SYSSTATUS); 587 while (!(omap_readl(base + MMCHS_SYSSTATUS) & 588 MMCHS_SYSSTATUS_RESETDONE)) 589 cpu_relax(); 590 591 if (fclk) { 592 clk_disable(fclk); 593 clk_put(fclk); 594 } 595 if (iclk) { 596 clk_disable(iclk); 597 clk_put(iclk); 598 } 599 } 600} 601#else 602static inline void omap_hsmmc_reset(void) {} 603#endif 604 605#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ 606 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 607 608static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, 609 int controller_nr) 610{ 611 if ((mmc_controller->slots[0].switch_pin > 0) && \ 612 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) 613 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, 614 OMAP_PIN_INPUT_PULLUP); 615 if ((mmc_controller->slots[0].gpio_wp > 0) && \ 616 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) 617 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, 618 OMAP_PIN_INPUT_PULLUP); 619 620 if (cpu_is_omap2420() && controller_nr == 0) { 621 omap_mux_init_signal("sdmmc_cmd", 0); 622 omap_mux_init_signal("sdmmc_clki", 0); 623 omap_mux_init_signal("sdmmc_clko", 0); 624 omap_mux_init_signal("sdmmc_dat0", 0); 625 omap_mux_init_signal("sdmmc_dat_dir0", 0); 626 omap_mux_init_signal("sdmmc_cmd_dir", 0); 627 if (mmc_controller->slots[0].wires == 4) { 628 omap_mux_init_signal("sdmmc_dat1", 0); 629 omap_mux_init_signal("sdmmc_dat2", 0); 630 omap_mux_init_signal("sdmmc_dat3", 0); 631 omap_mux_init_signal("sdmmc_dat_dir1", 0); 632 omap_mux_init_signal("sdmmc_dat_dir2", 0); 633 omap_mux_init_signal("sdmmc_dat_dir3", 0); 634 } 635 636 /* 637 * Use internal loop-back in MMC/SDIO Module Input Clock 638 * selection 639 */ 640 if (mmc_controller->slots[0].internal_clock) { 641 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 642 v |= (1 << 24); 643 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); 644 } 645 } 646 647 if (cpu_is_omap34xx()) { 648 if (controller_nr == 0) { 649 omap_mux_init_signal("sdmmc1_clk", 650 OMAP_PIN_INPUT_PULLUP); 651 omap_mux_init_signal("sdmmc1_cmd", 652 OMAP_PIN_INPUT_PULLUP); 653 omap_mux_init_signal("sdmmc1_dat0", 654 OMAP_PIN_INPUT_PULLUP); 655 if (mmc_controller->slots[0].wires == 4 || 656 mmc_controller->slots[0].wires == 8) { 657 omap_mux_init_signal("sdmmc1_dat1", 658 OMAP_PIN_INPUT_PULLUP); 659 omap_mux_init_signal("sdmmc1_dat2", 660 OMAP_PIN_INPUT_PULLUP); 661 omap_mux_init_signal("sdmmc1_dat3", 662 OMAP_PIN_INPUT_PULLUP); 663 } 664 if (mmc_controller->slots[0].wires == 8) { 665 omap_mux_init_signal("sdmmc1_dat4", 666 OMAP_PIN_INPUT_PULLUP); 667 omap_mux_init_signal("sdmmc1_dat5", 668 OMAP_PIN_INPUT_PULLUP); 669 omap_mux_init_signal("sdmmc1_dat6", 670 OMAP_PIN_INPUT_PULLUP); 671 omap_mux_init_signal("sdmmc1_dat7", 672 OMAP_PIN_INPUT_PULLUP); 673 } 674 } 675 if (controller_nr == 1) { 676 /* MMC2 */ 677 omap_mux_init_signal("sdmmc2_clk", 678 OMAP_PIN_INPUT_PULLUP); 679 omap_mux_init_signal("sdmmc2_cmd", 680 OMAP_PIN_INPUT_PULLUP); 681 omap_mux_init_signal("sdmmc2_dat0", 682 OMAP_PIN_INPUT_PULLUP); 683 684 /* 685 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed 686 * in the board-*.c files 687 */ 688 if (mmc_controller->slots[0].wires == 4 || 689 mmc_controller->slots[0].wires == 8) { 690 omap_mux_init_signal("sdmmc2_dat1", 691 OMAP_PIN_INPUT_PULLUP); 692 omap_mux_init_signal("sdmmc2_dat2", 693 OMAP_PIN_INPUT_PULLUP); 694 omap_mux_init_signal("sdmmc2_dat3", 695 OMAP_PIN_INPUT_PULLUP); 696 } 697 if (mmc_controller->slots[0].wires == 8) { 698 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", 699 OMAP_PIN_INPUT_PULLUP); 700 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", 701 OMAP_PIN_INPUT_PULLUP); 702 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", 703 OMAP_PIN_INPUT_PULLUP); 704 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", 705 OMAP_PIN_INPUT_PULLUP); 706 } 707 } 708 709 /* 710 * For MMC3 the pins need to be muxed in the board-*.c files 711 */ 712 } 713} 714 715void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 716 int nr_controllers) 717{ 718 int i; 719 char *name; 720 721 for (i = 0; i < nr_controllers; i++) { 722 unsigned long base, size; 723 unsigned int irq = 0; 724 725 if (!mmc_data[i]) 726 continue; 727 728 omap2_mmc_mux(mmc_data[i], i); 729 730 switch (i) { 731 case 0: 732 base = OMAP2_MMC1_BASE; 733 irq = INT_24XX_MMC_IRQ; 734 break; 735 case 1: 736 base = OMAP2_MMC2_BASE; 737 irq = INT_24XX_MMC2_IRQ; 738 break; 739 case 2: 740 if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) 741 return; 742 base = OMAP3_MMC3_BASE; 743 irq = INT_34XX_MMC3_IRQ; 744 break; 745 case 3: 746 if (!cpu_is_omap44xx()) 747 return; 748 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; 749 irq = OMAP44XX_IRQ_MMC4; 750 break; 751 case 4: 752 if (!cpu_is_omap44xx()) 753 return; 754 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; 755 irq = OMAP44XX_IRQ_MMC5; 756 break; 757 default: 758 continue; 759 } 760 761 if (cpu_is_omap2420()) { 762 size = OMAP2420_MMC_SIZE; 763 name = "mmci-omap"; 764 } else if (cpu_is_omap44xx()) { 765 if (i < 3) { 766 base += OMAP4_MMC_REG_OFFSET; 767 irq += OMAP44XX_IRQ_GIC_START; 768 } 769 size = OMAP4_HSMMC_SIZE; 770 name = "mmci-omap-hs"; 771 } else { 772 size = OMAP3_HSMMC_SIZE; 773 name = "mmci-omap-hs"; 774 } 775 omap_mmc_add(name, i, base, size, irq, mmc_data[i]); 776 }; 777} 778 779#endif 780 781/*-------------------------------------------------------------------------*/ 782 783#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) 784#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 785#define OMAP_HDQ_BASE 0x480B2000 786#endif 787static struct resource omap_hdq_resources[] = { 788 { 789 .start = OMAP_HDQ_BASE, 790 .end = OMAP_HDQ_BASE + 0x1C, 791 .flags = IORESOURCE_MEM, 792 }, 793 { 794 .start = INT_24XX_HDQ_IRQ, 795 .flags = IORESOURCE_IRQ, 796 }, 797}; 798static struct platform_device omap_hdq_dev = { 799 .name = "omap_hdq", 800 .id = 0, 801 .dev = { 802 .platform_data = NULL, 803 }, 804 .num_resources = ARRAY_SIZE(omap_hdq_resources), 805 .resource = omap_hdq_resources, 806}; 807static inline void omap_hdq_init(void) 808{ 809 (void) platform_device_register(&omap_hdq_dev); 810} 811#else 812static inline void omap_hdq_init(void) {} 813#endif 814 815/*---------------------------------------------------------------------------*/ 816 817#if defined(CONFIG_VIDEO_OMAP2_VOUT) || defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) 818#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) 819static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { 820}; 821#else 822static struct resource omap_vout_resource[2] = { 823}; 824#endif 825 826static struct platform_device omap_vout_device = { 827 .name = "omap_vout", 828 .num_resources = ARRAY_SIZE(omap_vout_resource), 829 .resource = &omap_vout_resource[0], 830 .id = -1, 831}; 832static void omap_init_vout(void) 833{ 834 if (platform_device_register(&omap_vout_device) < 0) 835 printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); 836} 837#else 838static inline void omap_init_vout(void) {} 839#endif 840 841/*-------------------------------------------------------------------------*/ 842 843static int __init omap2_init_devices(void) 844{ 845 /* please keep these calls, and their implementations above, 846 * in alphabetical order so they're easier to sort through. 847 */ 848 omap_hsmmc_reset(); 849 omap_init_camera(); 850 omap_init_mbox(); 851 omap_init_mcspi(); 852 omap_init_pmu(); 853 omap_hdq_init(); 854 omap_init_sti(); 855 omap_init_sham(); 856 omap_init_vout(); 857 858 return 0; 859} 860arch_initcall(omap2_init_devices); 861