1/* 2 * arch/arm/mach-at91/at91rm9200_devices.c 3 * 4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> 5 * Copyright (C) 2005 David Brownell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13#include <asm/mach/arch.h> 14#include <asm/mach/map.h> 15 16#include <linux/dma-mapping.h> 17#include <linux/platform_device.h> 18#include <linux/i2c-gpio.h> 19 20#include <mach/board.h> 21#include <mach/gpio.h> 22#include <mach/at91rm9200.h> 23#include <mach/at91rm9200_mc.h> 24 25#include "generic.h" 26 27 28/* -------------------------------------------------------------------- 29 * USB Host 30 * -------------------------------------------------------------------- */ 31 32#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 33static u64 ohci_dmamask = DMA_BIT_MASK(32); 34static struct at91_usbh_data usbh_data; 35 36static struct resource usbh_resources[] = { 37 [0] = { 38 .start = AT91RM9200_UHP_BASE, 39 .end = AT91RM9200_UHP_BASE + SZ_1M - 1, 40 .flags = IORESOURCE_MEM, 41 }, 42 [1] = { 43 .start = AT91RM9200_ID_UHP, 44 .end = AT91RM9200_ID_UHP, 45 .flags = IORESOURCE_IRQ, 46 }, 47}; 48 49static struct platform_device at91rm9200_usbh_device = { 50 .name = "at91_ohci", 51 .id = -1, 52 .dev = { 53 .dma_mask = &ohci_dmamask, 54 .coherent_dma_mask = DMA_BIT_MASK(32), 55 .platform_data = &usbh_data, 56 }, 57 .resource = usbh_resources, 58 .num_resources = ARRAY_SIZE(usbh_resources), 59}; 60 61void __init at91_add_device_usbh(struct at91_usbh_data *data) 62{ 63 if (!data) 64 return; 65 66 usbh_data = *data; 67 platform_device_register(&at91rm9200_usbh_device); 68} 69#else 70void __init at91_add_device_usbh(struct at91_usbh_data *data) {} 71#endif 72 73 74/* -------------------------------------------------------------------- 75 * USB Device (Gadget) 76 * -------------------------------------------------------------------- */ 77 78#ifdef CONFIG_USB_GADGET_AT91 79static struct at91_udc_data udc_data; 80 81static struct resource udc_resources[] = { 82 [0] = { 83 .start = AT91RM9200_BASE_UDP, 84 .end = AT91RM9200_BASE_UDP + SZ_16K - 1, 85 .flags = IORESOURCE_MEM, 86 }, 87 [1] = { 88 .start = AT91RM9200_ID_UDP, 89 .end = AT91RM9200_ID_UDP, 90 .flags = IORESOURCE_IRQ, 91 }, 92}; 93 94static struct platform_device at91rm9200_udc_device = { 95 .name = "at91_udc", 96 .id = -1, 97 .dev = { 98 .platform_data = &udc_data, 99 }, 100 .resource = udc_resources, 101 .num_resources = ARRAY_SIZE(udc_resources), 102}; 103 104void __init at91_add_device_udc(struct at91_udc_data *data) 105{ 106 if (!data) 107 return; 108 109 if (data->vbus_pin) { 110 at91_set_gpio_input(data->vbus_pin, 0); 111 at91_set_deglitch(data->vbus_pin, 1); 112 } 113 if (data->pullup_pin) 114 at91_set_gpio_output(data->pullup_pin, 0); 115 116 udc_data = *data; 117 platform_device_register(&at91rm9200_udc_device); 118} 119#else 120void __init at91_add_device_udc(struct at91_udc_data *data) {} 121#endif 122 123 124/* -------------------------------------------------------------------- 125 * Ethernet 126 * -------------------------------------------------------------------- */ 127 128#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE) 129static u64 eth_dmamask = DMA_BIT_MASK(32); 130static struct at91_eth_data eth_data; 131 132static struct resource eth_resources[] = { 133 [0] = { 134 .start = AT91_VA_BASE_EMAC, 135 .end = AT91_VA_BASE_EMAC + SZ_16K - 1, 136 .flags = IORESOURCE_MEM, 137 }, 138 [1] = { 139 .start = AT91RM9200_ID_EMAC, 140 .end = AT91RM9200_ID_EMAC, 141 .flags = IORESOURCE_IRQ, 142 }, 143}; 144 145static struct platform_device at91rm9200_eth_device = { 146 .name = "at91_ether", 147 .id = -1, 148 .dev = { 149 .dma_mask = ð_dmamask, 150 .coherent_dma_mask = DMA_BIT_MASK(32), 151 .platform_data = ð_data, 152 }, 153 .resource = eth_resources, 154 .num_resources = ARRAY_SIZE(eth_resources), 155}; 156 157void __init at91_add_device_eth(struct at91_eth_data *data) 158{ 159 if (!data) 160 return; 161 162 if (data->phy_irq_pin) { 163 at91_set_gpio_input(data->phy_irq_pin, 0); 164 at91_set_deglitch(data->phy_irq_pin, 1); 165 } 166 167 /* Pins used for MII and RMII */ 168 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */ 169 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */ 170 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */ 171 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ 172 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ 173 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */ 174 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */ 175 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */ 176 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ 177 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ 178 179 if (!data->is_rmii) { 180 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ 181 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ 182 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ 183 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */ 184 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */ 185 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */ 186 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */ 187 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */ 188 } 189 190 eth_data = *data; 191 platform_device_register(&at91rm9200_eth_device); 192} 193#else 194void __init at91_add_device_eth(struct at91_eth_data *data) {} 195#endif 196 197 198/* -------------------------------------------------------------------- 199 * Compact Flash / PCMCIA 200 * -------------------------------------------------------------------- */ 201 202#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) 203static struct at91_cf_data cf_data; 204 205#define CF_BASE AT91_CHIPSELECT_4 206 207static struct resource cf_resources[] = { 208 [0] = { 209 .start = CF_BASE, 210 /* ties up CS4, CS5 and CS6 */ 211 .end = CF_BASE + (0x30000000 - 1), 212 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT, 213 }, 214}; 215 216static struct platform_device at91rm9200_cf_device = { 217 .name = "at91_cf", 218 .id = -1, 219 .dev = { 220 .platform_data = &cf_data, 221 }, 222 .resource = cf_resources, 223 .num_resources = ARRAY_SIZE(cf_resources), 224}; 225 226void __init at91_add_device_cf(struct at91_cf_data *data) 227{ 228 unsigned int csa; 229 230 if (!data) 231 return; 232 233 data->chipselect = 4; /* can only use EBI ChipSelect 4 */ 234 235 /* CF takes over CS4, CS5, CS6 */ 236 csa = at91_sys_read(AT91_EBI_CSA); 237 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH); 238 239 /* 240 * Static memory controller timing adjustments. 241 * REVISIT: these timings are in terms of MCK cycles, so 242 * when MCK changes (cpufreq etc) so must these values... 243 */ 244 at91_sys_write(AT91_SMC_CSR(4), 245 AT91_SMC_ACSS_STD 246 | AT91_SMC_DBW_16 247 | AT91_SMC_BAT 248 | AT91_SMC_WSEN 249 | AT91_SMC_NWS_(32) /* wait states */ 250 | AT91_SMC_RWSETUP_(6) /* setup time */ 251 | AT91_SMC_RWHOLD_(4) /* hold time */ 252 ); 253 254 /* input/irq */ 255 if (data->irq_pin) { 256 at91_set_gpio_input(data->irq_pin, 1); 257 at91_set_deglitch(data->irq_pin, 1); 258 } 259 at91_set_gpio_input(data->det_pin, 1); 260 at91_set_deglitch(data->det_pin, 1); 261 262 /* outputs, initially off */ 263 if (data->vcc_pin) 264 at91_set_gpio_output(data->vcc_pin, 0); 265 at91_set_gpio_output(data->rst_pin, 0); 266 267 /* force poweron defaults for these pins ... */ 268 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */ 269 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */ 270 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */ 271 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */ 272 273 /* nWAIT is _not_ a default setting */ 274 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */ 275 276 cf_data = *data; 277 platform_device_register(&at91rm9200_cf_device); 278} 279#else 280void __init at91_add_device_cf(struct at91_cf_data *data) {} 281#endif 282 283 284/* -------------------------------------------------------------------- 285 * MMC / SD 286 * -------------------------------------------------------------------- */ 287 288#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) 289static u64 mmc_dmamask = DMA_BIT_MASK(32); 290static struct at91_mmc_data mmc_data; 291 292static struct resource mmc_resources[] = { 293 [0] = { 294 .start = AT91RM9200_BASE_MCI, 295 .end = AT91RM9200_BASE_MCI + SZ_16K - 1, 296 .flags = IORESOURCE_MEM, 297 }, 298 [1] = { 299 .start = AT91RM9200_ID_MCI, 300 .end = AT91RM9200_ID_MCI, 301 .flags = IORESOURCE_IRQ, 302 }, 303}; 304 305static struct platform_device at91rm9200_mmc_device = { 306 .name = "at91_mci", 307 .id = -1, 308 .dev = { 309 .dma_mask = &mmc_dmamask, 310 .coherent_dma_mask = DMA_BIT_MASK(32), 311 .platform_data = &mmc_data, 312 }, 313 .resource = mmc_resources, 314 .num_resources = ARRAY_SIZE(mmc_resources), 315}; 316 317void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) 318{ 319 if (!data) 320 return; 321 322 /* input/irq */ 323 if (data->det_pin) { 324 at91_set_gpio_input(data->det_pin, 1); 325 at91_set_deglitch(data->det_pin, 1); 326 } 327 if (data->wp_pin) 328 at91_set_gpio_input(data->wp_pin, 1); 329 if (data->vcc_pin) 330 at91_set_gpio_output(data->vcc_pin, 0); 331 332 /* CLK */ 333 at91_set_A_periph(AT91_PIN_PA27, 0); 334 335 if (data->slot_b) { 336 /* CMD */ 337 at91_set_B_periph(AT91_PIN_PA8, 1); 338 339 /* DAT0, maybe DAT1..DAT3 */ 340 at91_set_B_periph(AT91_PIN_PA9, 1); 341 if (data->wire4) { 342 at91_set_B_periph(AT91_PIN_PA10, 1); 343 at91_set_B_periph(AT91_PIN_PA11, 1); 344 at91_set_B_periph(AT91_PIN_PA12, 1); 345 } 346 } else { 347 /* CMD */ 348 at91_set_A_periph(AT91_PIN_PA28, 1); 349 350 /* DAT0, maybe DAT1..DAT3 */ 351 at91_set_A_periph(AT91_PIN_PA29, 1); 352 if (data->wire4) { 353 at91_set_B_periph(AT91_PIN_PB3, 1); 354 at91_set_B_periph(AT91_PIN_PB4, 1); 355 at91_set_B_periph(AT91_PIN_PB5, 1); 356 } 357 } 358 359 mmc_data = *data; 360 platform_device_register(&at91rm9200_mmc_device); 361} 362#else 363void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 364#endif 365 366 367/* -------------------------------------------------------------------- 368 * NAND / SmartMedia 369 * -------------------------------------------------------------------- */ 370 371#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) 372static struct atmel_nand_data nand_data; 373 374#define NAND_BASE AT91_CHIPSELECT_3 375 376static struct resource nand_resources[] = { 377 { 378 .start = NAND_BASE, 379 .end = NAND_BASE + SZ_256M - 1, 380 .flags = IORESOURCE_MEM, 381 } 382}; 383 384static struct platform_device at91rm9200_nand_device = { 385 .name = "atmel_nand", 386 .id = -1, 387 .dev = { 388 .platform_data = &nand_data, 389 }, 390 .resource = nand_resources, 391 .num_resources = ARRAY_SIZE(nand_resources), 392}; 393 394void __init at91_add_device_nand(struct atmel_nand_data *data) 395{ 396 unsigned int csa; 397 398 if (!data) 399 return; 400 401 /* enable the address range of CS3 */ 402 csa = at91_sys_read(AT91_EBI_CSA); 403 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA); 404 405 /* set the bus interface characteristics */ 406 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN 407 | AT91_SMC_NWS_(5) 408 | AT91_SMC_TDF_(1) 409 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */ 410 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */ 411 ); 412 413 /* enable pin */ 414 if (data->enable_pin) 415 at91_set_gpio_output(data->enable_pin, 1); 416 417 /* ready/busy pin */ 418 if (data->rdy_pin) 419 at91_set_gpio_input(data->rdy_pin, 1); 420 421 /* card detect pin */ 422 if (data->det_pin) 423 at91_set_gpio_input(data->det_pin, 1); 424 425 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */ 426 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */ 427 428 nand_data = *data; 429 platform_device_register(&at91rm9200_nand_device); 430} 431#else 432void __init at91_add_device_nand(struct atmel_nand_data *data) {} 433#endif 434 435 436/* -------------------------------------------------------------------- 437 * TWI (i2c) 438 * -------------------------------------------------------------------- */ 439 440/* 441 * Prefer the GPIO code since the TWI controller isn't robust 442 * (gets overruns and underruns under load) and can only issue 443 * repeated STARTs in one scenario (the driver doesn't yet handle them). 444 */ 445#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 446 447static struct i2c_gpio_platform_data pdata = { 448 .sda_pin = AT91_PIN_PA25, 449 .sda_is_open_drain = 1, 450 .scl_pin = AT91_PIN_PA26, 451 .scl_is_open_drain = 1, 452 .udelay = 2, /* ~100 kHz */ 453}; 454 455static struct platform_device at91rm9200_twi_device = { 456 .name = "i2c-gpio", 457 .id = -1, 458 .dev.platform_data = &pdata, 459}; 460 461void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 462{ 463 at91_set_GPIO_periph(AT91_PIN_PA25, 1); /* TWD (SDA) */ 464 at91_set_multi_drive(AT91_PIN_PA25, 1); 465 466 at91_set_GPIO_periph(AT91_PIN_PA26, 1); /* TWCK (SCL) */ 467 at91_set_multi_drive(AT91_PIN_PA26, 1); 468 469 i2c_register_board_info(0, devices, nr_devices); 470 platform_device_register(&at91rm9200_twi_device); 471} 472 473#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) 474 475static struct resource twi_resources[] = { 476 [0] = { 477 .start = AT91RM9200_BASE_TWI, 478 .end = AT91RM9200_BASE_TWI + SZ_16K - 1, 479 .flags = IORESOURCE_MEM, 480 }, 481 [1] = { 482 .start = AT91RM9200_ID_TWI, 483 .end = AT91RM9200_ID_TWI, 484 .flags = IORESOURCE_IRQ, 485 }, 486}; 487 488static struct platform_device at91rm9200_twi_device = { 489 .name = "at91_i2c", 490 .id = -1, 491 .resource = twi_resources, 492 .num_resources = ARRAY_SIZE(twi_resources), 493}; 494 495void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 496{ 497 /* pins used for TWI interface */ 498 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */ 499 at91_set_multi_drive(AT91_PIN_PA25, 1); 500 501 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */ 502 at91_set_multi_drive(AT91_PIN_PA26, 1); 503 504 i2c_register_board_info(0, devices, nr_devices); 505 platform_device_register(&at91rm9200_twi_device); 506} 507#else 508void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} 509#endif 510 511 512/* -------------------------------------------------------------------- 513 * SPI 514 * -------------------------------------------------------------------- */ 515 516#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) 517static u64 spi_dmamask = DMA_BIT_MASK(32); 518 519static struct resource spi_resources[] = { 520 [0] = { 521 .start = AT91RM9200_BASE_SPI, 522 .end = AT91RM9200_BASE_SPI + SZ_16K - 1, 523 .flags = IORESOURCE_MEM, 524 }, 525 [1] = { 526 .start = AT91RM9200_ID_SPI, 527 .end = AT91RM9200_ID_SPI, 528 .flags = IORESOURCE_IRQ, 529 }, 530}; 531 532static struct platform_device at91rm9200_spi_device = { 533 .name = "atmel_spi", 534 .id = 0, 535 .dev = { 536 .dma_mask = &spi_dmamask, 537 .coherent_dma_mask = DMA_BIT_MASK(32), 538 }, 539 .resource = spi_resources, 540 .num_resources = ARRAY_SIZE(spi_resources), 541}; 542 543static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; 544 545void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) 546{ 547 int i; 548 unsigned long cs_pin; 549 550 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */ 551 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */ 552 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */ 553 554 /* Enable SPI chip-selects */ 555 for (i = 0; i < nr_devices; i++) { 556 if (devices[i].controller_data) 557 cs_pin = (unsigned long) devices[i].controller_data; 558 else 559 cs_pin = spi_standard_cs[devices[i].chip_select]; 560 561 if (devices[i].chip_select == 0) /* for CS0 errata */ 562 at91_set_A_periph(cs_pin, 0); 563 else 564 at91_set_gpio_output(cs_pin, 1); 565 566 567 /* pass chip-select pin to driver */ 568 devices[i].controller_data = (void *) cs_pin; 569 } 570 571 spi_register_board_info(devices, nr_devices); 572 platform_device_register(&at91rm9200_spi_device); 573} 574#else 575void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} 576#endif 577 578 579/* -------------------------------------------------------------------- 580 * Timer/Counter blocks 581 * -------------------------------------------------------------------- */ 582 583#ifdef CONFIG_ATMEL_TCLIB 584 585static struct resource tcb0_resources[] = { 586 [0] = { 587 .start = AT91RM9200_BASE_TCB0, 588 .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1, 589 .flags = IORESOURCE_MEM, 590 }, 591 [1] = { 592 .start = AT91RM9200_ID_TC0, 593 .end = AT91RM9200_ID_TC0, 594 .flags = IORESOURCE_IRQ, 595 }, 596 [2] = { 597 .start = AT91RM9200_ID_TC1, 598 .end = AT91RM9200_ID_TC1, 599 .flags = IORESOURCE_IRQ, 600 }, 601 [3] = { 602 .start = AT91RM9200_ID_TC2, 603 .end = AT91RM9200_ID_TC2, 604 .flags = IORESOURCE_IRQ, 605 }, 606}; 607 608static struct platform_device at91rm9200_tcb0_device = { 609 .name = "atmel_tcb", 610 .id = 0, 611 .resource = tcb0_resources, 612 .num_resources = ARRAY_SIZE(tcb0_resources), 613}; 614 615static struct resource tcb1_resources[] = { 616 [0] = { 617 .start = AT91RM9200_BASE_TCB1, 618 .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1, 619 .flags = IORESOURCE_MEM, 620 }, 621 [1] = { 622 .start = AT91RM9200_ID_TC3, 623 .end = AT91RM9200_ID_TC3, 624 .flags = IORESOURCE_IRQ, 625 }, 626 [2] = { 627 .start = AT91RM9200_ID_TC4, 628 .end = AT91RM9200_ID_TC4, 629 .flags = IORESOURCE_IRQ, 630 }, 631 [3] = { 632 .start = AT91RM9200_ID_TC5, 633 .end = AT91RM9200_ID_TC5, 634 .flags = IORESOURCE_IRQ, 635 }, 636}; 637 638static struct platform_device at91rm9200_tcb1_device = { 639 .name = "atmel_tcb", 640 .id = 1, 641 .resource = tcb1_resources, 642 .num_resources = ARRAY_SIZE(tcb1_resources), 643}; 644 645static void __init at91_add_device_tc(void) 646{ 647 /* this chip has a separate clock and irq for each TC channel */ 648 at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk"); 649 at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk"); 650 at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk"); 651 platform_device_register(&at91rm9200_tcb0_device); 652 653 at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk"); 654 at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk"); 655 at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk"); 656 platform_device_register(&at91rm9200_tcb1_device); 657} 658#else 659static void __init at91_add_device_tc(void) { } 660#endif 661 662 663/* -------------------------------------------------------------------- 664 * RTC 665 * -------------------------------------------------------------------- */ 666 667#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) 668static struct platform_device at91rm9200_rtc_device = { 669 .name = "at91_rtc", 670 .id = -1, 671 .num_resources = 0, 672}; 673 674static void __init at91_add_device_rtc(void) 675{ 676 platform_device_register(&at91rm9200_rtc_device); 677} 678#else 679static void __init at91_add_device_rtc(void) {} 680#endif 681 682 683/* -------------------------------------------------------------------- 684 * Watchdog 685 * -------------------------------------------------------------------- */ 686 687#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE) 688static struct platform_device at91rm9200_wdt_device = { 689 .name = "at91_wdt", 690 .id = -1, 691 .num_resources = 0, 692}; 693 694static void __init at91_add_device_watchdog(void) 695{ 696 platform_device_register(&at91rm9200_wdt_device); 697} 698#else 699static void __init at91_add_device_watchdog(void) {} 700#endif 701 702 703/* -------------------------------------------------------------------- 704 * SSC -- Synchronous Serial Controller 705 * -------------------------------------------------------------------- */ 706 707#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) 708static u64 ssc0_dmamask = DMA_BIT_MASK(32); 709 710static struct resource ssc0_resources[] = { 711 [0] = { 712 .start = AT91RM9200_BASE_SSC0, 713 .end = AT91RM9200_BASE_SSC0 + SZ_16K - 1, 714 .flags = IORESOURCE_MEM, 715 }, 716 [1] = { 717 .start = AT91RM9200_ID_SSC0, 718 .end = AT91RM9200_ID_SSC0, 719 .flags = IORESOURCE_IRQ, 720 }, 721}; 722 723static struct platform_device at91rm9200_ssc0_device = { 724 .name = "ssc", 725 .id = 0, 726 .dev = { 727 .dma_mask = &ssc0_dmamask, 728 .coherent_dma_mask = DMA_BIT_MASK(32), 729 }, 730 .resource = ssc0_resources, 731 .num_resources = ARRAY_SIZE(ssc0_resources), 732}; 733 734static inline void configure_ssc0_pins(unsigned pins) 735{ 736 if (pins & ATMEL_SSC_TF) 737 at91_set_A_periph(AT91_PIN_PB0, 1); 738 if (pins & ATMEL_SSC_TK) 739 at91_set_A_periph(AT91_PIN_PB1, 1); 740 if (pins & ATMEL_SSC_TD) 741 at91_set_A_periph(AT91_PIN_PB2, 1); 742 if (pins & ATMEL_SSC_RD) 743 at91_set_A_periph(AT91_PIN_PB3, 1); 744 if (pins & ATMEL_SSC_RK) 745 at91_set_A_periph(AT91_PIN_PB4, 1); 746 if (pins & ATMEL_SSC_RF) 747 at91_set_A_periph(AT91_PIN_PB5, 1); 748} 749 750static u64 ssc1_dmamask = DMA_BIT_MASK(32); 751 752static struct resource ssc1_resources[] = { 753 [0] = { 754 .start = AT91RM9200_BASE_SSC1, 755 .end = AT91RM9200_BASE_SSC1 + SZ_16K - 1, 756 .flags = IORESOURCE_MEM, 757 }, 758 [1] = { 759 .start = AT91RM9200_ID_SSC1, 760 .end = AT91RM9200_ID_SSC1, 761 .flags = IORESOURCE_IRQ, 762 }, 763}; 764 765static struct platform_device at91rm9200_ssc1_device = { 766 .name = "ssc", 767 .id = 1, 768 .dev = { 769 .dma_mask = &ssc1_dmamask, 770 .coherent_dma_mask = DMA_BIT_MASK(32), 771 }, 772 .resource = ssc1_resources, 773 .num_resources = ARRAY_SIZE(ssc1_resources), 774}; 775 776static inline void configure_ssc1_pins(unsigned pins) 777{ 778 if (pins & ATMEL_SSC_TF) 779 at91_set_A_periph(AT91_PIN_PB6, 1); 780 if (pins & ATMEL_SSC_TK) 781 at91_set_A_periph(AT91_PIN_PB7, 1); 782 if (pins & ATMEL_SSC_TD) 783 at91_set_A_periph(AT91_PIN_PB8, 1); 784 if (pins & ATMEL_SSC_RD) 785 at91_set_A_periph(AT91_PIN_PB9, 1); 786 if (pins & ATMEL_SSC_RK) 787 at91_set_A_periph(AT91_PIN_PB10, 1); 788 if (pins & ATMEL_SSC_RF) 789 at91_set_A_periph(AT91_PIN_PB11, 1); 790} 791 792static u64 ssc2_dmamask = DMA_BIT_MASK(32); 793 794static struct resource ssc2_resources[] = { 795 [0] = { 796 .start = AT91RM9200_BASE_SSC2, 797 .end = AT91RM9200_BASE_SSC2 + SZ_16K - 1, 798 .flags = IORESOURCE_MEM, 799 }, 800 [1] = { 801 .start = AT91RM9200_ID_SSC2, 802 .end = AT91RM9200_ID_SSC2, 803 .flags = IORESOURCE_IRQ, 804 }, 805}; 806 807static struct platform_device at91rm9200_ssc2_device = { 808 .name = "ssc", 809 .id = 2, 810 .dev = { 811 .dma_mask = &ssc2_dmamask, 812 .coherent_dma_mask = DMA_BIT_MASK(32), 813 }, 814 .resource = ssc2_resources, 815 .num_resources = ARRAY_SIZE(ssc2_resources), 816}; 817 818static inline void configure_ssc2_pins(unsigned pins) 819{ 820 if (pins & ATMEL_SSC_TF) 821 at91_set_A_periph(AT91_PIN_PB12, 1); 822 if (pins & ATMEL_SSC_TK) 823 at91_set_A_periph(AT91_PIN_PB13, 1); 824 if (pins & ATMEL_SSC_TD) 825 at91_set_A_periph(AT91_PIN_PB14, 1); 826 if (pins & ATMEL_SSC_RD) 827 at91_set_A_periph(AT91_PIN_PB15, 1); 828 if (pins & ATMEL_SSC_RK) 829 at91_set_A_periph(AT91_PIN_PB16, 1); 830 if (pins & ATMEL_SSC_RF) 831 at91_set_A_periph(AT91_PIN_PB17, 1); 832} 833 834/* 835 * SSC controllers are accessed through library code, instead of any 836 * kind of all-singing/all-dancing driver. For example one could be 837 * used by a particular I2S audio codec's driver, while another one 838 * on the same system might be used by a custom data capture driver. 839 */ 840void __init at91_add_device_ssc(unsigned id, unsigned pins) 841{ 842 struct platform_device *pdev; 843 844 /* 845 * NOTE: caller is responsible for passing information matching 846 * "pins" to whatever will be using each particular controller. 847 */ 848 switch (id) { 849 case AT91RM9200_ID_SSC0: 850 pdev = &at91rm9200_ssc0_device; 851 configure_ssc0_pins(pins); 852 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc"); 853 break; 854 case AT91RM9200_ID_SSC1: 855 pdev = &at91rm9200_ssc1_device; 856 configure_ssc1_pins(pins); 857 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc"); 858 break; 859 case AT91RM9200_ID_SSC2: 860 pdev = &at91rm9200_ssc2_device; 861 configure_ssc2_pins(pins); 862 at91_clock_associate("ssc2_clk", &pdev->dev, "ssc"); 863 break; 864 default: 865 return; 866 } 867 868 platform_device_register(pdev); 869} 870 871#else 872void __init at91_add_device_ssc(unsigned id, unsigned pins) {} 873#endif 874 875 876/* -------------------------------------------------------------------- 877 * UART 878 * -------------------------------------------------------------------- */ 879 880#if defined(CONFIG_SERIAL_ATMEL) 881static struct resource dbgu_resources[] = { 882 [0] = { 883 .start = AT91_VA_BASE_SYS + AT91_DBGU, 884 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, 885 .flags = IORESOURCE_MEM, 886 }, 887 [1] = { 888 .start = AT91_ID_SYS, 889 .end = AT91_ID_SYS, 890 .flags = IORESOURCE_IRQ, 891 }, 892}; 893 894static struct atmel_uart_data dbgu_data = { 895 .use_dma_tx = 0, 896 .use_dma_rx = 0, /* DBGU not capable of receive DMA */ 897 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), 898}; 899 900static u64 dbgu_dmamask = DMA_BIT_MASK(32); 901 902static struct platform_device at91rm9200_dbgu_device = { 903 .name = "atmel_usart", 904 .id = 0, 905 .dev = { 906 .dma_mask = &dbgu_dmamask, 907 .coherent_dma_mask = DMA_BIT_MASK(32), 908 .platform_data = &dbgu_data, 909 }, 910 .resource = dbgu_resources, 911 .num_resources = ARRAY_SIZE(dbgu_resources), 912}; 913 914static inline void configure_dbgu_pins(void) 915{ 916 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */ 917 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */ 918} 919 920static struct resource uart0_resources[] = { 921 [0] = { 922 .start = AT91RM9200_BASE_US0, 923 .end = AT91RM9200_BASE_US0 + SZ_16K - 1, 924 .flags = IORESOURCE_MEM, 925 }, 926 [1] = { 927 .start = AT91RM9200_ID_US0, 928 .end = AT91RM9200_ID_US0, 929 .flags = IORESOURCE_IRQ, 930 }, 931}; 932 933static struct atmel_uart_data uart0_data = { 934 .use_dma_tx = 1, 935 .use_dma_rx = 1, 936}; 937 938static u64 uart0_dmamask = DMA_BIT_MASK(32); 939 940static struct platform_device at91rm9200_uart0_device = { 941 .name = "atmel_usart", 942 .id = 1, 943 .dev = { 944 .dma_mask = &uart0_dmamask, 945 .coherent_dma_mask = DMA_BIT_MASK(32), 946 .platform_data = &uart0_data, 947 }, 948 .resource = uart0_resources, 949 .num_resources = ARRAY_SIZE(uart0_resources), 950}; 951 952static inline void configure_usart0_pins(unsigned pins) 953{ 954 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */ 955 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */ 956 957 if (pins & ATMEL_UART_CTS) 958 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */ 959 960 if (pins & ATMEL_UART_RTS) { 961 /* 962 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21. 963 * We need to drive the pin manually. Default is off (RTS is active low). 964 */ 965 at91_set_gpio_output(AT91_PIN_PA21, 1); 966 } 967} 968 969static struct resource uart1_resources[] = { 970 [0] = { 971 .start = AT91RM9200_BASE_US1, 972 .end = AT91RM9200_BASE_US1 + SZ_16K - 1, 973 .flags = IORESOURCE_MEM, 974 }, 975 [1] = { 976 .start = AT91RM9200_ID_US1, 977 .end = AT91RM9200_ID_US1, 978 .flags = IORESOURCE_IRQ, 979 }, 980}; 981 982static struct atmel_uart_data uart1_data = { 983 .use_dma_tx = 1, 984 .use_dma_rx = 1, 985}; 986 987static u64 uart1_dmamask = DMA_BIT_MASK(32); 988 989static struct platform_device at91rm9200_uart1_device = { 990 .name = "atmel_usart", 991 .id = 2, 992 .dev = { 993 .dma_mask = &uart1_dmamask, 994 .coherent_dma_mask = DMA_BIT_MASK(32), 995 .platform_data = &uart1_data, 996 }, 997 .resource = uart1_resources, 998 .num_resources = ARRAY_SIZE(uart1_resources), 999}; 1000 1001static inline void configure_usart1_pins(unsigned pins) 1002{ 1003 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */ 1004 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */ 1005 1006 if (pins & ATMEL_UART_RI) 1007 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */ 1008 if (pins & ATMEL_UART_DTR) 1009 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */ 1010 if (pins & ATMEL_UART_DCD) 1011 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */ 1012 if (pins & ATMEL_UART_CTS) 1013 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */ 1014 if (pins & ATMEL_UART_DSR) 1015 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */ 1016 if (pins & ATMEL_UART_RTS) 1017 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */ 1018} 1019 1020static struct resource uart2_resources[] = { 1021 [0] = { 1022 .start = AT91RM9200_BASE_US2, 1023 .end = AT91RM9200_BASE_US2 + SZ_16K - 1, 1024 .flags = IORESOURCE_MEM, 1025 }, 1026 [1] = { 1027 .start = AT91RM9200_ID_US2, 1028 .end = AT91RM9200_ID_US2, 1029 .flags = IORESOURCE_IRQ, 1030 }, 1031}; 1032 1033static struct atmel_uart_data uart2_data = { 1034 .use_dma_tx = 1, 1035 .use_dma_rx = 1, 1036}; 1037 1038static u64 uart2_dmamask = DMA_BIT_MASK(32); 1039 1040static struct platform_device at91rm9200_uart2_device = { 1041 .name = "atmel_usart", 1042 .id = 3, 1043 .dev = { 1044 .dma_mask = &uart2_dmamask, 1045 .coherent_dma_mask = DMA_BIT_MASK(32), 1046 .platform_data = &uart2_data, 1047 }, 1048 .resource = uart2_resources, 1049 .num_resources = ARRAY_SIZE(uart2_resources), 1050}; 1051 1052static inline void configure_usart2_pins(unsigned pins) 1053{ 1054 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */ 1055 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */ 1056 1057 if (pins & ATMEL_UART_CTS) 1058 at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */ 1059 if (pins & ATMEL_UART_RTS) 1060 at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */ 1061} 1062 1063static struct resource uart3_resources[] = { 1064 [0] = { 1065 .start = AT91RM9200_BASE_US3, 1066 .end = AT91RM9200_BASE_US3 + SZ_16K - 1, 1067 .flags = IORESOURCE_MEM, 1068 }, 1069 [1] = { 1070 .start = AT91RM9200_ID_US3, 1071 .end = AT91RM9200_ID_US3, 1072 .flags = IORESOURCE_IRQ, 1073 }, 1074}; 1075 1076static struct atmel_uart_data uart3_data = { 1077 .use_dma_tx = 1, 1078 .use_dma_rx = 1, 1079}; 1080 1081static u64 uart3_dmamask = DMA_BIT_MASK(32); 1082 1083static struct platform_device at91rm9200_uart3_device = { 1084 .name = "atmel_usart", 1085 .id = 4, 1086 .dev = { 1087 .dma_mask = &uart3_dmamask, 1088 .coherent_dma_mask = DMA_BIT_MASK(32), 1089 .platform_data = &uart3_data, 1090 }, 1091 .resource = uart3_resources, 1092 .num_resources = ARRAY_SIZE(uart3_resources), 1093}; 1094 1095static inline void configure_usart3_pins(unsigned pins) 1096{ 1097 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */ 1098 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */ 1099 1100 if (pins & ATMEL_UART_CTS) 1101 at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */ 1102 if (pins & ATMEL_UART_RTS) 1103 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */ 1104} 1105 1106static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1107struct platform_device *atmel_default_console_device; /* the serial console device */ 1108 1109void __init __deprecated at91_init_serial(struct at91_uart_config *config) 1110{ 1111 int i; 1112 1113 /* Fill in list of supported UARTs */ 1114 for (i = 0; i < config->nr_tty; i++) { 1115 switch (config->tty_map[i]) { 1116 case 0: 1117 configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS); 1118 at91_uarts[i] = &at91rm9200_uart0_device; 1119 at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart"); 1120 break; 1121 case 1: 1122 configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI); 1123 at91_uarts[i] = &at91rm9200_uart1_device; 1124 at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart"); 1125 break; 1126 case 2: 1127 configure_usart2_pins(0); 1128 at91_uarts[i] = &at91rm9200_uart2_device; 1129 at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart"); 1130 break; 1131 case 3: 1132 configure_usart3_pins(0); 1133 at91_uarts[i] = &at91rm9200_uart3_device; 1134 at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart"); 1135 break; 1136 case 4: 1137 configure_dbgu_pins(); 1138 at91_uarts[i] = &at91rm9200_dbgu_device; 1139 at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart"); 1140 break; 1141 default: 1142 continue; 1143 } 1144 at91_uarts[i]->id = i; /* update ID number to mapped ID */ 1145 } 1146 1147 /* Set serial console device */ 1148 if (config->console_tty < ATMEL_MAX_UART) 1149 atmel_default_console_device = at91_uarts[config->console_tty]; 1150 if (!atmel_default_console_device) 1151 printk(KERN_INFO "AT91: No default serial console defined.\n"); 1152} 1153 1154void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1155{ 1156 struct platform_device *pdev; 1157 1158 switch (id) { 1159 case 0: /* DBGU */ 1160 pdev = &at91rm9200_dbgu_device; 1161 configure_dbgu_pins(); 1162 at91_clock_associate("mck", &pdev->dev, "usart"); 1163 break; 1164 case AT91RM9200_ID_US0: 1165 pdev = &at91rm9200_uart0_device; 1166 configure_usart0_pins(pins); 1167 at91_clock_associate("usart0_clk", &pdev->dev, "usart"); 1168 break; 1169 case AT91RM9200_ID_US1: 1170 pdev = &at91rm9200_uart1_device; 1171 configure_usart1_pins(pins); 1172 at91_clock_associate("usart1_clk", &pdev->dev, "usart"); 1173 break; 1174 case AT91RM9200_ID_US2: 1175 pdev = &at91rm9200_uart2_device; 1176 configure_usart2_pins(pins); 1177 at91_clock_associate("usart2_clk", &pdev->dev, "usart"); 1178 break; 1179 case AT91RM9200_ID_US3: 1180 pdev = &at91rm9200_uart3_device; 1181 configure_usart3_pins(pins); 1182 at91_clock_associate("usart3_clk", &pdev->dev, "usart"); 1183 break; 1184 default: 1185 return; 1186 } 1187 pdev->id = portnr; /* update to mapped ID */ 1188 1189 if (portnr < ATMEL_MAX_UART) 1190 at91_uarts[portnr] = pdev; 1191} 1192 1193void __init at91_set_serial_console(unsigned portnr) 1194{ 1195 if (portnr < ATMEL_MAX_UART) 1196 atmel_default_console_device = at91_uarts[portnr]; 1197} 1198 1199void __init at91_add_device_serial(void) 1200{ 1201 int i; 1202 1203 for (i = 0; i < ATMEL_MAX_UART; i++) { 1204 if (at91_uarts[i]) 1205 platform_device_register(at91_uarts[i]); 1206 } 1207 1208 if (!atmel_default_console_device) 1209 printk(KERN_INFO "AT91: No default serial console defined.\n"); 1210} 1211#else 1212void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} 1213void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} 1214void __init at91_set_serial_console(unsigned portnr) {} 1215void __init at91_add_device_serial(void) {} 1216#endif 1217 1218 1219/* -------------------------------------------------------------------- */ 1220 1221/* 1222 * These devices are always present and don't need any board-specific 1223 * setup. 1224 */ 1225static int __init at91_add_standard_devices(void) 1226{ 1227 at91_add_device_rtc(); 1228 at91_add_device_watchdog(); 1229 at91_add_device_tc(); 1230 return 0; 1231} 1232 1233arch_initcall(at91_add_standard_devices); 1234