1/* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */ 2/* 3 * linux/arch/arm/kernel/bios32.c 4 * 5 * PCI bios-type initialisation for PCI machines 6 * 7 * Bits taken from various places. 8 */ 9#include <linux/module.h> 10#include <linux/kernel.h> 11#include <linux/pci.h> 12#include <linux/slab.h> 13#include <linux/init.h> 14#include <linux/io.h> 15 16#include <asm/mach-types.h> 17#include <asm/mach/pci.h> 18 19static int debug_pci; 20static int use_firmware; 21 22/* 23 * We can't use pci_find_device() here since we are 24 * called from interrupt context. 25 */ 26static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn) 27{ 28 struct pci_dev *dev; 29 30 list_for_each_entry(dev, &bus->devices, bus_list) { 31 u16 status; 32 33 /* 34 * ignore host bridge - we handle 35 * that separately 36 */ 37 if (dev->bus->number == 0 && dev->devfn == 0) 38 continue; 39 40 pci_read_config_word(dev, PCI_STATUS, &status); 41 if (status == 0xffff) 42 continue; 43 44 if ((status & status_mask) == 0) 45 continue; 46 47 /* clear the status errors */ 48 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 49 50 if (warn) 51 printk("(%s: %04X) ", pci_name(dev), status); 52 } 53 54 list_for_each_entry(dev, &bus->devices, bus_list) 55 if (dev->subordinate) 56 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 57} 58 59void pcibios_report_status(u_int status_mask, int warn) 60{ 61 struct list_head *l; 62 63 list_for_each(l, &pci_root_buses) { 64 struct pci_bus *bus = pci_bus_b(l); 65 66 pcibios_bus_report_status(bus, status_mask, warn); 67 } 68} 69 70/* 71 * We don't use this to fix the device, but initialisation of it. 72 * It's not the correct use for this, but it works. 73 * Note that the arbiter/ISA bridge appears to be buggy, specifically in 74 * the following area: 75 * 1. park on CPU 76 * 2. ISA bridge ping-pong 77 * 3. ISA bridge master handling of target RETRY 78 * 79 * Bug 3 is responsible for the sound DMA grinding to a halt. We now 80 * live with bug 2. 81 */ 82static void __devinit pci_fixup_83c553(struct pci_dev *dev) 83{ 84 /* 85 * Set memory region to start at address 0, and enable IO 86 */ 87 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY); 88 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO); 89 90 dev->resource[0].end -= dev->resource[0].start; 91 dev->resource[0].start = 0; 92 93 /* 94 * All memory requests from ISA to be channelled to PCI 95 */ 96 pci_write_config_byte(dev, 0x48, 0xff); 97 98 /* 99 * Enable ping-pong on bus master to ISA bridge transactions. 100 * This improves the sound DMA substantially. The fixed 101 * priority arbiter also helps (see below). 102 */ 103 pci_write_config_byte(dev, 0x42, 0x01); 104 105 /* 106 * Enable PCI retry 107 */ 108 pci_write_config_byte(dev, 0x40, 0x22); 109 110 /* 111 * We used to set the arbiter to "park on last master" (bit 112 * 1 set), but unfortunately the CyberPro does not park the 113 * bus. We must therefore park on CPU. Unfortunately, this 114 * may trigger yet another bug in the 553. 115 */ 116 pci_write_config_byte(dev, 0x83, 0x02); 117 118 /* 119 * Make the ISA DMA request lowest priority, and disable 120 * rotating priorities completely. 121 */ 122 pci_write_config_byte(dev, 0x80, 0x11); 123 pci_write_config_byte(dev, 0x81, 0x00); 124 125 /* 126 * Route INTA input to IRQ 11, and set IRQ11 to be level 127 * sensitive. 128 */ 129 pci_write_config_word(dev, 0x44, 0xb000); 130 outb(0x08, 0x4d1); 131} 132DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553); 133 134static void __devinit pci_fixup_unassign(struct pci_dev *dev) 135{ 136 dev->resource[0].end -= dev->resource[0].start; 137 dev->resource[0].start = 0; 138} 139DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign); 140 141/* 142 * Prevent the PCI layer from seeing the resources allocated to this device 143 * if it is the host bridge by marking it as such. These resources are of 144 * no consequence to the PCI layer (they are handled elsewhere). 145 */ 146static void __devinit pci_fixup_dec21285(struct pci_dev *dev) 147{ 148 int i; 149 150 if (dev->devfn == 0) { 151 dev->class &= 0xff; 152 dev->class |= PCI_CLASS_BRIDGE_HOST << 8; 153 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 154 dev->resource[i].start = 0; 155 dev->resource[i].end = 0; 156 dev->resource[i].flags = 0; 157 } 158 } 159} 160DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); 161 162/* 163 * Same as above. The PrPMC800 carrier board for the PrPMC1100 164 * card maps the host-bridge @ 00:01:00 for some reason and it 165 * ends up getting scanned. Note that we only want to do this 166 * fixup when we find the IXP4xx on a PrPMC system, which is why 167 * we check the machine type. We could be running on a board 168 * with an IXP4xx target device and we don't want to kill the 169 * resources in that case. 170 */ 171static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev) 172{ 173 int i; 174 175 if (machine_is_prpmc1100()) { 176 dev->class &= 0xff; 177 dev->class |= PCI_CLASS_BRIDGE_HOST << 8; 178 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 179 dev->resource[i].start = 0; 180 dev->resource[i].end = 0; 181 dev->resource[i].flags = 0; 182 } 183 } 184} 185DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100); 186 187/* 188 * PCI IDE controllers use non-standard I/O port decoding, respect it. 189 */ 190static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) 191{ 192 struct resource *r; 193 int i; 194 195 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 196 return; 197 198 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 199 r = dev->resource + i; 200 if ((r->start & ~0x80) == 0x374) { 201 r->start |= 2; 202 r->end = r->start; 203 } 204 } 205} 206DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); 207 208/* 209 * Put the DEC21142 to sleep 210 */ 211static void __devinit pci_fixup_dec21142(struct pci_dev *dev) 212{ 213 pci_write_config_dword(dev, 0x40, 0x80000000); 214} 215DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142); 216 217/* 218 * The CY82C693 needs some rather major fixups to ensure that it does 219 * the right thing. Idea from the Alpha people, with a few additions. 220 * 221 * We ensure that the IDE base registers are set to 1f0/3f4 for the 222 * primary bus, and 170/374 for the secondary bus. Also, hide them 223 * from the PCI subsystem view as well so we won't try to perform 224 * our own auto-configuration on them. 225 * 226 * In addition, we ensure that the PCI IDE interrupts are routed to 227 * IRQ 14 and IRQ 15 respectively. 228 * 229 * The above gets us to a point where the IDE on this device is 230 * functional. However, The CY82C693U _does not work_ in bus 231 * master mode without locking the PCI bus solid. 232 */ 233static void __devinit pci_fixup_cy82c693(struct pci_dev *dev) 234{ 235 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { 236 u32 base0, base1; 237 238 if (dev->class & 0x80) { /* primary */ 239 base0 = 0x1f0; 240 base1 = 0x3f4; 241 } else { /* secondary */ 242 base0 = 0x170; 243 base1 = 0x374; 244 } 245 246 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 247 base0 | PCI_BASE_ADDRESS_SPACE_IO); 248 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 249 base1 | PCI_BASE_ADDRESS_SPACE_IO); 250 251 dev->resource[0].start = 0; 252 dev->resource[0].end = 0; 253 dev->resource[0].flags = 0; 254 255 dev->resource[1].start = 0; 256 dev->resource[1].end = 0; 257 dev->resource[1].flags = 0; 258 } else if (PCI_FUNC(dev->devfn) == 0) { 259 /* 260 * Setup IDE IRQ routing. 261 */ 262 pci_write_config_byte(dev, 0x4b, 14); 263 pci_write_config_byte(dev, 0x4c, 15); 264 265 /* 266 * Disable FREQACK handshake, enable USB. 267 */ 268 pci_write_config_byte(dev, 0x4d, 0x41); 269 270 /* 271 * Enable PCI retry, and PCI post-write buffer. 272 */ 273 pci_write_config_byte(dev, 0x44, 0x17); 274 275 /* 276 * Enable ISA master and DMA post write buffering. 277 */ 278 pci_write_config_byte(dev, 0x45, 0x03); 279 } 280} 281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); 282 283static void __init pci_fixup_it8152(struct pci_dev *dev) 284{ 285 int i; 286 /* fixup for ITE 8152 devices */ 287 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST || 288 dev->class == 0x68000 || 289 dev->class == 0x80103) { 290 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 291 dev->resource[i].start = 0; 292 dev->resource[i].end = 0; 293 dev->resource[i].flags = 0; 294 } 295 } 296} 297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); 298 299 300 301void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) 302{ 303 if (debug_pci) 304 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev)); 305 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 306} 307 308/* 309 * If the bus contains any of these devices, then we must not turn on 310 * parity checking of any kind. Currently this is CyberPro 20x0 only. 311 */ 312static inline int pdev_bad_for_parity(struct pci_dev *dev) 313{ 314 return ((dev->vendor == PCI_VENDOR_ID_INTERG && 315 (dev->device == PCI_DEVICE_ID_INTERG_2000 || 316 dev->device == PCI_DEVICE_ID_INTERG_2010)) || 317 (dev->vendor == PCI_VENDOR_ID_ITE && 318 dev->device == PCI_DEVICE_ID_ITE_8152)); 319 320} 321 322/* 323 * Adjust the device resources from bus-centric to Linux-centric. 324 */ 325static void __devinit 326pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev) 327{ 328 resource_size_t offset; 329 int i; 330 331 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 332 if (dev->resource[i].start == 0) 333 continue; 334 if (dev->resource[i].flags & IORESOURCE_MEM) 335 offset = root->mem_offset; 336 else 337 offset = root->io_offset; 338 339 dev->resource[i].start += offset; 340 dev->resource[i].end += offset; 341 } 342} 343 344static void __devinit 345pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root) 346{ 347 struct pci_dev *dev = bus->self; 348 int i; 349 350 if (!dev) { 351 /* 352 * Assign root bus resources. 353 */ 354 for (i = 0; i < 3; i++) 355 bus->resource[i] = root->resource[i]; 356 } 357} 358 359extern bool plat_fixup_bus(struct pci_bus *b); 360 361/* 362 * pcibios_fixup_bus - Called after each bus is probed, 363 * but before its children are examined. 364 */ 365void pcibios_fixup_bus(struct pci_bus *bus) 366{ 367 struct pci_sys_data *root = bus->sysdata; 368 struct pci_dev *dev; 369 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; 370 371 if (plat_fixup_bus(bus)) 372 return; 373 374 pbus_assign_bus_resources(bus, root); 375 376 /* 377 * Walk the devices on this bus, working out what we can 378 * and can't support. 379 */ 380 list_for_each_entry(dev, &bus->devices, bus_list) { 381 u16 status; 382 383 pdev_fixup_device_resources(root, dev); 384 385 pci_read_config_word(dev, PCI_STATUS, &status); 386 387 /* 388 * If any device on this bus does not support fast back 389 * to back transfers, then the bus as a whole is not able 390 * to support them. Having fast back to back transfers 391 * on saves us one PCI cycle per transaction. 392 */ 393 if (!(status & PCI_STATUS_FAST_BACK)) 394 features &= ~PCI_COMMAND_FAST_BACK; 395 396 if (pdev_bad_for_parity(dev)) 397 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 398 399 switch (dev->class >> 8) { 400 case PCI_CLASS_BRIDGE_PCI: 401 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); 402 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT; 403 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK); 404 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); 405 break; 406 407 case PCI_CLASS_BRIDGE_CARDBUS: 408 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status); 409 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT; 410 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status); 411 break; 412 } 413 } 414 415 /* 416 * Now walk the devices again, this time setting them up. 417 */ 418 list_for_each_entry(dev, &bus->devices, bus_list) { 419 u16 cmd; 420 421 pci_read_config_word(dev, PCI_COMMAND, &cmd); 422 cmd |= features; 423 pci_write_config_word(dev, PCI_COMMAND, cmd); 424 425 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 426 L1_CACHE_BYTES >> 2); 427 } 428 429 /* 430 * Propagate the flags to the PCI bridge. 431 */ 432 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 433 if (features & PCI_COMMAND_FAST_BACK) 434 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; 435 if (features & PCI_COMMAND_PARITY) 436 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; 437 } 438 439 /* 440 * Report what we did for this bus 441 */ 442 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n", 443 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); 444} 445 446/* 447 * Convert from Linux-centric to bus-centric addresses for bridge devices. 448 */ 449void 450pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 451 struct resource *res) 452{ 453 struct pci_sys_data *root = dev->sysdata; 454 unsigned long offset = 0; 455 456 if (res->flags & IORESOURCE_IO) 457 offset = root->io_offset; 458 if (res->flags & IORESOURCE_MEM) 459 offset = root->mem_offset; 460 461 region->start = res->start - offset; 462 region->end = res->end - offset; 463} 464 465void __devinit 466pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 467 struct pci_bus_region *region) 468{ 469 struct pci_sys_data *root = dev->sysdata; 470 unsigned long offset = 0; 471 472 if (res->flags & IORESOURCE_IO) 473 offset = root->io_offset; 474 if (res->flags & IORESOURCE_MEM) 475 offset = root->mem_offset; 476 477 res->start = region->start + offset; 478 res->end = region->end + offset; 479} 480 481#ifdef CONFIG_HOTPLUG 482EXPORT_SYMBOL(pcibios_fixup_bus); 483EXPORT_SYMBOL(pcibios_resource_to_bus); 484EXPORT_SYMBOL(pcibios_bus_to_resource); 485#endif 486 487/* 488 * Swizzle the device pin each time we cross a bridge. 489 * This might update pin and returns the slot number. 490 */ 491static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin) 492{ 493 struct pci_sys_data *sys = dev->sysdata; 494 int slot = 0, oldpin = *pin; 495 496 if (sys->swizzle) 497 slot = sys->swizzle(dev, pin); 498 499 if (debug_pci) 500 printk("PCI: %s swizzling pin %d => pin %d slot %d\n", 501 pci_name(dev), oldpin, *pin, slot); 502 503 return slot; 504} 505 506/* 507 * Map a slot/pin to an IRQ. 508 */ 509static int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 510{ 511 struct pci_sys_data *sys = dev->sysdata; 512 int irq = -1; 513 514 if (sys->map_irq) 515 irq = sys->map_irq(dev, slot, pin); 516 517 if (debug_pci) 518 printk("PCI: %s mapping slot %d pin %d => irq %d\n", 519 pci_name(dev), slot, pin, irq); 520 521 return irq; 522} 523 524static void __init pcibios_init_hw(struct hw_pci *hw) 525{ 526 struct pci_sys_data *sys = NULL; 527 int ret; 528 int nr, busnr; 529 530 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { 531 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL); 532 if (!sys) 533 panic("PCI: unable to allocate sys data!"); 534 535#ifdef CONFIG_PCI_DOMAINS 536 sys->domain = hw->domain; 537#endif 538 sys->hw = hw; 539 sys->busnr = busnr; 540 sys->swizzle = hw->swizzle; 541 sys->map_irq = hw->map_irq; 542 sys->resource[0] = &ioport_resource; 543 sys->resource[1] = &iomem_resource; 544 545 ret = hw->setup(nr, sys); 546 547 if (ret > 0) { 548 sys->bus = hw->scan(nr, sys); 549 550 if (!sys->bus) 551 panic("PCI: unable to scan bus!"); 552 553 busnr = sys->bus->subordinate + 1; 554 555 list_add(&sys->node, &hw->buses); 556 } else { 557 kfree(sys); 558 if (ret < 0) 559 break; 560 } 561 } 562} 563 564void __init pci_common_init(struct hw_pci *hw) 565{ 566 struct pci_sys_data *sys; 567 568 INIT_LIST_HEAD(&hw->buses); 569 570 if (hw->preinit) 571 hw->preinit(); 572 pcibios_init_hw(hw); 573 if (hw->postinit) 574 hw->postinit(); 575 576 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); 577 578 list_for_each_entry(sys, &hw->buses, node) { 579 struct pci_bus *bus = sys->bus; 580 581 if (!use_firmware) { 582 /* 583 * Size the bridge windows. 584 */ 585 pci_bus_size_bridges(bus); 586 587 /* 588 * Assign resources. 589 */ 590 pci_bus_assign_resources(bus); 591 } 592 593 /* 594 * Tell drivers about devices found. 595 */ 596 pci_bus_add_devices(bus); 597 } 598} 599 600char * __init pcibios_setup(char *str) 601{ 602 if (!strcmp(str, "debug")) { 603 debug_pci = 1; 604 return NULL; 605 } else if (!strcmp(str, "firmware")) { 606 use_firmware = 1; 607 return NULL; 608 } 609 return str; 610} 611 612/* 613 * From arch/i386/kernel/pci-i386.c: 614 * 615 * We need to avoid collisions with `mirrored' VGA ports 616 * and other strange ISA hardware, so we always want the 617 * addresses to be allocated in the 0x000-0x0ff region 618 * modulo 0x400. 619 * 620 * Why? Because some silly external IO cards only decode 621 * the low 10 bits of the IO address. The 0x00-0xff region 622 * is reserved for motherboard devices that decode all 16 623 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 624 * but we want to try to avoid allocating at 0x2900-0x2bff 625 * which might be mirrored at 0x0100-0x03ff.. 626 */ 627resource_size_t pcibios_align_resource(void *data, const struct resource *res, 628 resource_size_t size, resource_size_t align) 629{ 630 resource_size_t start = res->start; 631 632 if (res->flags & IORESOURCE_IO && start & 0x300) 633 start = (start + 0x3ff) & ~0x3ff; 634 635 start = (start + align - 1) & ~(align - 1); 636 637 return start; 638} 639int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 640 enum pci_mmap_state mmap_state, int write_combine) 641{ 642 struct pci_sys_data *root = dev->sysdata; 643 unsigned long phys; 644 645 if (mmap_state == pci_mmap_io) { 646 return -EINVAL; 647 } else { 648 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT); 649 } 650 651 /* 652 * Mark this as IO 653 */ 654 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 655 656 if (remap_pfn_range(vma, vma->vm_start, phys, 657 vma->vm_end - vma->vm_start, 658 vma->vm_page_prot)) 659 return -EAGAIN; 660 661 return 0; 662} 663