1/* 2 * linux/arch/alpha/kernel/core_titan.c 3 * 4 * Code common to all TITAN core logic chips. 5 */ 6 7#define __EXTERN_INLINE inline 8#include <asm/io.h> 9#include <asm/core_titan.h> 10#undef __EXTERN_INLINE 11 12#include <linux/module.h> 13#include <linux/types.h> 14#include <linux/pci.h> 15#include <linux/sched.h> 16#include <linux/init.h> 17#include <linux/vmalloc.h> 18#include <linux/bootmem.h> 19 20#include <asm/ptrace.h> 21#include <asm/smp.h> 22#include <asm/pgalloc.h> 23#include <asm/tlbflush.h> 24#include <asm/vga.h> 25 26#include "proto.h" 27#include "pci_impl.h" 28 29/* Save Titan configuration data as the console had it set up. */ 30 31struct 32{ 33 unsigned long wsba[4]; 34 unsigned long wsm[4]; 35 unsigned long tba[4]; 36} saved_config[4] __attribute__((common)); 37 38/* 39 * Is PChip 1 present? No need to query it more than once. 40 */ 41static int titan_pchip1_present; 42 43/* 44 * BIOS32-style PCI interface: 45 */ 46 47#define DEBUG_CONFIG 0 48 49#if DEBUG_CONFIG 50# define DBG_CFG(args) printk args 51#else 52# define DBG_CFG(args) 53#endif 54 55 56/* 57 * Routines to access TIG registers. 58 */ 59static inline volatile unsigned long * 60mk_tig_addr(int offset) 61{ 62 return (volatile unsigned long *)(TITAN_TIG_SPACE + (offset << 6)); 63} 64 65static inline u8 66titan_read_tig(int offset, u8 value) 67{ 68 volatile unsigned long *tig_addr = mk_tig_addr(offset); 69 return (u8)(*tig_addr & 0xff); 70} 71 72static inline void 73titan_write_tig(int offset, u8 value) 74{ 75 volatile unsigned long *tig_addr = mk_tig_addr(offset); 76 *tig_addr = (unsigned long)value; 77} 78 79 80/* 81 * Given a bus, device, and function number, compute resulting 82 * configuration space address 83 * accordingly. It is therefore not safe to have concurrent 84 * invocations to configuration space access routines, but there 85 * really shouldn't be any need for this. 86 * 87 * Note that all config space accesses use Type 1 address format. 88 * 89 * Note also that type 1 is determined by non-zero bus number. 90 * 91 * Type 1: 92 * 93 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 94 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 95 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 96 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| 97 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 98 * 99 * 31:24 reserved 100 * 23:16 bus number (8 bits = 128 possible buses) 101 * 15:11 Device number (5 bits) 102 * 10:8 function number 103 * 7:2 register number 104 * 105 * Notes: 106 * The function number selects which function of a multi-function device 107 * (e.g., SCSI and Ethernet). 108 * 109 * The register selects a DWORD (32 bit) register offset. Hence it 110 * doesn't get shifted by 2 bits as we want to "drop" the bottom two 111 * bits. 112 */ 113 114static int 115mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, 116 unsigned long *pci_addr, unsigned char *type1) 117{ 118 struct pci_controller *hose = pbus->sysdata; 119 unsigned long addr; 120 u8 bus = pbus->number; 121 122 DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, " 123 "pci_addr=0x%p, type1=0x%p)\n", 124 bus, device_fn, where, pci_addr, type1)); 125 126 if (!pbus->parent) /* No parent means peer PCI bus. */ 127 bus = 0; 128 *type1 = (bus != 0); 129 130 addr = (bus << 16) | (device_fn << 8) | where; 131 addr |= hose->config_space_base; 132 133 *pci_addr = addr; 134 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); 135 return 0; 136} 137 138static int 139titan_read_config(struct pci_bus *bus, unsigned int devfn, int where, 140 int size, u32 *value) 141{ 142 unsigned long addr; 143 unsigned char type1; 144 145 if (mk_conf_addr(bus, devfn, where, &addr, &type1)) 146 return PCIBIOS_DEVICE_NOT_FOUND; 147 148 switch (size) { 149 case 1: 150 *value = __kernel_ldbu(*(vucp)addr); 151 break; 152 case 2: 153 *value = __kernel_ldwu(*(vusp)addr); 154 break; 155 case 4: 156 *value = *(vuip)addr; 157 break; 158 } 159 160 return PCIBIOS_SUCCESSFUL; 161} 162 163static int 164titan_write_config(struct pci_bus *bus, unsigned int devfn, int where, 165 int size, u32 value) 166{ 167 unsigned long addr; 168 unsigned char type1; 169 170 if (mk_conf_addr(bus, devfn, where, &addr, &type1)) 171 return PCIBIOS_DEVICE_NOT_FOUND; 172 173 switch (size) { 174 case 1: 175 __kernel_stb(value, *(vucp)addr); 176 mb(); 177 __kernel_ldbu(*(vucp)addr); 178 break; 179 case 2: 180 __kernel_stw(value, *(vusp)addr); 181 mb(); 182 __kernel_ldwu(*(vusp)addr); 183 break; 184 case 4: 185 *(vuip)addr = value; 186 mb(); 187 *(vuip)addr; 188 break; 189 } 190 191 return PCIBIOS_SUCCESSFUL; 192} 193 194struct pci_ops titan_pci_ops = 195{ 196 .read = titan_read_config, 197 .write = titan_write_config, 198}; 199 200 201void 202titan_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) 203{ 204 titan_pachip *pachip = 205 (hose->index & 1) ? TITAN_pachip1 : TITAN_pachip0; 206 titan_pachip_port *port; 207 volatile unsigned long *csr; 208 unsigned long value; 209 210 /* Get the right hose. */ 211 port = &pachip->g_port; 212 if (hose->index & 2) 213 port = &pachip->a_port; 214 215 /* We can invalidate up to 8 tlb entries in a go. The flush 216 matches against <31:16> in the pci address. 217 Note that gtlbi* and atlbi* are in the same place in the g_port 218 and a_port, respectively, so the g_port offset can be used 219 even if hose is an a_port */ 220 csr = &port->port_specific.g.gtlbia.csr; 221 if (((start ^ end) & 0xffff0000) == 0) 222 csr = &port->port_specific.g.gtlbiv.csr; 223 224 /* For TBIA, it doesn't matter what value we write. For TBI, 225 it's the shifted tag bits. */ 226 value = (start & 0xffff0000) >> 12; 227 228 wmb(); 229 *csr = value; 230 mb(); 231 *csr; 232} 233 234static int 235titan_query_agp(titan_pachip_port *port) 236{ 237 union TPAchipPCTL pctl; 238 239 /* set up APCTL */ 240 pctl.pctl_q_whole = port->pctl.csr; 241 242 return pctl.pctl_r_bits.apctl_v_agp_present; 243 244} 245 246static void __init 247titan_init_one_pachip_port(titan_pachip_port *port, int index) 248{ 249 struct pci_controller *hose; 250 251 hose = alloc_pci_controller(); 252 if (index == 0) 253 pci_isa_hose = hose; 254 hose->io_space = alloc_resource(); 255 hose->mem_space = alloc_resource(); 256 257 /* 258 * This is for userland consumption. The 40-bit PIO bias that we 259 * use in the kernel through KSEG doesn't work in the page table 260 * based user mappings. (43-bit KSEG sign extends the physical 261 * address from bit 40 to hit the I/O bit - mapped addresses don't). 262 * So make sure we get the 43-bit PIO bias. 263 */ 264 hose->sparse_mem_base = 0; 265 hose->sparse_io_base = 0; 266 hose->dense_mem_base 267 = (TITAN_MEM(index) & 0xffffffffffUL) | 0x80000000000UL; 268 hose->dense_io_base 269 = (TITAN_IO(index) & 0xffffffffffUL) | 0x80000000000UL; 270 271 hose->config_space_base = TITAN_CONF(index); 272 hose->index = index; 273 274 hose->io_space->start = TITAN_IO(index) - TITAN_IO_BIAS; 275 hose->io_space->end = hose->io_space->start + TITAN_IO_SPACE - 1; 276 hose->io_space->name = pci_io_names[index]; 277 hose->io_space->flags = IORESOURCE_IO; 278 279 hose->mem_space->start = TITAN_MEM(index) - TITAN_MEM_BIAS; 280 hose->mem_space->end = hose->mem_space->start + 0xffffffff; 281 hose->mem_space->name = pci_mem_names[index]; 282 hose->mem_space->flags = IORESOURCE_MEM; 283 284 if (request_resource(&ioport_resource, hose->io_space) < 0) 285 printk(KERN_ERR "Failed to request IO on hose %d\n", index); 286 if (request_resource(&iomem_resource, hose->mem_space) < 0) 287 printk(KERN_ERR "Failed to request MEM on hose %d\n", index); 288 289 /* 290 * Save the existing PCI window translations. SRM will 291 * need them when we go to reboot. 292 */ 293 saved_config[index].wsba[0] = port->wsba[0].csr; 294 saved_config[index].wsm[0] = port->wsm[0].csr; 295 saved_config[index].tba[0] = port->tba[0].csr; 296 297 saved_config[index].wsba[1] = port->wsba[1].csr; 298 saved_config[index].wsm[1] = port->wsm[1].csr; 299 saved_config[index].tba[1] = port->tba[1].csr; 300 301 saved_config[index].wsba[2] = port->wsba[2].csr; 302 saved_config[index].wsm[2] = port->wsm[2].csr; 303 saved_config[index].tba[2] = port->tba[2].csr; 304 305 saved_config[index].wsba[3] = port->wsba[3].csr; 306 saved_config[index].wsm[3] = port->wsm[3].csr; 307 saved_config[index].tba[3] = port->tba[3].csr; 308 309 /* 310 * Set up the PCI to main memory translation windows. 311 * 312 * Note: Window 3 on Titan is Scatter-Gather ONLY. 313 * 314 * Window 0 is scatter-gather 8MB at 8MB (for isa) 315 * Window 1 is direct access 1GB at 2GB 316 * Window 2 is scatter-gather 1GB at 3GB 317 */ 318 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0); 319 hose->sg_isa->align_entry = 8; /* 64KB for ISA */ 320 321 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, 0); 322 hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */ 323 324 port->wsba[0].csr = hose->sg_isa->dma_base | 3; 325 port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000; 326 port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes); 327 328 port->wsba[1].csr = __direct_map_base | 1; 329 port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000; 330 port->tba[1].csr = 0; 331 332 port->wsba[2].csr = hose->sg_pci->dma_base | 3; 333 port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000; 334 port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes); 335 336 port->wsba[3].csr = 0; 337 338 /* Enable the Monster Window to make DAC pci64 possible. */ 339 port->pctl.csr |= pctl_m_mwin; 340 341 /* 342 * If it's an AGP port, initialize agplastwr. 343 */ 344 if (titan_query_agp(port)) 345 port->port_specific.a.agplastwr.csr = __direct_map_base; 346 347 titan_pci_tbi(hose, 0, -1); 348} 349 350static void __init 351titan_init_pachips(titan_pachip *pachip0, titan_pachip *pachip1) 352{ 353 titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14; 354 355 /* Init the ports in hose order... */ 356 titan_init_one_pachip_port(&pachip0->g_port, 0); /* hose 0 */ 357 if (titan_pchip1_present) 358 titan_init_one_pachip_port(&pachip1->g_port, 1);/* hose 1 */ 359 titan_init_one_pachip_port(&pachip0->a_port, 2); /* hose 2 */ 360 if (titan_pchip1_present) 361 titan_init_one_pachip_port(&pachip1->a_port, 3);/* hose 3 */ 362} 363 364void __init 365titan_init_arch(void) 366{ 367 368 boot_cpuid = __hard_smp_processor_id(); 369 370 /* With multiple PCI busses, we play with I/O as physical addrs. */ 371 ioport_resource.end = ~0UL; 372 iomem_resource.end = ~0UL; 373 374 /* PCI DMA Direct Mapping is 1GB at 2GB. */ 375 __direct_map_base = 0x80000000; 376 __direct_map_size = 0x40000000; 377 378 /* Init the PA chip(s). */ 379 titan_init_pachips(TITAN_pachip0, TITAN_pachip1); 380 381 /* Check for graphic console location (if any). */ 382 find_console_vga_hose(); 383} 384 385static void 386titan_kill_one_pachip_port(titan_pachip_port *port, int index) 387{ 388 port->wsba[0].csr = saved_config[index].wsba[0]; 389 port->wsm[0].csr = saved_config[index].wsm[0]; 390 port->tba[0].csr = saved_config[index].tba[0]; 391 392 port->wsba[1].csr = saved_config[index].wsba[1]; 393 port->wsm[1].csr = saved_config[index].wsm[1]; 394 port->tba[1].csr = saved_config[index].tba[1]; 395 396 port->wsba[2].csr = saved_config[index].wsba[2]; 397 port->wsm[2].csr = saved_config[index].wsm[2]; 398 port->tba[2].csr = saved_config[index].tba[2]; 399 400 port->wsba[3].csr = saved_config[index].wsba[3]; 401 port->wsm[3].csr = saved_config[index].wsm[3]; 402 port->tba[3].csr = saved_config[index].tba[3]; 403} 404 405static void 406titan_kill_pachips(titan_pachip *pachip0, titan_pachip *pachip1) 407{ 408 if (titan_pchip1_present) { 409 titan_kill_one_pachip_port(&pachip1->g_port, 1); 410 titan_kill_one_pachip_port(&pachip1->a_port, 3); 411 } 412 titan_kill_one_pachip_port(&pachip0->g_port, 0); 413 titan_kill_one_pachip_port(&pachip0->a_port, 2); 414} 415 416void 417titan_kill_arch(int mode) 418{ 419 titan_kill_pachips(TITAN_pachip0, TITAN_pachip1); 420} 421 422 423/* 424 * IO map support. 425 */ 426 427void __iomem * 428titan_ioportmap(unsigned long addr) 429{ 430 FIXUP_IOADDR_VGA(addr); 431 return (void __iomem *)(addr + TITAN_IO_BIAS); 432} 433 434 435void __iomem * 436titan_ioremap(unsigned long addr, unsigned long size) 437{ 438 int h = (addr & TITAN_HOSE_MASK) >> TITAN_HOSE_SHIFT; 439 unsigned long baddr = addr & ~TITAN_HOSE_MASK; 440 unsigned long last = baddr + size - 1; 441 struct pci_controller *hose; 442 struct vm_struct *area; 443 unsigned long vaddr; 444 unsigned long *ptes; 445 unsigned long pfn; 446 447 /* 448 * Adjust the address and hose, if necessary. 449 */ 450 if (pci_vga_hose && __is_mem_vga(addr)) { 451 h = pci_vga_hose->index; 452 addr += pci_vga_hose->mem_space->start; 453 } 454 455 /* 456 * Find the hose. 457 */ 458 for (hose = hose_head; hose; hose = hose->next) 459 if (hose->index == h) 460 break; 461 if (!hose) 462 return NULL; 463 464 /* 465 * Is it direct-mapped? 466 */ 467 if ((baddr >= __direct_map_base) && 468 ((baddr + size - 1) < __direct_map_base + __direct_map_size)) { 469 vaddr = addr - __direct_map_base + TITAN_MEM_BIAS; 470 return (void __iomem *) vaddr; 471 } 472 473 /* 474 * Check the scatter-gather arena. 475 */ 476 if (hose->sg_pci && 477 baddr >= (unsigned long)hose->sg_pci->dma_base && 478 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size){ 479 480 /* 481 * Adjust the limits (mappings must be page aligned) 482 */ 483 baddr -= hose->sg_pci->dma_base; 484 last -= hose->sg_pci->dma_base; 485 baddr &= PAGE_MASK; 486 size = PAGE_ALIGN(last) - baddr; 487 488 /* 489 * Map it 490 */ 491 area = get_vm_area(size, VM_IOREMAP); 492 if (!area) { 493 printk("ioremap failed... no vm_area...\n"); 494 return NULL; 495 } 496 497 ptes = hose->sg_pci->ptes; 498 for (vaddr = (unsigned long)area->addr; 499 baddr <= last; 500 baddr += PAGE_SIZE, vaddr += PAGE_SIZE) { 501 pfn = ptes[baddr >> PAGE_SHIFT]; 502 if (!(pfn & 1)) { 503 printk("ioremap failed... pte not valid...\n"); 504 vfree(area->addr); 505 return NULL; 506 } 507 pfn >>= 1; /* make it a true pfn */ 508 509 if (__alpha_remap_area_pages(vaddr, 510 pfn << PAGE_SHIFT, 511 PAGE_SIZE, 0)) { 512 printk("FAILED to remap_area_pages...\n"); 513 vfree(area->addr); 514 return NULL; 515 } 516 } 517 518 flush_tlb_all(); 519 520 vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK); 521 return (void __iomem *) vaddr; 522 } 523 524 /* Assume a legacy (read: VGA) address, and return appropriately. */ 525 return (void __iomem *)(addr + TITAN_MEM_BIAS); 526} 527 528void 529titan_iounmap(volatile void __iomem *xaddr) 530{ 531 unsigned long addr = (unsigned long) xaddr; 532 if (addr >= VMALLOC_START) 533 vfree((void *)(PAGE_MASK & addr)); 534} 535 536int 537titan_is_mmio(const volatile void __iomem *xaddr) 538{ 539 unsigned long addr = (unsigned long) xaddr; 540 541 if (addr >= VMALLOC_START) 542 return 1; 543 else 544 return (addr & 0x100000000UL) == 0; 545} 546 547#ifndef CONFIG_ALPHA_GENERIC 548EXPORT_SYMBOL(titan_ioportmap); 549EXPORT_SYMBOL(titan_ioremap); 550EXPORT_SYMBOL(titan_iounmap); 551EXPORT_SYMBOL(titan_is_mmio); 552#endif 553 554/* 555 * AGP GART Support. 556 */ 557#include <linux/agp_backend.h> 558#include <asm/agp_backend.h> 559#include <linux/slab.h> 560#include <linux/delay.h> 561 562struct titan_agp_aperture { 563 struct pci_iommu_arena *arena; 564 long pg_start; 565 long pg_count; 566}; 567 568static int 569titan_agp_setup(alpha_agp_info *agp) 570{ 571 struct titan_agp_aperture *aper; 572 573 if (!alpha_agpgart_size) 574 return -ENOMEM; 575 576 aper = kmalloc(sizeof(struct titan_agp_aperture), GFP_KERNEL); 577 if (aper == NULL) 578 return -ENOMEM; 579 580 aper->arena = agp->hose->sg_pci; 581 aper->pg_count = alpha_agpgart_size / PAGE_SIZE; 582 aper->pg_start = iommu_reserve(aper->arena, aper->pg_count, 583 aper->pg_count - 1); 584 if (aper->pg_start < 0) { 585 printk(KERN_ERR "Failed to reserve AGP memory\n"); 586 kfree(aper); 587 return -ENOMEM; 588 } 589 590 agp->aperture.bus_base = 591 aper->arena->dma_base + aper->pg_start * PAGE_SIZE; 592 agp->aperture.size = aper->pg_count * PAGE_SIZE; 593 agp->aperture.sysdata = aper; 594 595 return 0; 596} 597 598static void 599titan_agp_cleanup(alpha_agp_info *agp) 600{ 601 struct titan_agp_aperture *aper = agp->aperture.sysdata; 602 int status; 603 604 status = iommu_release(aper->arena, aper->pg_start, aper->pg_count); 605 if (status == -EBUSY) { 606 printk(KERN_WARNING 607 "Attempted to release bound AGP memory - unbinding\n"); 608 iommu_unbind(aper->arena, aper->pg_start, aper->pg_count); 609 status = iommu_release(aper->arena, aper->pg_start, 610 aper->pg_count); 611 } 612 if (status < 0) 613 printk(KERN_ERR "Failed to release AGP memory\n"); 614 615 kfree(aper); 616 kfree(agp); 617} 618 619static int 620titan_agp_configure(alpha_agp_info *agp) 621{ 622 union TPAchipPCTL pctl; 623 titan_pachip_port *port = agp->private; 624 pctl.pctl_q_whole = port->pctl.csr; 625 626 /* Side-Band Addressing? */ 627 pctl.pctl_r_bits.apctl_v_agp_sba_en = agp->mode.bits.sba; 628 629 /* AGP Rate? */ 630 pctl.pctl_r_bits.apctl_v_agp_rate = 0; /* 1x */ 631 if (agp->mode.bits.rate & 2) 632 pctl.pctl_r_bits.apctl_v_agp_rate = 1; /* 2x */ 633 634 /* RQ Depth? */ 635 pctl.pctl_r_bits.apctl_v_agp_hp_rd = 2; 636 pctl.pctl_r_bits.apctl_v_agp_lp_rd = 7; 637 638 /* 639 * AGP Enable. 640 */ 641 pctl.pctl_r_bits.apctl_v_agp_en = agp->mode.bits.enable; 642 643 /* Tell the user. */ 644 printk("Enabling AGP: %dX%s\n", 645 1 << pctl.pctl_r_bits.apctl_v_agp_rate, 646 pctl.pctl_r_bits.apctl_v_agp_sba_en ? " - SBA" : ""); 647 648 /* Write it. */ 649 port->pctl.csr = pctl.pctl_q_whole; 650 651 /* And wait at least 5000 66MHz cycles (per Titan spec). */ 652 udelay(100); 653 654 return 0; 655} 656 657static int 658titan_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem) 659{ 660 struct titan_agp_aperture *aper = agp->aperture.sysdata; 661 return iommu_bind(aper->arena, aper->pg_start + pg_start, 662 mem->page_count, mem->pages); 663} 664 665static int 666titan_agp_unbind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem) 667{ 668 struct titan_agp_aperture *aper = agp->aperture.sysdata; 669 return iommu_unbind(aper->arena, aper->pg_start + pg_start, 670 mem->page_count); 671} 672 673static unsigned long 674titan_agp_translate(alpha_agp_info *agp, dma_addr_t addr) 675{ 676 struct titan_agp_aperture *aper = agp->aperture.sysdata; 677 unsigned long baddr = addr - aper->arena->dma_base; 678 unsigned long pte; 679 680 if (addr < agp->aperture.bus_base || 681 addr >= agp->aperture.bus_base + agp->aperture.size) { 682 printk("%s: addr out of range\n", __func__); 683 return -EINVAL; 684 } 685 686 pte = aper->arena->ptes[baddr >> PAGE_SHIFT]; 687 if (!(pte & 1)) { 688 printk("%s: pte not valid\n", __func__); 689 return -EINVAL; 690 } 691 692 return (pte >> 1) << PAGE_SHIFT; 693} 694 695struct alpha_agp_ops titan_agp_ops = 696{ 697 .setup = titan_agp_setup, 698 .cleanup = titan_agp_cleanup, 699 .configure = titan_agp_configure, 700 .bind = titan_agp_bind_memory, 701 .unbind = titan_agp_unbind_memory, 702 .translate = titan_agp_translate 703}; 704 705alpha_agp_info * 706titan_agp_info(void) 707{ 708 alpha_agp_info *agp; 709 struct pci_controller *hose; 710 titan_pachip_port *port; 711 int hosenum = -1; 712 union TPAchipPCTL pctl; 713 714 /* 715 * Find the AGP port. 716 */ 717 port = &TITAN_pachip0->a_port; 718 if (titan_query_agp(port)) 719 hosenum = 2; 720 if (hosenum < 0 && 721 titan_pchip1_present && 722 titan_query_agp(port = &TITAN_pachip1->a_port)) 723 hosenum = 3; 724 725 /* 726 * Find the hose the port is on. 727 */ 728 for (hose = hose_head; hose; hose = hose->next) 729 if (hose->index == hosenum) 730 break; 731 732 if (!hose || !hose->sg_pci) 733 return NULL; 734 735 /* 736 * Allocate the info structure. 737 */ 738 agp = kmalloc(sizeof(*agp), GFP_KERNEL); 739 if (!agp) 740 return NULL; 741 742 /* 743 * Fill it in. 744 */ 745 agp->hose = hose; 746 agp->private = port; 747 agp->ops = &titan_agp_ops; 748 749 agp->aperture.bus_base = 0; 750 agp->aperture.size = 0; 751 agp->aperture.sysdata = NULL; 752 753 /* 754 * Capabilities. 755 */ 756 agp->capability.lw = 0; 757 agp->capability.bits.rate = 3; /* 2x, 1x */ 758 agp->capability.bits.sba = 1; 759 agp->capability.bits.rq = 7; /* 8 - 1 */ 760 761 /* 762 * Mode. 763 */ 764 pctl.pctl_q_whole = port->pctl.csr; 765 agp->mode.lw = 0; 766 agp->mode.bits.rate = 1 << pctl.pctl_r_bits.apctl_v_agp_rate; 767 agp->mode.bits.sba = pctl.pctl_r_bits.apctl_v_agp_sba_en; 768 agp->mode.bits.rq = 7; /* RQ Depth? */ 769 agp->mode.bits.enable = pctl.pctl_r_bits.apctl_v_agp_en; 770 771 return agp; 772} 773