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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/
1/*  *********************************************************************
2    *  SB1250 Board Support Package
3    *
4    *  Global constants and macros		File: sb1250_defs.h
5    *
6    *  This file contains macros and definitions used by the other
7    *  include files.
8    *
9    *  SB1250 specification level:  User's manual 1/02/02
10    *
11    *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
12    *
13    *********************************************************************
14    *
15    *  Copyright 2000,2001,2002,2003
16    *  Broadcom Corporation. All rights reserved.
17    *
18    *  This software is furnished under license and may be used and
19    *  copied only in accordance with the following terms and
20    *  conditions.  Subject to these conditions, you may download,
21    *  copy, install, use, modify and distribute modified or unmodified
22    *  copies of this software in source and/or binary form.  No title
23    *  or ownership is transferred hereby.
24    *
25    *  1) Any source code used, modified or distributed must reproduce
26    *     and retain this copyright notice and list of conditions
27    *     as they appear in the source file.
28    *
29    *  2) No right is granted to use any trade name, trademark, or
30    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
31    *     name may not be used to endorse or promote products derived
32    *     from this software without the prior written permission of
33    *     Broadcom Corporation.
34    *
35    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
36    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
37    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
38    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
39    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
40    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
41    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
43    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
44    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
45    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
46    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
47    *     THE POSSIBILITY OF SUCH DAMAGE.
48    ********************************************************************* */
49
50#ifndef _SB1250_DEFS_H
51#define _SB1250_DEFS_H
52
53/*
54 * These headers require ANSI C89 string concatenation, and GCC or other
55 * 'long long' (64-bit integer) support.
56 */
57#if !defined(__STDC__) && !defined(_MSC_VER)
58#error SiByte headers require ANSI C89 support
59#endif
60
61
62/*  *********************************************************************
63    *  Macros for feature tests, used to enable include file features
64    *  for chip features only present in certain chip revisions.
65    *
66    *  SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
67    *  which is to be exposed by the headers.  If undefined, it defaults to
68    *  "all features."
69    *
70    *  Use like:
71    *
72    *    #define SIBYTE_HDR_FEATURES	SIBYTE_HDR_FMASK_112x_PASS1
73    *
74    *		Generate defines only for that revision of chip.
75    *
76    *    #if SIBYTE_HDR_FEATURE(chip,pass)
77    *
78    *		True if header features for that revision or later of
79    *	        that particular chip type are enabled in SIBYTE_HDR_FEATURES.
80    *	        (Use this to bracket #defines for features present in a given
81    *		revision and later.)
82    *
83    *		Note that there is no implied ordering between chip types.
84    *
85    *		Note also that 'chip' and 'pass' must textually exactly
86    *		match the defines below.  So, for example,
87    *		SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
88    *		SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
89    *
90    *    #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
91    *
92    *		Same as SIBYTE_HDR_FEATURE, but true for the named revision
93    *		and earlier revisions of the named chip type.
94    *
95    *    #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
96    *
97    *		Same as SIBYTE_HDR_FEATURE, but only true for the named
98    *		revision of the named chip type.  (Note that this CANNOT
99    *		be used to verify that you're compiling only for that
100    *		particular chip/revision.  It will be true any time this
101    *		chip/revision is included in SIBYTE_HDR_FEATURES.)
102    *
103    *    #if SIBYTE_HDR_FEATURE_CHIP(chip)
104    *
105    *		True if header features for (any revision of) that chip type
106    *		are enabled in SIBYTE_HDR_FEATURES.  (Use this to bracket
107    *		#defines for features specific to a given chip type.)
108    *
109    *  Mask values currently include room for additional revisions of each
110    *  chip type, but can be renumbered at will.  Note that they MUST fit
111    *  into 31 bits and may not include C type constructs, for safe use in
112    *  CPP conditionals.  Bit positions within chip types DO indicate
113    *  ordering, so be careful when adding support for new minor revs.
114    ********************************************************************* */
115
116#define	SIBYTE_HDR_FMASK_1250_ALL		0x00000ff
117#define	SIBYTE_HDR_FMASK_1250_PASS1		0x0000001
118#define	SIBYTE_HDR_FMASK_1250_PASS2		0x0000002
119
120#define	SIBYTE_HDR_FMASK_112x_ALL		0x0000f00
121#define	SIBYTE_HDR_FMASK_112x_PASS1		0x0000100
122#define SIBYTE_HDR_FMASK_112x_PASS3		0x0000200
123
124/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
125#define	SIBYTE_HDR_FMASK(chip, pass)					\
126    (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
127#define	SIBYTE_HDR_FMASK_ALLREVS(chip)					\
128    (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
129
130#define	SIBYTE_HDR_FMASK_ALL						\
131    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
132
133#ifndef SIBYTE_HDR_FEATURES
134#define	SIBYTE_HDR_FEATURES			SIBYTE_HDR_FMASK_ALL
135#endif
136
137
138/* Bit mask for revisions of chip exclusively before the named revision.  */
139#define	SIBYTE_HDR_FMASK_BEFORE(chip, pass)				\
140    ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
141
142/* Bit mask for revisions of chip exclusively after the named revision.  */
143#define	SIBYTE_HDR_FMASK_AFTER(chip, pass)				\
144    (~(SIBYTE_HDR_FMASK(chip, pass)					\
145     | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
146
147
148/* True if header features enabled for (any revision of) that chip type.  */
149#define SIBYTE_HDR_FEATURE_CHIP(chip)					\
150    (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
151
152/* True if header features enabled for that rev or later, inclusive.  */
153#define SIBYTE_HDR_FEATURE(chip, pass)					\
154    (!! ((SIBYTE_HDR_FMASK(chip, pass)					\
155	  | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
156
157/* True if header features enabled for exactly that rev.  */
158#define SIBYTE_HDR_FEATURE_EXACT(chip, pass)				\
159    (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
160
161/* True if header features enabled for that rev or before, inclusive.  */
162#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass)				\
163    (!! ((SIBYTE_HDR_FMASK(chip, pass)					\
164	 | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
165
166
167/*  *********************************************************************
168    *  Naming schemes for constants in these files:
169    *
170    *  M_xxx           MASK constant (identifies bits in a register).
171    *                  For multi-bit fields, all bits in the field will
172    *                  be set.
173    *
174    *  K_xxx           "Code" constant (value for data in a multi-bit
175    *                  field).  The value is right justified.
176    *
177    *  V_xxx           "Value" constant.  This is the same as the
178    *                  corresponding "K_xxx" constant, except it is
179    *                  shifted to the correct position in the register.
180    *
181    *  S_xxx           SHIFT constant.  This is the number of bits that
182    *                  a field value (code) needs to be shifted
183    *                  (towards the left) to put the value in the right
184    *                  position for the register.
185    *
186    *  A_xxx           ADDRESS constant.  This will be a physical
187    *                  address.  Use the PHYS_TO_K1 macro to generate
188    *                  a K1SEG address.
189    *
190    *  R_xxx           RELATIVE offset constant.  This is an offset from
191    *                  an A_xxx constant (usually the first register in
192    *                  a group).
193    *
194    *  G_xxx(X)        GET value.  This macro obtains a multi-bit field
195    *                  from a register, masks it, and shifts it to
196    *                  the bottom of the register (retrieving a K_xxx
197    *                  value, for example).
198    *
199    *  V_xxx(X)        VALUE.  This macro computes the value of a
200    *                  K_xxx constant shifted to the correct position
201    *                  in the register.
202    ********************************************************************* */
203
204
205
206
207/*
208 * Cast to 64-bit number.  Presumably the syntax is different in
209 * assembly language.
210 *
211 * Note: you'll need to define uint32_t and uint64_t in your headers.
212 */
213
214#if !defined(__ASSEMBLER__)
215#define _SB_MAKE64(x) ((uint64_t)(x))
216#define _SB_MAKE32(x) ((uint32_t)(x))
217#else
218#define _SB_MAKE64(x) (x)
219#define _SB_MAKE32(x) (x)
220#endif
221
222
223/*
224 * Make a mask for 1 bit at position 'n'
225 */
226
227#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
228#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
229
230/*
231 * Make a mask for 'v' bits at position 'n'
232 */
233
234#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
235#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
236
237/*
238 * Make a value at 'v' at bit position 'n'
239 */
240
241#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
242#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n))
243
244#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
245#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
246
247
248
249#if defined(__mips64) && !defined(__ASSEMBLER__)
250#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
251#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
252#endif /* __ASSEMBLER__ */
253
254#endif
255