1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * BCM11xx Checkout Board definitions File: bcm91120c.h 5 * 6 * This file contains I/O, chip select, and GPIO assignments 7 * for the BCM91120c checkout board. 8 * 9 * Author: Mitch Lichtenberg (mpl@broadcom.com) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49/* 50 * I/O Address assignments for the CSWARM board 51 * 52 * Summary of address map: 53 * 54 * Address Size CSel Description 55 * --------------- ---- ------ -------------------------------- 56 * 0x1FC00000 2MB CS0 Boot ROM 57 * 0x1F800000 2MB CS1 Alternate boot ROM (PromICE) 58 * 0x1E000000 16MB CS2 Big Flash 59 * 0x100A0000 64KB CS3 LED display 60 * CS4 Unused 61 * CS5 Unused 62 * CS6 Unused 63 * CS7 Unused 64 * 65 * GPIO assignments 66 * 67 * GPIO# Direction Description 68 * ------- --------- ------------------------------------------ 69 * GPIO0 Input Not used 70 * GPIO1 Input Not used 71 * GPIO2 Input PHY Interrupt (interrupt) 72 * GPIO3 Input Not used 73 * GPIO4 Input Not used 74 * GPIO5 Input Temperature Sensor Alert (interrupt) 75 * GPIO6 Input Not used 76 * GPIO7 Input Not used 77 * GPIO8 Input Not used 78 * GPIO9 Input Not used 79 * GPIO10 Input Not used 80 * GPIO11 Input Not used 81 * GPIO12 Input Not used 82 * GPIO13 Input Not used 83 * GPIO14 Output Serial port 1 Loopback Enable 84 * GPIO15 Output Serial port 0 Loopback Enable 85 */ 86 87/* ********************************************************************* 88 * Macros 89 ********************************************************************* */ 90 91#define MB (1024*1024) 92#define K64 65536 93#define NUM64K(x) (((x)+(K64-1))/K64) 94 95 96/* ********************************************************************* 97 * GPIO pins 98 ********************************************************************* */ 99 100 101#define GPIO_PHY_INTERRUPT 2 102#define GPIO_TEMP_SENSOR_INT 5 103 104#define GPIO_SERIAL1_LOOPBACK 14 105#define GPIO_SERIAL0_LOOPBACK 15 106 107 108#define M_GPIO_SERIAL1_LOOPBACK _SB_MAKEMASK1(GPIO_SERIAL1_LOOPBACK) 109#define M_GPIO_SERIAL0_LOOPBACK _SB_MAKEMASK1(GPIO_SERIAL0_LOOPBACK) 110#define M_GPIO_PHY_INTERRUPT _SB_MAKEMASK1(GPIO_PHY_INTERRUPT) 111#define M_GPIO_TEMP_SENSOR_INT _SB_MAKEMASK1(GPIO_TEMP_SENSOR_INT) 112 113#define GPIO_OUTPUT_MASK (_SB_MAKEMASK1(GPIO_SERIAL0_LOOPBACK) | \ 114 _SB_MAKEMASK1(GPIO_SERIAL1_LOOPBACK) ) 115 116#define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_PHY_INTERRUPT,K_GPIO_INTR_LEVEL)) | \ 117 (V_GPIO_INTR_TYPEX(GPIO_TEMP_SENSOR_INT,K_GPIO_INTR_LEVEL))) 118 119 120/* ********************************************************************* 121 * Generic Bus 122 ********************************************************************* */ 123 124#define BOOTROM_CS 0 125#define BOOTROM_PHYS 0x1FC00000 /* address of boot ROM (CS0) */ 126#define BOOTROM_SIZE NUM64K(2*MB) /* size of boot ROM */ 127#define BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 128 V_IO_ALE_TO_CS(2) | \ 129 V_IO_CS_WIDTH(24) | \ 130 V_IO_RDY_SMPLE(1) 131#define BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 132 V_IO_WRITE_WIDTH(7) | \ 133 V_IO_IDLE_CYCLE(6) | \ 134 V_IO_CS_TO_OE(0) | \ 135 V_IO_OE_TO_CS(0) 136#define BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 137 138#define ALT_BOOTROM_CS 1 139#define ALT_BOOTROM_PHYS 0x1F800000 /* address of alternate boot ROM (CS1) */ 140#define ALT_BOOTROM_SIZE NUM64K(2*MB) /* size of alternate boot ROM */ 141#define ALT_BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 142 V_IO_ALE_TO_CS(2) | \ 143 V_IO_CS_WIDTH(24) | \ 144 V_IO_RDY_SMPLE(1) 145#define ALT_BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 146 V_IO_WRITE_WIDTH(7) | \ 147 V_IO_IDLE_CYCLE(6) | \ 148 V_IO_CS_TO_OE(0) | \ 149 V_IO_OE_TO_CS(0) 150#define ALT_BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 151 152 153#define BIG_FLASH_CS 2 154#define BIG_FLASH_PHYS 0x1E000000 /* address of big flash ROM (CS2) */ 155#define BIG_FLASH_SIZE NUM64K(16*MB) /* size of big flash ROM */ 156#define BIG_FLASH_TIMING0 V_IO_ALE_WIDTH(4) | \ 157 V_IO_ALE_TO_CS(2) | \ 158 V_IO_CS_WIDTH(24) | \ 159 V_IO_RDY_SMPLE(1) 160#define BIG_FLASH_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 161 V_IO_WRITE_WIDTH(7) | \ 162 V_IO_IDLE_CYCLE(6) | \ 163 V_IO_CS_TO_OE(0) | \ 164 V_IO_OE_TO_CS(0) 165#define BIG_FLASH_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 166 167/* 168 * LEDs: non-multiplexed, byte width, no parity, no ack 169 */ 170#define LEDS_CS 3 171#define LEDS_PHYS 0x100A0000 172#define LEDS_SIZE NUM64K(4) 173#define LEDS_TIMING0 V_IO_ALE_WIDTH(4) | \ 174 V_IO_ALE_TO_CS(2) | \ 175 V_IO_CS_WIDTH(13) | \ 176 V_IO_RDY_SMPLE(1) 177#define LEDS_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 178 V_IO_WRITE_WIDTH(8) | \ 179 V_IO_IDLE_CYCLE(6) | \ 180 V_IO_CS_TO_OE(0) | \ 181 V_IO_OE_TO_CS(0) 182#define LEDS_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 183 184 185 186/* ********************************************************************* 187 * SMBus Devices 188 ********************************************************************* */ 189 190#define TEMPSENSOR_SMBUS_CHAN 0 191#define TEMPSENSOR_SMBUS_DEV 0x2A 192#define BIGEEPROM0_SMBUS_CHAN 0 193#define BIGEEPROM0_SMBUS_DEV 0x50 194#define BIGEEPROM1_SMBUS_CHAN 1 195#define BIGEEPROM1_SMBUS_DEV 0x50 196#define X1240_SMBUS_CHAN 1 197#define X1240_SMBUS_DEV 0x57 198 199#define M41T81_SMBUS_CHAN 1 /* Only on newer CRhines */ 200#define M41T81_SMBUS_DEV 0x68 /* that does not have an X1240 */ 201