1 2/********************************************************************* 3 * 4 * vlsi_ir.h: VLSI82C147 PCI IrDA controller driver for Linux 5 * 6 * Version: 0.3, Sep 30, 2001 7 * 8 * Copyright (c) 2001 Martin Diehl 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 * 25 ********************************************************************/ 26 27#ifndef IRDA_VLSI_FIR_H 28#define IRDA_VLSI_FIR_H 29 30/* ================================================================ */ 31 32/* non-standard PCI registers */ 33 34enum vlsi_pci_regs { 35 VLSI_PCI_CLKCTL = 0x40, /* chip clock input control */ 36 VLSI_PCI_MSTRPAGE = 0x41, /* addr [31:24] for all busmaster cycles */ 37 VLSI_PCI_IRMISC = 0x42 /* mainly legacy UART related */ 38}; 39 40/* ------------------------------------------ */ 41 42/* VLSI_PCI_CLKCTL: Clock Control Register (u8, rw) */ 43 44/* Three possible clock sources: either on-chip 48MHz PLL or 45 * external clock applied to EXTCLK pin. External clock may 46 * be either 48MHz or 40MHz, which is indicated by XCKSEL. 47 * CLKSTP controls whether the selected clock source gets 48 * connected to the IrDA block. 49 * 50 * On my HP OB-800 the BIOS sets external 40MHz clock as source 51 * when IrDA enabled and I've never detected any PLL lock success. 52 * Apparently the 14.3...MHz OSC input required for the PLL to work 53 * is not connected and the 40MHz EXTCLK is provided externally. 54 * At least this is what makes the driver working for me. 55 */ 56 57enum vlsi_pci_clkctl { 58 59 /* PLL control */ 60 61 CLKCTL_NO_PD = 0x04, /* PD# (inverted power down) signal, 62 * i.e. PLL is powered, if NO_PD set */ 63 CLKCTL_LOCK = 0x40, /* (ro) set, if PLL is locked */ 64 65 /* clock source selection */ 66 67 CLKCTL_EXTCLK = 0x20, /* set to select external clock input */ 68 CLKCTL_XCKSEL = 0x10, /* set to indicate 40MHz EXTCLK, not 48MHz */ 69 70 /* IrDA block control */ 71 72 CLKCTL_CLKSTP = 0x80, /* set to disconnect from selected clock source */ 73 CLKCTL_WAKE = 0x08 /* set to enable wakeup feature: whenever IR activity 74 * is detected, NO_PD gets set and CLKSTP cleared */ 75}; 76 77/* ------------------------------------------ */ 78 79/* VLSI_PCI_MSTRPAGE: Master Page Register (u8, rw) and busmastering stuff */ 80 81#define DMA_MASK_USED_BY_HW 0xffffffff 82#define DMA_MASK_MSTRPAGE 0x00ffffff 83#define MSTRPAGE_VALUE (DMA_MASK_MSTRPAGE >> 24) 84 85 86 /* PCI busmastering is somewhat special for this guy - in short: 87 * 88 * We select to operate using MSTRPAGE=0 fixed, use ISA DMA 89 * address restrictions to make the PCI BM api aware of this, 90 * but ensure the hardware is dealing with real 32bit access. 91 * 92 * In detail: 93 * The chip executes normal 32bit busmaster cycles, i.e. 94 * drives all 32 address lines. These addresses however are 95 * composed of [0:23] taken from various busaddr-pointers 96 * and [24:31] taken from the MSTRPAGE register in the VLSI82C147 97 * config space. Therefore _all_ busmastering must be 98 * targeted to/from one single 16MB (busaddr-) superpage! 99 * The point is to make sure all the allocations for memory 100 * locations with busmaster access (ring descriptors, buffers) 101 * are indeed bus-mappable to the same 16MB range (for x86 this 102 * means they must reside in the same 16MB physical memory address 103 * range). The only constraint we have which supports "several objects 104 * mappable to common 16MB range" paradigma, is the old ISA DMA 105 * restriction to the first 16MB of physical address range. 106 * Hence the approach here is to enable PCI busmaster support using 107 * the correct 32bit dma-mask used by the chip. Afterwards the device's 108 * dma-mask gets restricted to 24bit, which must be honoured somehow by 109 * all allocations for memory areas to be exposed to the chip ... 110 * 111 * Note: 112 * Don't be surprised to get "Setting latency timer..." messages every 113 * time when PCI busmastering is enabled for the chip. 114 * The chip has its PCI latency timer RO fixed at 0 - which is not a 115 * problem here, because it is never requesting _burst_ transactions. 116 */ 117 118/* ------------------------------------------ */ 119 120/* VLSI_PCIIRMISC: IR Miscellaneous Register (u8, rw) */ 121 122/* legacy UART emulation - not used by this driver - would require: 123 * (see below for some register-value definitions) 124 * 125 * - IRMISC_UARTEN must be set to enable UART address decoding 126 * - IRMISC_UARTSEL configured 127 * - IRCFG_MASTER must be cleared 128 * - IRCFG_SIR must be set 129 * - IRENABLE_IREN must be asserted 0->1 (and hence IRENABLE_SIR_ON) 130 */ 131 132enum vlsi_pci_irmisc { 133 134 /* IR transceiver control */ 135 136 IRMISC_IRRAIL = 0x40, /* (ro?) IR rail power indication (and control?) 137 * 0=3.3V / 1=5V. Probably set during power-on? 138 * unclear - not touched by driver */ 139 IRMISC_IRPD = 0x08, /* transceiver power down, if set */ 140 141 /* legacy UART control */ 142 143 IRMISC_UARTTST = 0x80, /* UART test mode - "always write 0" */ 144 IRMISC_UARTEN = 0x04, /* enable UART address decoding */ 145 146 /* bits [1:0] IRMISC_UARTSEL to select legacy UART address */ 147 148 IRMISC_UARTSEL_3f8 = 0x00, 149 IRMISC_UARTSEL_2f8 = 0x01, 150 IRMISC_UARTSEL_3e8 = 0x02, 151 IRMISC_UARTSEL_2e8 = 0x03 152}; 153 154 155/* ================================================================ */ 156 157/* registers mapped to 32 byte PCI IO space */ 158 159/* note: better access all registers at the indicated u8/u16 size 160 * although some of them contain only 1 byte of information. 161 * some of them (particaluarly PROMPT and IRCFG) ignore 162 * access when using the wrong addressing mode! 163 */ 164 165enum vlsi_pio_regs { 166 VLSI_PIO_IRINTR = 0x00, /* interrupt enable/request (u8, rw) */ 167 VLSI_PIO_RINGPTR = 0x02, /* rx/tx ring pointer (u16, ro) */ 168 VLSI_PIO_RINGBASE = 0x04, /* [23:10] of ring address (u16, rw) */ 169 VLSI_PIO_RINGSIZE = 0x06, /* rx/tx ring size (u16, rw) */ 170 VLSI_PIO_PROMPT = 0x08, /* triggers ring processing (u16, wo) */ 171 /* 0x0a-0x0f: reserved / duplicated UART regs */ 172 VLSI_PIO_IRCFG = 0x10, /* configuration select (u16, rw) */ 173 VLSI_PIO_SIRFLAG = 0x12, /* BOF/EOF for filtered SIR (u16, ro) */ 174 VLSI_PIO_IRENABLE = 0x14, /* enable and status register (u16, rw/ro) */ 175 VLSI_PIO_PHYCTL = 0x16, /* physical layer current status (u16, ro) */ 176 VLSI_PIO_NPHYCTL = 0x18, /* next physical layer select (u16, rw) */ 177 VLSI_PIO_MAXPKT = 0x1a, /* [11:0] max len for packet receive (u16, rw) */ 178 VLSI_PIO_RCVBCNT = 0x1c /* current receive-FIFO byte count (u16, ro) */ 179 /* 0x1e-0x1f: reserved / duplicated UART regs */ 180}; 181 182/* ------------------------------------------ */ 183 184/* VLSI_PIO_IRINTR: Interrupt Register (u8, rw) */ 185 186/* enable-bits: 187 * 1 = enable / 0 = disable 188 * interrupt condition bits: 189 * set according to corresponding interrupt source 190 * (regardless of the state of the enable bits) 191 * enable bit status indicates whether interrupt gets raised 192 * write-to-clear 193 * note: RPKTINT and TPKTINT behave different in legacy UART mode (which we don't use :-) 194 */ 195 196enum vlsi_pio_irintr { 197 IRINTR_ACTEN = 0x80, /* activity interrupt enable */ 198 IRINTR_ACTIVITY = 0x40, /* activity monitor (traffic detected) */ 199 IRINTR_RPKTEN = 0x20, /* receive packet interrupt enable*/ 200 IRINTR_RPKTINT = 0x10, /* rx-packet transfered from fifo to memory finished */ 201 IRINTR_TPKTEN = 0x08, /* transmit packet interrupt enable */ 202 IRINTR_TPKTINT = 0x04, /* last bit of tx-packet+crc shifted to ir-pulser */ 203 IRINTR_OE_EN = 0x02, /* UART rx fifo overrun error interrupt enable */ 204 IRINTR_OE_INT = 0x01 /* UART rx fifo overrun error (read LSR to clear) */ 205}; 206 207/* we use this mask to check whether the (shared PCI) interrupt is ours */ 208 209#define IRINTR_INT_MASK (IRINTR_ACTIVITY|IRINTR_RPKTINT|IRINTR_TPKTINT) 210 211/* ------------------------------------------ */ 212 213/* VLSI_PIO_RINGPTR: Ring Pointer Read-Back Register (u16, ro) */ 214 215/* _both_ ring pointers are indices relative to the _entire_ rx,tx-ring! 216 * i.e. the referenced descriptor is located 217 * at RINGBASE + PTR * sizeof(descr) for rx and tx 218 * therefore, the tx-pointer has offset MAX_RING_DESCR 219 */ 220 221#define MAX_RING_DESCR 64 /* tx, rx rings may contain up to 64 descr each */ 222 223#define RINGPTR_RX_MASK (MAX_RING_DESCR-1) 224#define RINGPTR_TX_MASK ((MAX_RING_DESCR-1)<<8) 225 226#define RINGPTR_GET_RX(p) ((p)&RINGPTR_RX_MASK) 227#define RINGPTR_GET_TX(p) (((p)&RINGPTR_TX_MASK)>>8) 228 229/* ------------------------------------------ */ 230 231/* VLSI_PIO_RINGBASE: Ring Pointer Base Address Register (u16, ro) */ 232 233/* Contains [23:10] part of the ring base (bus-) address 234 * which must be 1k-alinged. [31:24] is taken from 235 * VLSI_PCI_MSTRPAGE above. 236 * The controller initiates non-burst PCI BM cycles to 237 * fetch and update the descriptors in the ring. 238 * Once fetched, the descriptor remains cached onchip 239 * until it gets closed and updated due to the ring 240 * processing state machine. 241 * The entire ring area is split in rx and tx areas with each 242 * area consisting of 64 descriptors of 8 bytes each. 243 * The rx(tx) ring is located at ringbase+0 (ringbase+64*8). 244 */ 245 246#define BUS_TO_RINGBASE(p) (((p)>>10)&0x3fff) 247 248/* ------------------------------------------ */ 249 250/* VLSI_PIO_RINGSIZE: Ring Size Register (u16, rw) */ 251 252/* bit mask to indicate the ring size to be used for rx and tx. 253 * possible values encoded bits 254 * 4 0000 255 * 8 0001 256 * 16 0011 257 * 32 0111 258 * 64 1111 259 * located at [15:12] for tx and [11:8] for rx ([7:0] unused) 260 * 261 * note: probably a good idea to have IRCFG_MSTR cleared when writing 262 * this so the state machines are stopped and the RINGPTR is reset! 263 */ 264 265#define SIZE_TO_BITS(num) ((((num)-1)>>2)&0x0f) 266#define TX_RX_TO_RINGSIZE(tx,rx) ((SIZE_TO_BITS(tx)<<12)|(SIZE_TO_BITS(rx)<<8)) 267#define RINGSIZE_TO_RXSIZE(rs) ((((rs)&0x0f00)>>6)+4) 268#define RINGSIZE_TO_TXSIZE(rs) ((((rs)&0xf000)>>10)+4) 269 270 271/* ------------------------------------------ */ 272 273/* VLSI_PIO_PROMPT: Ring Prompting Register (u16, write-to-start) */ 274 275/* writing any value kicks the ring processing state machines 276 * for both tx, rx rings as follows: 277 * - active rings (currently owning an active descriptor) 278 * ignore the prompt and continue 279 * - idle rings fetch the next descr from the ring and start 280 * their processing 281 */ 282 283/* ------------------------------------------ */ 284 285/* VLSI_PIO_IRCFG: IR Config Register (u16, rw) */ 286 287/* notes: 288 * - not more than one SIR/MIR/FIR bit must be set at any time 289 * - SIR, MIR, FIR and CRC16 select the configuration which will 290 * be applied on next 0->1 transition of IRENABLE_IREN (see below). 291 * - besides allowing the PCI interface to execute busmaster cycles 292 * and therefore the ring SM to operate, the MSTR bit has side-effects: 293 * when MSTR is cleared, the RINGPTR's get reset and the legacy UART mode 294 * (in contrast to busmaster access mode) gets enabled. 295 * - clearing ENRX or setting ENTX while data is received may stall the 296 * receive fifo until ENRX reenabled _and_ another packet arrives 297 * - SIRFILT means the chip performs the required unwrapping of hardware 298 * headers (XBOF's, BOF/EOF) and un-escaping in the _receive_ direction. 299 * Only the resulting IrLAP payload is copied to the receive buffers - 300 * but with the 16bit FCS still encluded. Question remains, whether it 301 * was already checked or we should do it before passing the packet to IrLAP? 302 */ 303 304enum vlsi_pio_ircfg { 305 IRCFG_LOOP = 0x4000, /* enable loopback test mode */ 306 IRCFG_ENTX = 0x1000, /* transmit enable */ 307 IRCFG_ENRX = 0x0800, /* receive enable */ 308 IRCFG_MSTR = 0x0400, /* master enable */ 309 IRCFG_RXANY = 0x0200, /* receive any packet */ 310 IRCFG_CRC16 = 0x0080, /* 16bit (not 32bit) CRC select for MIR/FIR */ 311 IRCFG_FIR = 0x0040, /* FIR 4PPM encoding mode enable */ 312 IRCFG_MIR = 0x0020, /* MIR HDLC encoding mode enable */ 313 IRCFG_SIR = 0x0010, /* SIR encoding mode enable */ 314 IRCFG_SIRFILT = 0x0008, /* enable SIR decode filter (receiver unwrapping) */ 315 IRCFG_SIRTEST = 0x0004, /* allow SIR decode filter when not in SIR mode */ 316 IRCFG_TXPOL = 0x0002, /* invert tx polarity when set */ 317 IRCFG_RXPOL = 0x0001 /* invert rx polarity when set */ 318}; 319 320/* ------------------------------------------ */ 321 322/* VLSI_PIO_SIRFLAG: SIR Flag Register (u16, ro) */ 323 324/* register contains hardcoded BOF=0xc0 at [7:0] and EOF=0xc1 at [15:8] 325 * which is used for unwrapping received frames in SIR decode-filter mode 326 */ 327 328/* ------------------------------------------ */ 329 330/* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */ 331 332/* notes: 333 * - IREN acts as gate for latching the configured IR mode information 334 * from IRCFG and IRPHYCTL when IREN=reset and applying them when 335 * IREN gets set afterwards. 336 * - ENTXST reflects IRCFG_ENTX 337 * - ENRXST = IRCFG_ENRX && (!IRCFG_ENTX || IRCFG_LOOP) 338 */ 339 340enum vlsi_pio_irenable { 341 IRENABLE_IREN = 0x8000, /* enable IR phy and gate the mode config (rw) */ 342 IRENABLE_CFGER = 0x4000, /* mode configuration error (ro) */ 343 IRENABLE_FIR_ON = 0x2000, /* FIR on status (ro) */ 344 IRENABLE_MIR_ON = 0x1000, /* MIR on status (ro) */ 345 IRENABLE_SIR_ON = 0x0800, /* SIR on status (ro) */ 346 IRENABLE_ENTXST = 0x0400, /* transmit enable status (ro) */ 347 IRENABLE_ENRXST = 0x0200, /* Receive enable status (ro) */ 348 IRENABLE_CRC16_ON = 0x0100 /* 16bit (not 32bit) CRC enabled status (ro) */ 349}; 350 351#define IRENABLE_MASK 0xff00 /* Read mask */ 352 353 354/* ------------------------------------------ */ 355 356/* VLSI_PIO_PHYCTL: IR Physical Layer Current Control Register (u16, ro) */ 357 358 359/* read-back of the currently applied physical layer status. 360 * applied from VLSI_PIO_NPHYCTL at rising edge of IRENABLE_IREN 361 * contents identical to VLSI_PIO_NPHYCTL (see below) 362 */ 363 364 365 366/* ------------------------------------------ */ 367 368 369/* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */ 370 371/* latched during IRENABLE_IREN=0 and applied at 0-1 transition 372 * 373 * consists of BAUD[15:10], PLSWID[9:5] and PREAMB[4:0] bits defined as follows: 374 * 375 * SIR-mode: BAUD = (115.2kHz / baudrate) - 1 376 * PLSWID = (pulsetime * freq / (BAUD+1)) - 1 377 * where pulsetime is the requested IrPHY pulse width 378 * and freq is 8(16)MHz for 40(48)MHz primary input clock 379 * PREAMB: dont care for SIR 380 * 381 * The nominal SIR pulse width is 3/16 bit time so we have PLSWID=12 382 * fixed for all SIR speeds at 40MHz input clock (PLSWID=24 at 48MHz). 383 * IrPHY also allows shorter pulses down to the nominal pulse duration 384 * at 115.2kbaud (minus some tolerance) which is 1.41 usec. 385 * Using the expression PLSWID = 12/(BAUD+1)-1 (multiplied by to for 48MHz) 386 * we get the minimum acceptable PLSWID values according to the VLSI 387 * specification, which provides 1.5 usec pulse width for all speeds (except 388 * for 2.4kbaud getting 6usec). This is well inside IrPHY v1.3 specs and 389 * reduces the transceiver power which drains the battery. At 9.6kbaud for 390 * example this amounts to more than 90% battery power saving! 391 * 392 * MIR-mode: BAUD = 0 393 * PLSWID = 9(10) for 40(48) MHz input clock 394 * to get nominal MIR pulse width 395 * PREAMB = 1 396 * 397 * FIR-mode: BAUD = 0 398 * PLSWID: dont care 399 * PREAMB = 15 400 */ 401 402#define BWP_TO_PHYCTL(B,W,P) ((((B)&0x3f)<<10) | (((W)&0x1f)<<5) | (((P)&0x1f)<<0)) 403#define BAUD_BITS(br) ((115200/(br))-1) 404 405static inline unsigned 406calc_width_bits(unsigned baudrate, unsigned widthselect, unsigned clockselect) 407{ 408 unsigned tmp; 409 410 if (widthselect) /* nominal 3/16 puls width */ 411 return (clockselect) ? 12 : 24; 412 413 tmp = ((clockselect) ? 12 : 24) / (BAUD_BITS(baudrate)+1); 414 415 /* intermediate result of integer division needed here */ 416 417 return (tmp>0) ? (tmp-1) : 0; 418} 419 420 421#define PHYCTL_SIR(br,ws,cs) BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0) 422#define PHYCTL_MIR(cs) BWP_TO_PHYCTL(0,((cs)?9:10),1) 423#define PHYCTL_FIR BWP_TO_PHYCTL(0,0,15) 424 425/* quite ugly, I know. But implementing these calculations here avoids 426 * having magic numbers in the code and allows some playing with pulsewidths 427 * without risk to violate the standards. 428 * FWIW, here is the table for reference: 429 * 430 * baudrate BAUD min-PLSWID nom-PLSWID PREAMB 431 * 2400 47 0(0) 12(24) 0 432 * 9600 11 0(0) 12(24) 0 433 * 19200 5 1(2) 12(24) 0 434 * 38400 2 3(6) 12(24) 0 435 * 57600 1 5(10) 12(24) 0 436 * 115200 0 11(22) 12(24) 0 437 * MIR 0 - 9(10) 1 438 * FIR 0 - 0 15 439 * 440 * note: x(y) means x-value for 40MHz / y-value for 48MHz primary input clock 441 */ 442 443/* ------------------------------------------ */ 444 445 446/* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */ 447 448/* specifies the maximum legth (up to 4k - or (4k-1)? - bytes), which a 449 * received frame may have - i.e. the size of the corresponding 450 * receive buffers. For simplicity we use the same length for 451 * receive and submit buffers and increase transfer buffer size 452 * byond IrDA-MTU = 2048 so we have sufficient space left when 453 * packet size increases during wrapping due to XBOFs and CE's. 454 * Even for receiving unwrapped frames we need >MAX_PACKET_LEN 455 * space since the controller appends FCS/CRC (2 or 4 bytes) 456 * so we use 2*IrDA-MTU for both directions and cover even the 457 * worst case, where all data bytes have to be escaped when wrapping. 458 * well, this wastes some memory - anyway, later we will 459 * either map skb's directly or use pci_pool allocator... 460 */ 461 462#define IRDA_MTU 2048 /* seems to be undefined elsewhere */ 463 464#define XFER_BUF_SIZE (2*IRDA_MTU) 465 466#define MAX_PACKET_LENGTH (XFER_BUF_SIZE-1) /* register uses only [11:0] */ 467 468 469/* ------------------------------------------ */ 470 471 472/* VLSI_PIO_RCVBCNT: Receive Byte Count Register (u16, ro) */ 473 474/* recive packet counter gets incremented on every non-filtered 475 * byte which was put in the receive fifo and reset for each 476 * new packet. Used to decide whether we are just in the middle 477 * of receiving 478 */ 479 480#define RCVBCNT_MASK 0x0fff 481 482/* ================================================================ */ 483 484 485 486struct ring_descr { 487 volatile u16 rd_count; /* tx/rx count [11:0] */ 488 u16 reserved; 489 union { 490 u32 addr; /* [23:0] of the buffer's busaddress */ 491 struct { 492 u8 addr_res[3]; 493 volatile u8 status; /* descriptor status */ 494 } rd_s; 495 } rd_u; 496}; 497 498#define rd_addr rd_u.addr 499#define rd_status rd_u.rd_s.status 500 501 502/* ring descriptor status bits */ 503 504#define RD_STAT_ACTIVE 0x80 /* descriptor owned by hw (both TX,RX) */ 505 506/* TX ring descriptor status */ 507 508#define TX_STAT_DISCRC 0x40 /* do not send CRC (for SIR) */ 509#define TX_STAT_BADCRC 0x20 /* force a bad CRC */ 510#define TX_STAT_PULSE 0x10 /* send indication pulse after this frame (MIR/FIR) */ 511#define TX_STAT_FRCEUND 0x08 /* force underrun */ 512#define TX_STAT_CLRENTX 0x04 /* clear ENTX after this frame */ 513#define TX_STAT_UNDRN 0x01 /* TX fifo underrun (probably PCI problem) */ 514 515/* RX ring descriptor status */ 516 517#define RX_STAT_PHYERR 0x40 /* physical encoding error */ 518#define RX_STAT_CRCERR 0x20 /* CRC error (MIR/FIR) */ 519#define RX_STAT_LENGTH 0x10 /* frame exceeds buffer length */ 520#define RX_STAT_OVER 0x08 /* RX fifo overrun (probably PCI problem) */ 521#define RX_STAT_SIRBAD 0x04 /* EOF missing: BOF follows BOF (SIR, filtered) */ 522 523 524#define RX_STAT_ERROR 0x7c /* any error in frame */ 525 526 527/* ------------------------------------------ */ 528 529/* contains the objects we've put into the ring descriptors 530 * static buffers for now - probably skb's later 531 */ 532 533struct ring_entry { 534 struct sk_buff *skb; 535 void *data; 536}; 537 538 539struct vlsi_ring { 540 unsigned size; 541 unsigned mask; 542 unsigned head, tail; 543 struct ring_descr *hw; 544 struct ring_entry buf[MAX_RING_DESCR]; 545}; 546 547/* ------------------------------------------ */ 548 549/* our private compound VLSI-PCI-IRDA device information */ 550 551typedef struct vlsi_irda_dev { 552 struct pci_dev *pdev; 553 struct net_device_stats stats; 554 555 struct irlap_cb *irlap; 556 557 struct qos_info qos; 558 559 unsigned mode; 560 int baud, new_baud; 561 562 dma_addr_t busaddr; 563 void *virtaddr; 564 struct vlsi_ring tx_ring, rx_ring; 565 566 struct timeval last_rx; 567 568 spinlock_t lock; 569 570} vlsi_irda_dev_t; 571 572/********************************************************/ 573 574#endif /* IRDA_VLSI_FIR_H */ 575 576