1/* 2 * mcs01_pci.h 3 * 4 * Carsten Langgaard, carstenl@mips.com 5 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 6 * 7 * ######################################################################## 8 * 9 * PCI Register definitions for the MIPS System Controller. 10 */ 11#ifndef MSC01_PCI_H 12#define MSC01_PCI_H 13 14/***************************************************************************** 15 * Register offset addresses 16 ****************************************************************************/ 17 18#define MSC01_PCI_ID_OFS 0x0000 19#define MSC01_PCI_SC2PMBASL_OFS 0x0208 20#define MSC01_PCI_SC2PMMSKL_OFS 0x0218 21#define MSC01_PCI_SC2PMMAPL_OFS 0x0228 22#define MSC01_PCI_SC2PIOBASL_OFS 0x0248 23#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 24#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 25#define MSC01_PCI_P2SCMSKL_OFS 0x0308 26#define MSC01_PCI_P2SCMAPL_OFS 0x0318 27#define MSC01_PCI_INTCFG_OFS 0x0600 28#define MSC01_PCI_INTSTAT_OFS 0x0608 29#define MSC01_PCI_CFGADDR_OFS 0x0610 30#define MSC01_PCI_CFGDATA_OFS 0x0618 31#define MSC01_PCI_IACK_OFS 0x0620 32#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ 33#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ 34#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ 35#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ 36#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ 37#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ 38#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ 39#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ 40#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ 41#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ 42#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ 43#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ 44#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ 45#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ 46#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ 47#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ 48#define MSC01_PCI_BAR0_OFS 0x2220 49#define MSC01_PCI_CFG_OFS 0x2380 50#define MSC01_PCI_SWAP_OFS 0x2388 51 52 53/***************************************************************************** 54 * Register encodings 55 ****************************************************************************/ 56 57#define MSC01_PCI_ID_ID_SHF 16 58#define MSC01_PCI_ID_ID_MSK 0x00ff0000 59#define MSC01_PCI_ID_ID_HOSTBRIDGE 82 60#define MSC01_PCI_ID_MAR_SHF 8 61#define MSC01_PCI_ID_MAR_MSK 0x0000ff00 62#define MSC01_PCI_ID_MIR_SHF 0 63#define MSC01_PCI_ID_MIR_MSK 0x000000ff 64 65#define MSC01_PCI_SC2PMBASL_BAS_SHF 24 66#define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000 67 68#define MSC01_PCI_SC2PMMSKL_MSK_SHF 24 69#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 70 71#define MSC01_PCI_SC2PMMAPL_MAP_SHF 24 72#define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000 73 74#define MSC01_PCI_SC2PIOBASL_BAS_SHF 24 75#define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000 76 77#define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24 78#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 79 80#define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24 81#define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000 82 83#define MSC01_PCI_P2SCMSKL_MSK_SHF 24 84#define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000 85 86#define MSC01_PCI_P2SCMAPL_MAP_SHF 24 87#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 88 89#define MSC01_PCI_INTCFG_RST_SHF 10 90#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 91#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 92#define MSC01_PCI_INTCFG_MWE_SHF 9 93#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 94#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 95#define MSC01_PCI_INTCFG_DTO_SHF 8 96#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 97#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 98#define MSC01_PCI_INTCFG_MA_SHF 7 99#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 100#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 101#define MSC01_PCI_INTCFG_TA_SHF 6 102#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 103#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 104#define MSC01_PCI_INTCFG_RTY_SHF 5 105#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 106#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 107#define MSC01_PCI_INTCFG_MWP_SHF 4 108#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 109#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 110#define MSC01_PCI_INTCFG_MRP_SHF 3 111#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 112#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 113#define MSC01_PCI_INTCFG_SWP_SHF 2 114#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 115#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 116#define MSC01_PCI_INTCFG_SRP_SHF 1 117#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 118#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 119#define MSC01_PCI_INTCFG_SE_SHF 0 120#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 121#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 122 123#define MSC01_PCI_INTSTAT_RST_SHF 10 124#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 125#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 126#define MSC01_PCI_INTSTAT_MWE_SHF 9 127#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 128#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 129#define MSC01_PCI_INTSTAT_DTO_SHF 8 130#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 131#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 132#define MSC01_PCI_INTSTAT_MA_SHF 7 133#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 134#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 135#define MSC01_PCI_INTSTAT_TA_SHF 6 136#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 137#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 138#define MSC01_PCI_INTSTAT_RTY_SHF 5 139#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 140#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 141#define MSC01_PCI_INTSTAT_MWP_SHF 4 142#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 143#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 144#define MSC01_PCI_INTSTAT_MRP_SHF 3 145#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 146#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 147#define MSC01_PCI_INTSTAT_SWP_SHF 2 148#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 149#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 150#define MSC01_PCI_INTSTAT_SRP_SHF 1 151#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 152#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 153#define MSC01_PCI_INTSTAT_SE_SHF 0 154#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 155#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 156 157#define MSC01_PCI_CFGADDR_BNUM_SHF 16 158#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 159#define MSC01_PCI_CFGADDR_DNUM_SHF 11 160#define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800 161#define MSC01_PCI_CFGADDR_FNUM_SHF 8 162#define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700 163#define MSC01_PCI_CFGADDR_RNUM_SHF 2 164#define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc 165 166#define MSC01_PCI_CFGDATA_DATA_SHF 0 167#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff 168 169/* The defines below are ONLY valid for a MEM bar! */ 170#define MSC01_PCI_BAR0_SIZE_SHF 4 171#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 172#define MSC01_PCI_BAR0_P_SHF 3 173#define MSC01_PCI_BAR0_P_MSK 0x00000008 174#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK 175#define MSC01_PCI_BAR0_D_SHF 1 176#define MSC01_PCI_BAR0_D_MSK 0x00000006 177#define MSC01_PCI_BAR0_T_SHF 0 178#define MSC01_PCI_BAR0_T_MSK 0x00000001 179#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK 180 181 182#define MSC01_PCI_CFG_RA_SHF 17 183#define MSC01_PCI_CFG_RA_MSK 0x00020000 184#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK 185#define MSC01_PCI_CFG_G_SHF 16 186#define MSC01_PCI_CFG_G_MSK 0x00010000 187#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK 188#define MSC01_PCI_CFG_EN_SHF 15 189#define MSC01_PCI_CFG_EN_MSK 0x00008000 190#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK 191#define MSC01_PCI_CFG_MAXRTRY_SHF 0 192#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff 193 194#define MSC01_PCI_SWAP_IO_SHF 18 195#define MSC01_PCI_SWAP_IO_MSK 0x000c0000 196#define MSC01_PCI_SWAP_MEM_SHF 16 197#define MSC01_PCI_SWAP_MEM_MSK 0x00030000 198#define MSC01_PCI_SWAP_BAR0_SHF 0 199#define MSC01_PCI_SWAP_BAR0_MSK 0x00000003 200#define MSC01_PCI_SWAP_NOSWAP 0 201#define MSC01_PCI_SWAP_BYTESWAP 1 202 203/***************************************************************************** 204 * Registers absolute addresses 205 ****************************************************************************/ 206 207#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) 208#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) 209#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) 210#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) 211#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) 212#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) 213#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) 214#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) 215#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) 216#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) 217#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) 218#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) 219#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) 220#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) 221#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) 222#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) 223#define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS) 224#define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS) 225#define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS) 226#define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS) 227#define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS) 228#define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS) 229#define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS) 230#define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS) 231#define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS) 232#define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 233#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 234#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 235#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 236#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 237#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) 238#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) 239#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) 240 241#endif 242/***************************************************************************** 243 * End of msc01_pci.h 244 *****************************************************************************/ 245