1/* $Id: pbm.h,v 1.1.1.1 2008/10/15 03:29:18 james26_jang Exp $
2 * pbm.h: UltraSparc PCI controller software state.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 */
6
7#ifndef __SPARC64_PBM_H
8#define __SPARC64_PBM_H
9
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/ioport.h>
13#include <linux/spinlock.h>
14
15#include <asm/io.h>
16#include <asm/page.h>
17#include <asm/oplib.h>
18
19/* The abstraction used here is that there are PCI controllers,
20 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
21 * underneath.  Each PCI bus module uses an IOMMU (shared by both
22 * PBMs of a controller, or per-PBM), and if a streaming buffer
23 * is present, each PCI bus module has it's own. (ie. the IOMMU
24 * might be shared between PBMs, the STC is never shared)
25 * Furthermore, each PCI bus module controls it's own autonomous
26 * PCI bus.
27 */
28
29#define PBM_LOGCLUSTERS 3
30#define PBM_NCLUSTERS (1 << PBM_LOGCLUSTERS)
31
32struct pci_controller_info;
33
34/* This contains the software state necessary to drive a PCI
35 * controller's IOMMU.
36 */
37struct pci_iommu {
38	/* This protects the controller's IOMMU and all
39	 * streaming buffers underneath.
40	 */
41	spinlock_t	lock;
42
43	/* Context allocator. */
44	unsigned int	iommu_cur_ctx;
45
46	/* IOMMU page table, a linear array of ioptes. */
47	iopte_t		*page_table;		/* The page table itself. */
48	int		page_table_sz_bits;	/* log2 of ow many pages does it map? */
49
50	/* Base PCI memory space address where IOMMU mappings
51	 * begin.
52	 */
53	u32		page_table_map_base;
54
55	/* IOMMU Controller Registers */
56	unsigned long	iommu_control;		/* IOMMU control register */
57	unsigned long	iommu_tsbbase;		/* IOMMU page table base register */
58	unsigned long	iommu_flush;		/* IOMMU page flush register */
59	unsigned long	iommu_ctxflush;		/* IOMMU context flush register */
60
61	/* This is a register in the PCI controller, which if
62	 * read will have no side-effects but will guarentee
63	 * completion of all previous writes into IOMMU/STC.
64	 */
65	unsigned long	write_complete_reg;
66
67	/* The lowest used consistent mapping entry.  Since
68	 * we allocate consistent maps out of cluster 0 this
69	 * is relative to the beginning of closter 0.
70	 */
71	u32		lowest_consistent_map;
72
73	/* If PBM_NCLUSTERS is ever decreased to 4 or lower,
74	 * or if largest supported page_table_sz * 8K goes above
75	 * 2GB, you must increase the size of the type of
76	 * these counters.  You have been duly warned. -DaveM
77	 */
78	struct {
79		u16	next;
80		u16	flush;
81	} alloc_info[PBM_NCLUSTERS];
82
83	/* Here a PCI controller driver describes the areas of
84	 * PCI memory space where DMA to/from physical memory
85	 * are addressed.  Drivers interrogate the PCI layer
86	 * if their device has addressing limitations.  They
87	 * do so via pci_dma_supported, and pass in a mask of
88	 * DMA address bits their device can actually drive.
89	 *
90	 * The test for being usable is:
91	 * 	(device_mask & dma_addr_mask) == dma_addr_mask
92	 */
93	u32 dma_addr_mask;
94};
95
96/* This describes a PCI bus module's streaming buffer. */
97struct pci_strbuf {
98	int		strbuf_enabled;		/* Present and using it? */
99
100	/* Streaming Buffer Control Registers */
101	unsigned long	strbuf_control;		/* STC control register */
102	unsigned long	strbuf_pflush;		/* STC page flush register */
103	unsigned long	strbuf_fsync;		/* STC flush synchronization reg */
104	unsigned long	strbuf_ctxflush;	/* STC context flush register */
105	unsigned long	strbuf_ctxmatch_base;	/* STC context flush match reg */
106	unsigned long	strbuf_flushflag_pa;	/* Physical address of flush flag */
107	volatile unsigned long *strbuf_flushflag; /* The flush flag itself */
108
109	/* And this is the actual flush flag area.
110	 * We allocate extra because the chips require
111	 * a 64-byte aligned area.
112	 */
113	volatile unsigned long	__flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
114};
115
116#define PCI_STC_FLUSHFLAG_INIT(STC) \
117	(*((STC)->strbuf_flushflag) = 0UL)
118#define PCI_STC_FLUSHFLAG_SET(STC) \
119	(*((STC)->strbuf_flushflag) != 0UL)
120
121/* There can be quite a few ranges and interrupt maps on a PCI
122 * segment.  Thus...
123 */
124#define PROM_PCIRNG_MAX		64
125#define PROM_PCIIMAP_MAX	64
126
127struct pci_pbm_info {
128	/* PCI controller we sit under. */
129	struct pci_controller_info	*parent;
130
131	/* Name used for top-level resources. */
132	char				name[64];
133
134	/* OBP specific information. */
135	int				prom_node;
136	char				prom_name[64];
137	struct linux_prom_pci_ranges	pbm_ranges[PROM_PCIRNG_MAX];
138	int				num_pbm_ranges;
139	struct linux_prom_pci_intmap	pbm_intmap[PROM_PCIIMAP_MAX];
140	int				num_pbm_intmap;
141	struct linux_prom_pci_intmask	pbm_intmask;
142
143	/* PBM I/O and Memory space resources. */
144	struct resource			io_space;
145	struct resource			mem_space;
146
147	/* Base of PCI Config space, can be per-PBM or shared. */
148	unsigned long			config_space;
149
150	/* State of 66MHz capabilities on this PBM. */
151	int				is_66mhz_capable;
152	int				all_devs_66mhz;
153
154	/* This PBM's streaming buffer. */
155	struct pci_strbuf		stc;
156
157	/* IOMMU state, potentially shared by both PBM segments. */
158	struct pci_iommu		*iommu;
159
160	/* PCI slot mapping. */
161	unsigned int			pci_first_slot;
162
163	/* Now things for the actual PCI bus probes. */
164	unsigned int			pci_first_busno;
165	unsigned int			pci_last_busno;
166	struct pci_bus			*pci_bus;
167};
168
169struct pci_controller_info {
170	/* List of all PCI controllers. */
171	struct pci_controller_info	*next;
172
173	/* Physical address base of controller registers. */
174	unsigned long			controller_regs;
175
176	/* Opaque 32-bit system bus Port ID. */
177	u32				portid;
178
179	/* Each controller gets a unique index, used mostly for
180	 * error logging purposes.
181	 */
182	int				index;
183
184	/* Do the PBMs both exist in the same PCI domain? */
185	int				pbms_same_domain;
186
187	/* The PCI bus modules controlled by us. */
188	struct pci_pbm_info		pbm_A;
189	struct pci_pbm_info		pbm_B;
190
191	/* Operations which are controller specific. */
192	void (*scan_bus)(struct pci_controller_info *);
193	unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int);
194	void (*base_address_update)(struct pci_dev *, int);
195	void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
196
197	/* Now things for the actual PCI bus probes. */
198	struct pci_ops			*pci_ops;
199	unsigned int			pci_first_busno;
200	unsigned int			pci_last_busno;
201
202	void				*starfire_cookie;
203};
204
205/* PCI devices which are not bridges have this placed in their pci_dev
206 * sysdata member.  This makes OBP aware PCI device drivers easier to
207 * code.
208 */
209struct pcidev_cookie {
210	struct pci_pbm_info		*pbm;
211	char				prom_name[64];
212	int				prom_node;
213	struct linux_prom_pci_registers	prom_regs[PROMREG_MAX];
214	int num_prom_regs;
215	struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
216	int num_prom_assignments;
217};
218
219/* Currently these are the same across all PCI controllers
220 * we support.  Someday they may not be...
221 */
222#define PCI_IRQ_IGN	0x000007c0	/* Interrupt Group Number */
223#define PCI_IRQ_INO	0x0000003f	/* Interrupt Number */
224
225#endif /* !(__SPARC64_PBM_H) */
226