1#ifndef __ASM_SH_DMA_H
2#define __ASM_SH_DMA_H
3
4#include <linux/config.h>
5#include <asm/io.h>		/* need byte IO */
6
7#define MAX_DMA_CHANNELS 8
8#define SH_MAX_DMA_CHANNELS 4
9
10/* The maximum address that we can perform a DMA transfer to on this platform */
11/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
12   occurrence should be flagged as an error.  */
13/* But... */
14#define MAX_DMA_ADDRESS      (PAGE_OFFSET+0x10000000)
15
16#if defined(__sh3__)
17#define SAR ((unsigned long[]){0xa4000020,0xa4000030,0xa4000040,0xa4000050})
18#define DAR ((unsigned long[]){0xa4000024,0xa4000034,0xa4000044,0xa4000054})
19#define DMATCR ((unsigned long[]){0xa4000028,0xa4000038,0xa4000048,0xa4000058})
20#define CHCR ((unsigned long[]){0xa400002c,0xa400003c,0xa400004c,0xa400005c})
21#define DMAOR 0xa4000060UL
22#elif defined(__SH4__)
23#define SAR ((unsigned long[]){0xbfa00000,0xbfa00010,0xbfa00020,0xbfa00030})
24#define DAR ((unsigned long[]){0xbfa00004,0xbfa00014,0xbfa00024,0xbfa00034})
25#define DMATCR ((unsigned long[]){0xbfa00008,0xbfa00018,0xbfa00028,0xbfa00038})
26#define CHCR ((unsigned long[]){0xbfa0000c,0xbfa0001c,0xbfa0002c,0xbfa0003c})
27#define DMAOR 0xbfa00040UL
28#endif
29
30#define DMTE_IRQ ((int[]){DMTE0_IRQ,DMTE1_IRQ,DMTE2_IRQ,DMTE3_IRQ})
31
32#define DMA_MODE_READ	0x00	/* I/O to memory, no autoinit, increment, single mode */
33#define DMA_MODE_WRITE	0x01	/* memory to I/O, no autoinit, increment, single mode */
34#define DMA_AUTOINIT	0x10
35
36#define REQ_L	0x00000000
37#define REQ_E	0x00080000
38#define RACK_H	0x00000000
39#define RACK_L	0x00040000
40#define ACK_R	0x00000000
41#define ACK_W	0x00020000
42#define ACK_H	0x00000000
43#define ACK_L	0x00010000
44#define DM_INC	0x00004000
45#define DM_DEC	0x00008000
46#define SM_INC	0x00001000
47#define SM_DEC	0x00002000
48#define RS_DUAL	0x00000000
49#define RS_IN	0x00000200
50#define RS_OUT	0x00000300
51#define TM_BURST 0x0000080
52#define TS_8	0x00000010
53#define TS_16	0x00000020
54#define TS_32	0x00000030
55#define TS_64	0x00000000
56#define TS_BLK	0x00000040
57#define CHCR_DE 0x00000001
58#define CHCR_TE 0x00000002
59#define CHCR_IE 0x00000004
60
61#define DMAOR_COD	0x00000008
62#define DMAOR_AE	0x00000004
63#define DMAOR_NMIF	0x00000002
64#define DMAOR_DME	0x00000001
65
66struct dma_info_t {
67	unsigned int chan;
68	unsigned int mode_read;
69	unsigned int mode_write;
70	unsigned long dev_addr;
71	unsigned int mode;
72	unsigned long mem_addr;
73	unsigned int count;
74};
75
76static __inline__ void clear_dma_ff(unsigned int dmanr){}
77
78/* These are in arch/sh/kernel/dma.c: */
79extern unsigned long claim_dma_lock(void);
80extern void release_dma_lock(unsigned long flags);
81extern void setup_dma(unsigned int dmanr, struct dma_info_t *info);
82extern void enable_dma(unsigned int dmanr);
83extern void disable_dma(unsigned int dmanr);
84extern void set_dma_mode(unsigned int dmanr, char mode);
85extern void set_dma_addr(unsigned int dmanr, unsigned int a);
86extern void set_dma_count(unsigned int dmanr, unsigned int count);
87extern int get_dma_residue(unsigned int dmanr);
88
89#ifdef CONFIG_PCI
90extern int isa_dma_bridge_buggy;
91#else
92#define isa_dma_bridge_buggy 	(0)
93#endif
94
95
96#endif /* __ASM_SH_DMA_H */
97