1#ifndef _PPC64_PACA_H 2#define _PPC64_PACA_H 3 4/*============================================================================ 5 * Header File Id 6 * Name______________: paca.h 7 * 8 * Description_______: 9 * 10 * This control block defines the PACA which defines the processor 11 * specific data for each logical processor on the system. 12 * There are some pointers defined that are utilized by PLIC. 13 * 14 * C 2001 PPC 64 Team, IBM Corp 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License 18 * as published by the Free Software Foundation; either version 19 * 2 of the License, or (at your option) any later version. 20 */ 21#include <asm/types.h> 22 23#define N_EXC_STACK 2 24 25/*----------------------------------------------------------------------------- 26 * Other Includes 27 *----------------------------------------------------------------------------- 28 */ 29#include <asm/iSeries/ItLpPaca.h> 30#include <asm/iSeries/ItLpRegSave.h> 31#include <asm/iSeries/ItLpQueue.h> 32#include <asm/rtas.h> 33#include <asm/mmu.h> 34#include <asm/processor.h> 35 36/* A paca entry is required for each logical processor. On systems 37 * that support hardware multi-threading, this is equal to twice the 38 * number of physical processors. On LPAR systems, we are required 39 * to have space for the maximum number of logical processors we 40 * could ever possibly have. Currently, we are limited to allocating 41 * 24 processors to a partition which gives 48 logical processors on 42 * an HMT box. Therefore, we reserve this many paca entries. 43 */ 44#define MAX_PROCESSORS 24 45#define MAX_PACAS MAX_PROCESSORS * 2 46 47extern struct paca_struct paca[]; 48#define get_paca() ((struct paca_struct *)mfspr(SPRG3)) 49 50/*============================================================================ 51 * Name_______: paca 52 * 53 * Description: 54 * 55 * Defines the layout of the paca. 56 * 57 * This structure is not directly accessed by PLIC or the SP except 58 * for the first two pointers that point to the ItLpPaca area and the 59 * ItLpRegSave area for this processor. Both the ItLpPaca and 60 * ItLpRegSave objects are currently contained within the 61 * PACA but they do not need to be. 62 * 63 *============================================================================ 64 */ 65struct paca_struct { 66/*===================================================================================== 67 * CACHE_LINE_1 0x0000 - 0x007F 68 *===================================================================================== 69 */ 70 struct ItLpPaca *xLpPacaPtr; /* Pointer to LpPaca for PLIC 0x00 */ 71 struct ItLpRegSave *xLpRegSavePtr; /* Pointer to LpRegSave for PLIC 0x08 */ 72 u64 xCurrent; /* Pointer to current 0x10 */ 73 u16 xPacaIndex; /* Logical processor number 0x18 */ 74 u16 xHwProcNum; /* Actual Hardware Processor Number 0x1a */ 75 u32 default_decr; /* Default decrementer value 0x1c */ 76 u64 xHrdIntStack; /* Stack for hardware interrupts 0x20 */ 77 u64 xKsave; /* Saved Kernel stack addr or zero 0x28 */ 78 u64 pvr; /* Processor version register 0x30 */ 79 u8 *exception_sp; /* 0x38 */ 80 81 struct ItLpQueue *lpQueuePtr; /* LpQueue handled by this processor 0x40 */ 82 u64 xTOC; /* Kernel TOC address 0x48 */ 83 STAB xStab_data; /* Segment table information 0x50,0x58,0x60 */ 84 u8 xSegments[STAB_CACHE_SIZE]; /* Cache of used stab entries 0x68,0x70 */ 85 u8 xProcEnabled; /* 1=soft enabled 0x78 */ 86 u8 xHrdIntCount; /* Count of active hardware interrupts 0x79 */ 87 u8 resv1[6]; /* 0x7B-0x7F */ 88 89/*===================================================================================== 90 * CACHE_LINE_2 0x0080 - 0x00FF 91 *===================================================================================== 92 */ 93 u64 *pgd_cache; /* 0x00 */ 94 u64 *pmd_cache; /* 0x08 */ 95 u64 *pte_cache; /* 0x10 */ 96 u64 pgtable_cache_sz; /* 0x18 */ 97 u64 next_jiffy_update_tb; /* TB value for next jiffy update 0x20 */ 98 u32 lpEvent_count; /* lpEvents processed 0x28 */ 99 u8 rsvd2[128-5*8-1*4]; /* 0x68 */ 100 101/*===================================================================================== 102 * CACHE_LINE_3 0x0100 - 0x017F 103 *===================================================================================== 104 */ 105 u8 xProcStart; /* At startup, processor spins until 0x100 */ 106 /* xProcStart becomes non-zero. */ 107 u8 rsvd3[127]; 108 109/*===================================================================================== 110 * CACHE_LINE_4-8 0x0180 - 0x03FF Contains ItLpPaca 111 *===================================================================================== 112 */ 113 struct ItLpPaca xLpPaca; /* Space for ItLpPaca */ 114 115/*===================================================================================== 116 * CACHE_LINE_9-16 0x0400 - 0x07FF Contains ItLpRegSave 117 *===================================================================================== 118 */ 119 struct ItLpRegSave xRegSav; /* Register save for proc */ 120 121/*===================================================================================== 122 * CACHE_LINE_17-18 0x0800 - 0x0EFF Reserved 123 *===================================================================================== 124 */ 125 struct rtas_args xRtas; /* Per processor RTAS struct */ 126 u64 xR1; /* r1 save for RTAS calls */ 127 u64 xSavedMsr; /* Old msr saved here by HvCall */ 128 u8 rsvd5[256-16-sizeof(struct rtas_args)]; 129 130/*===================================================================================== 131 * CACHE_LINE_19 - 20 Profile Data 132 *===================================================================================== 133 */ 134 u32 pmc[12]; /* Default pmc value */ 135 u64 pmcc[8]; /* Cumulative pmc counts */ 136 u64 rsvd5a[2]; 137 138 u32 prof_multiplier; /* */ 139 u32 prof_shift; /* iSeries shift for profile bucket size */ 140 u32 *prof_buffer; /* iSeries profiling buffer */ 141 u32 *prof_stext; /* iSeries start of kernel text */ 142 u32 *prof_etext; /* iSeries start of kernel text */ 143 u32 prof_len; /* iSeries length of profile buffer -1 */ 144 u8 prof_mode; /* */ 145 u8 rsvv5b[3]; 146 u64 prof_counter; /* */ 147 u8 rsvd5c[128-8*6]; 148 149/*===================================================================================== 150 * CACHE_LINE_20-30 151 *===================================================================================== 152 */ 153 u8 rsvd6[0x500]; 154 155/*===================================================================================== 156 * CACHE_LINE_31 0x0F00 - 0x0F7F Exception stack 157 *===================================================================================== 158 */ 159 u8 exception_stack[N_EXC_STACK*EXC_FRAME_SIZE]; 160 161/*===================================================================================== 162 * CACHE_LINE_32 0x0F80 - 0x0FFF Reserved 163 *===================================================================================== 164 */ 165 u8 rsvd7[0x80]; /* Give the stack some rope ... */ 166 167/*===================================================================================== 168 * Page 2 Reserved for guard page. Also used as a stack early in SMP boots before 169 * relocation is enabled. 170 *===================================================================================== 171 */ 172 u8 guard[0x1000]; /* ... and then hang 'em */ 173}; 174 175#endif /* _PPC64_PACA_H */ 176