1/* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 4 * 5 * This program is free software; you can distribute it and/or modify it 6 * under the terms of the GNU General Public License (Version 2) as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 */ 18#ifndef _ASM_GT64120_H 19#define _ASM_GT64120_H 20 21#define MSK(n) ((1 << (n)) - 1) 22 23/* 24 * Register offset addresses 25 */ 26#define GT_CPU_OFS 0x000 27 28/* 29 * Interrupt Registers 30 */ 31#define GT_SCS10LD_OFS 0x008 32#define GT_SCS10HD_OFS 0x010 33#define GT_SCS32LD_OFS 0x018 34#define GT_SCS32HD_OFS 0x020 35#define GT_CS20LD_OFS 0x028 36#define GT_CS20HD_OFS 0x030 37#define GT_CS3BOOTLD_OFS 0x038 38#define GT_CS3BOOTHD_OFS 0x040 39#define GT_PCI0IOLD_OFS 0x048 40#define GT_PCI0IOHD_OFS 0x050 41#define GT_PCI0M0LD_OFS 0x058 42#define GT_PCI0M0HD_OFS 0x060 43#define GT_ISD_OFS 0x068 44#define GT_PCI0M1LD_OFS 0x080 45#define GT_PCI0M1HD_OFS 0x088 46#define GT_PCI1IOLD_OFS 0x090 47#define GT_PCI1IOHD_OFS 0x098 48#define GT_PCI1M0LD_OFS 0x0a0 49#define GT_PCI1M0HD_OFS 0x0a8 50#define GT_PCI1M1LD_OFS 0x0b0 51#define GT_PCI1M1HD_OFS 0x0b8 52 53/* 54 * GT64120A only 55 */ 56#define GT_PCI0IOREMAP_OFS 0x0f0 57#define GT_PCI0M0REMAP_OFS 0x0f8 58#define GT_PCI0M1REMAP_OFS 0x100 59#define GT_PCI1IOREMAP_OFS 0x108 60#define GT_PCI1M0REMAP_OFS 0x110 61#define GT_PCI1M1REMAP_OFS 0x118 62 63#define GT_SCS0LD_OFS 0x400 64#define GT_SCS0HD_OFS 0x404 65#define GT_SCS1LD_OFS 0x408 66#define GT_SCS1HD_OFS 0x40c 67#define GT_SCS2LD_OFS 0x410 68#define GT_SCS2HD_OFS 0x414 69#define GT_SCS3LD_OFS 0x418 70#define GT_SCS3HD_OFS 0x41c 71#define GT_CS0LD_OFS 0x420 72#define GT_CS0HD_OFS 0x424 73#define GT_CS1LD_OFS 0x428 74#define GT_CS1HD_OFS 0x42c 75#define GT_CS2LD_OFS 0x430 76#define GT_CS2HD_OFS 0x434 77#define GT_CS3LD_OFS 0x438 78#define GT_CS3HD_OFS 0x43c 79#define GT_BOOTLD_OFS 0x440 80#define GT_BOOTHD_OFS 0x444 81 82#define GT_SDRAM_B0_OFS 0x44c 83#define GT_SDRAM_CFG_OFS 0x448 84#define GT_SDRAM_B2_OFS 0x454 85#define GT_SDRAM_OPMODE_OFS 0x474 86#define GT_SDRAM_BM_OFS 0x478 87#define GT_SDRAM_ADDRDECODE_OFS 0x47c 88 89#define GT_PCI0_CMD_OFS 0xc00 /* GT64120A only */ 90#define GT_PCI0_TOR_OFS 0xc04 91#define GT_PCI0_BS_SCS10_OFS 0xc08 92#define GT_PCI0_BS_SCS32_OFS 0xc0c 93#define GT_INTRCAUSE_OFS 0xc18 94#define GT_INTRMASK_OFS 0xc1c /* GT64120A only */ 95#define GT_PCI0_IACK_OFS 0xc34 96#define GT_PCI0_BARE_OFS 0xc3c 97#define GT_HINTRCAUSE_OFS 0xc98 /* GT64120A only */ 98#define GT_HINTRMASK_OFS 0xc9c /* GT64120A only */ 99#define GT_PCI1_CFGADDR_OFS 0xcf0 /* GT64120A only */ 100#define GT_PCI1_CFGDATA_OFS 0xcf4 /* GT64120A only */ 101#define GT_PCI0_CFGADDR_OFS 0xcf8 102#define GT_PCI0_CFGDATA_OFS 0xcfc 103 104 105/* 106 * Timer/Counter. GT64120A only. 107 */ 108#define GT_TC0_OFS 0x850 109#define GT_TC1_OFS 0x854 110#define GT_TC2_OFS 0x858 111#define GT_TC3_OFS 0x85C 112#define GT_TC_CONTROL_OFS 0x864 113 114/* 115 * I2O Support Registers 116 */ 117#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 118#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 119#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 120#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c 121#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 122#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 123#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 124#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c 125#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 126#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 127#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 128#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 129#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 130#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 131#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 132#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 133#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 134#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c 135#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 136#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 137#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 138#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c 139 140#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 141#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 142#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 143#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c 144#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 145#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 146#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 147#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c 148#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 149#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 150#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 151#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 152#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 153#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 154#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 155#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 156#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 157#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c 158#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 159#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 160#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 161#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c 162 163/* 164 * Register encodings 165 */ 166#define GT_CPU_ENDIAN_SHF 12 167#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) 168#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK 169#define GT_CPU_WR_SHF 16 170#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) 171#define GT_CPU_WR_BIT GT_CPU_WR_MSK 172#define GT_CPU_WR_DXDXDXDX 0 173#define GT_CPU_WR_DDDD 1 174 175 176#define GT_CFGADDR_CFGEN_SHF 31 177#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) 178#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK 179 180#define GT_CFGADDR_BUSNUM_SHF 16 181#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) 182 183#define GT_CFGADDR_DEVNUM_SHF 11 184#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) 185 186#define GT_CFGADDR_FUNCNUM_SHF 8 187#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) 188 189#define GT_CFGADDR_REGNUM_SHF 2 190#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) 191 192 193#define GT_SDRAM_BM_ORDER_SHF 2 194#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) 195#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK 196#define GT_SDRAM_BM_ORDER_SUB 1 197#define GT_SDRAM_BM_ORDER_LIN 0 198 199#define GT_SDRAM_BM_RSVD_ALL1 0xffb 200 201 202#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 203#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) 204#define GT_SDRAM_ADDRDECODE_ADDR_0 0 205#define GT_SDRAM_ADDRDECODE_ADDR_1 1 206#define GT_SDRAM_ADDRDECODE_ADDR_2 2 207#define GT_SDRAM_ADDRDECODE_ADDR_3 3 208#define GT_SDRAM_ADDRDECODE_ADDR_4 4 209#define GT_SDRAM_ADDRDECODE_ADDR_5 5 210#define GT_SDRAM_ADDRDECODE_ADDR_6 6 211#define GT_SDRAM_ADDRDECODE_ADDR_7 7 212 213 214#define GT_SDRAM_B0_CASLAT_SHF 0 215#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) 216#define GT_SDRAM_B0_CASLAT_2 1 217#define GT_SDRAM_B0_CASLAT_3 2 218 219#define GT_SDRAM_B0_FTDIS_SHF 2 220#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) 221#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK 222 223#define GT_SDRAM_B0_SRASPRCHG_SHF 3 224#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) 225#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK 226#define GT_SDRAM_B0_SRASPRCHG_2 0 227#define GT_SDRAM_B0_SRASPRCHG_3 1 228 229#define GT_SDRAM_B0_B0COMPAB_SHF 4 230#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) 231#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK 232 233#define GT_SDRAM_B0_64BITINT_SHF 5 234#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) 235#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK 236#define GT_SDRAM_B0_64BITINT_2 0 237#define GT_SDRAM_B0_64BITINT_4 1 238 239#define GT_SDRAM_B0_BW_SHF 6 240#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) 241#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK 242#define GT_SDRAM_B0_BW_32 0 243#define GT_SDRAM_B0_BW_64 1 244 245#define GT_SDRAM_B0_BLODD_SHF 7 246#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) 247#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK 248 249#define GT_SDRAM_B0_PAR_SHF 8 250#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) 251#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK 252 253#define GT_SDRAM_B0_BYPASS_SHF 9 254#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) 255#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK 256 257#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 258#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) 259#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK 260#define GT_SDRAM_B0_SRAS2SCAS_2 0 261#define GT_SDRAM_B0_SRAS2SCAS_3 1 262 263#define GT_SDRAM_B0_SIZE_SHF 11 264#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) 265#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK 266#define GT_SDRAM_B0_SIZE_16M 0 267#define GT_SDRAM_B0_SIZE_64M 1 268 269#define GT_SDRAM_B0_EXTPAR_SHF 12 270#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) 271#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK 272 273#define GT_SDRAM_B0_BLEN_SHF 13 274#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) 275#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK 276#define GT_SDRAM_B0_BLEN_8 0 277#define GT_SDRAM_B0_BLEN_4 1 278 279 280#define GT_SDRAM_CFG_REFINT_SHF 0 281#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) 282 283#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 284#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) 285#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK 286 287#define GT_SDRAM_CFG_RMW_SHF 15 288#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) 289#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK 290 291#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 292#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) 293#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK 294 295#define GT_SDRAM_CFG_DUPCNTL_SHF 19 296#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) 297#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK 298 299#define GT_SDRAM_CFG_DUPBA_SHF 20 300#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) 301#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK 302 303#define GT_SDRAM_CFG_DUPEOT0_SHF 21 304#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) 305#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK 306 307#define GT_SDRAM_CFG_DUPEOT1_SHF 22 308#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) 309#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK 310 311#define GT_SDRAM_OPMODE_OP_SHF 0 312#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) 313#define GT_SDRAM_OPMODE_OP_NORMAL 0 314#define GT_SDRAM_OPMODE_OP_NOP 1 315#define GT_SDRAM_OPMODE_OP_PRCHG 2 316#define GT_SDRAM_OPMODE_OP_MODE 3 317#define GT_SDRAM_OPMODE_OP_CBR 4 318 319 320#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 321#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) 322#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK 323 324#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 325#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) 326#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK 327 328#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 329#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) 330#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK 331 332#define GT_PCI0_BARE_INTIODIS_SHF 3 333#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) 334#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK 335 336#define GT_PCI0_BARE_INTMEMDIS_SHF 4 337#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) 338#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK 339 340#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 341#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) 342#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK 343 344#define GT_PCI0_BARE_CS20DIS_SHF 6 345#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) 346#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK 347 348#define GT_PCI0_BARE_SCS32DIS_SHF 7 349#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) 350#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK 351 352#define GT_PCI0_BARE_SCS10DIS_SHF 8 353#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) 354#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK 355 356 357#define GT_INTRCAUSE_MASABORT0_SHF 18 358#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) 359#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK 360 361#define GT_INTRCAUSE_TARABORT0_SHF 19 362#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) 363#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK 364 365 366#define GT_PCI0_CFGADDR_REGNUM_SHF 2 367#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) 368#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 369#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) 370#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 371#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) 372#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 373#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) 374#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 375#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) 376#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK 377 378#define GT_PCI0_CMD_MBYTESWAP_SHF 0 379#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) 380#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK 381#define GT_PCI0_CMD_MWORDSWAP_SHF 10 382#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) 383#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK 384#define GT_PCI0_CMD_SBYTESWAP_SHF 16 385#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) 386#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK 387#define GT_PCI0_CMD_SWORDSWAP_SHF 11 388#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) 389#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK 390 391/* 392 * Misc 393 */ 394#define GT_DEF_BASE 0x14000000 395#define GT_DEF_PCI0_MEM0_BASE 0x12000000 396#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ 397#define GT_LATTIM_MIN 6 /* Minimum lat */ 398 399#endif /* _ASM_GT64120_H */ 400