1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle at alii 7 * Copyright (C) 1999 Silicon Graphics, Inc. 8 */ 9#ifndef _ASM_PGTABLE_H 10#define _ASM_PGTABLE_H 11 12#include <linux/config.h> 13#include <asm/addrspace.h> 14#include <asm/page.h> 15 16#include <linux/linkage.h> 17#include <asm/cachectl.h> 18#include <asm/fixmap.h> 19 20/* Cache flushing: 21 * 22 * - flush_cache_all() flushes entire cache 23 * - flush_cache_mm(mm) flushes the specified mm context's cache lines 24 * - flush_cache_page(mm, vmaddr) flushes a single page 25 * - flush_cache_range(mm, start, end) flushes a range of pages 26 * - flush_page_to_ram(page) write back kernel page to ram 27 * - flush_icache_range(start, end) flush a range of instructions 28 * 29 * - flush_cache_sigtramp() flush signal trampoline 30 * - flush_icache_all() flush the entire instruction cache 31 */ 32extern void (*_flush_cache_all)(void); 33extern void (*___flush_cache_all)(void); 34extern void (*_flush_cache_mm)(struct mm_struct *mm); 35extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start, 36 unsigned long end); 37extern void (*_flush_cache_page)(struct vm_area_struct *vma, 38 unsigned long page); 39extern void (*_flush_page_to_ram)(struct page * page); 40extern void (*_flush_icache_range)(unsigned long start, unsigned long end); 41extern void (*_flush_icache_page)(struct vm_area_struct *vma, 42 struct page *page); 43extern void (*_flush_cache_sigtramp)(unsigned long addr); 44extern void (*_flush_icache_all)(void); 45 46#define flush_dcache_page(page) do { } while (0) 47 48#define flush_cache_all() _flush_cache_all() 49#define __flush_cache_all() ___flush_cache_all() 50#define flush_cache_mm(mm) _flush_cache_mm(mm) 51#define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end) 52#define flush_cache_page(vma,page) _flush_cache_page(vma, page) 53#define flush_page_to_ram(page) _flush_page_to_ram(page) 54 55#define flush_icache_range(start, end) _flush_icache_range(start,end) 56#define flush_icache_user_range(vma, page, addr, len) \ 57 _flush_icache_page((vma), (page)) 58#define flush_icache_page(vma, page) _flush_icache_page(vma, page) 59 60#define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr) 61#ifdef CONFIG_VTAG_ICACHE 62#define flush_icache_all() _flush_icache_all() 63#else 64#define flush_icache_all() do { } while(0) 65#endif 66 67/* 68 * - add_wired_entry() add a fixed TLB entry, and move wired register 69 */ 70extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, 71 unsigned long entryhi, unsigned long pagemask); 72 73/* 74 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries 75 * starting at the top and working down. This is for populating the 76 * TLB before trap_init() puts the TLB miss handler in place. It 77 * should be used only for entries matching the actual page tables, 78 * to prevent inconsistencies. 79 */ 80extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, 81 unsigned long entryhi, unsigned long pagemask); 82 83 84/* Basically we have the same two-level (which is the logical three level 85 * Linux page table layout folded) page tables as the i386. Some day 86 * when we have proper page coloring support we can have a 1% quicker 87 * tlb refill handling mechanism, but for now it is a bit slower but 88 * works even with the cache aliasing problem the R4k and above have. 89 */ 90 91/* PMD_SHIFT determines the size of the area a second-level page table can map */ 92#ifdef CONFIG_64BIT_PHYS_ADDR 93#define PMD_SHIFT 21 94#else 95#define PMD_SHIFT 22 96#endif 97#define PMD_SIZE (1UL << PMD_SHIFT) 98#define PMD_MASK (~(PMD_SIZE-1)) 99 100/* PGDIR_SHIFT determines what a third-level page table entry can map */ 101#define PGDIR_SHIFT PMD_SHIFT 102#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 103#define PGDIR_MASK (~(PGDIR_SIZE-1)) 104 105/* 106 * Entries per page directory level: we use two-level, so 107 * we don't really have any PMD directory physically. 108 */ 109#ifdef CONFIG_64BIT_PHYS_ADDR 110#define PTRS_PER_PTE 512 111#define PTRS_PER_PMD 1 112#define PTRS_PER_PGD 2048 113#define PGD_ORDER 1 114#else 115#define PTRS_PER_PTE 1024 116#define PTRS_PER_PMD 1 117#define PTRS_PER_PGD 1024 118#define PGD_ORDER 0 119#endif 120 121#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) 122#define FIRST_USER_PGD_NR 0 123 124#define VMALLOC_START KSEG2 125#define VMALLOC_VMADDR(x) ((unsigned long)(x)) 126 127#if CONFIG_HIGHMEM 128# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) 129#else 130# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) 131#endif 132 133#include <asm/pgtable-bits.h> 134 135#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) 136#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 137 PAGE_CACHABLE_DEFAULT) 138#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 139 PAGE_CACHABLE_DEFAULT) 140#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 141 PAGE_CACHABLE_DEFAULT) 142#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ 143 _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT) 144#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 145 PAGE_CACHABLE_DEFAULT) 146#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ 147 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) 148 149/* 150 * MIPS can't do page protection for execute, and considers that the same like 151 * read. Also, write permissions imply read permissions. This is the closest 152 * we can get by reasonable means.. 153 */ 154#define __P000 PAGE_NONE 155#define __P001 PAGE_READONLY 156#define __P010 PAGE_COPY 157#define __P011 PAGE_COPY 158#define __P100 PAGE_READONLY 159#define __P101 PAGE_READONLY 160#define __P110 PAGE_COPY 161#define __P111 PAGE_COPY 162 163#define __S000 PAGE_NONE 164#define __S001 PAGE_READONLY 165#define __S010 PAGE_SHARED 166#define __S011 PAGE_SHARED 167#define __S100 PAGE_READONLY 168#define __S101 PAGE_READONLY 169#define __S110 PAGE_SHARED 170#define __S111 PAGE_SHARED 171 172#ifdef CONFIG_64BIT_PHYS_ADDR 173#define pte_ERROR(e) \ 174 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) 175#else 176#define pte_ERROR(e) \ 177 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 178#endif 179#define pmd_ERROR(e) \ 180 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 181#define pgd_ERROR(e) \ 182 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 183 184extern unsigned long empty_zero_page; 185extern unsigned long zero_page_mask; 186 187#define ZERO_PAGE(vaddr) \ 188 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) 189 190extern void load_pgd(unsigned long pg_dir); 191 192extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)]; 193 194/* 195 * Conversion functions: convert a page and protection to a page entry, 196 * and a page entry and page directory to the page they refer to. 197 */ 198static inline unsigned long pmd_page(pmd_t pmd) 199{ 200 return pmd_val(pmd); 201} 202 203static inline void pmd_set(pmd_t * pmdp, pte_t * ptep) 204{ 205 pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK); 206} 207 208static inline int pte_none(pte_t pte) { return !(pte_val(pte) & ~_PAGE_GLOBAL); } 209static inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; } 210 211/* Certain architectures need to do special things when pte's 212 * within a page table are directly modified. Thus, the following 213 * hook is made available. 214 */ 215static inline void set_pte(pte_t *ptep, pte_t pteval) 216{ 217 *ptep = pteval; 218#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) 219 if (pte_val(pteval) & _PAGE_GLOBAL) { 220 pte_t *buddy = ptep_buddy(ptep); 221 /* 222 * Make sure the buddy is global too (if it's !none, 223 * it better already be global) 224 */ 225 if (pte_none(*buddy)) 226 pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL; 227 } 228#endif 229} 230 231static inline void pte_clear(pte_t *ptep) 232{ 233#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) 234 /* Preserve global status for the pair */ 235 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) 236 set_pte(ptep, __pte(_PAGE_GLOBAL)); 237 else 238#endif 239 set_pte(ptep, __pte(0)); 240} 241 242/* 243 * (pmds are folded into pgds so this doesn't get actually called, 244 * but the define is needed for a generic inline function.) 245 */ 246#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) 247#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval) 248 249/* 250 * Empty pgd/pmd entries point to the invalid_pte_table. 251 */ 252static inline int pmd_none(pmd_t pmd) 253{ 254 return pmd_val(pmd) == (unsigned long) invalid_pte_table; 255} 256 257static inline int pmd_bad(pmd_t pmd) 258{ 259 return ((pmd_page(pmd) > (unsigned long) high_memory) || 260 (pmd_page(pmd) < PAGE_OFFSET)); 261} 262 263static inline int pmd_present(pmd_t pmd) 264{ 265 return (pmd_val(pmd) != (unsigned long) invalid_pte_table); 266} 267 268static inline void pmd_clear(pmd_t *pmdp) 269{ 270 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 271} 272 273/* 274 * The "pgd_xxx()" functions here are trivial for a folded two-level 275 * setup: the pgd is never bad, and a pmd always exists (as it's folded 276 * into the pgd entry) 277 */ 278static inline int pgd_none(pgd_t pgd) { return 0; } 279static inline int pgd_bad(pgd_t pgd) { return 0; } 280static inline int pgd_present(pgd_t pgd) { return 1; } 281static inline void pgd_clear(pgd_t *pgdp) { } 282 283/* 284 * Permanent address of a page. Obviously must never be called on a highmem 285 * page. 286 */ 287#ifdef CONFIG_CPU_VR41XX 288#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> (PAGE_SHIFT + 2)))) 289#else 290#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT))) 291#endif 292 293/* 294 * The following only work if pte_present() is true. 295 * Undefined behaviour if not.. 296 */ 297static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } 298static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } 299static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } 300static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 301 302static inline pte_t pte_wrprotect(pte_t pte) 303{ 304 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); 305 return pte; 306} 307 308static inline pte_t pte_rdprotect(pte_t pte) 309{ 310 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); 311 return pte; 312} 313 314static inline pte_t pte_mkclean(pte_t pte) 315{ 316 pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); 317 return pte; 318} 319 320static inline pte_t pte_mkold(pte_t pte) 321{ 322 pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); 323 return pte; 324} 325 326static inline pte_t pte_mkwrite(pte_t pte) 327{ 328 pte_val(pte) |= _PAGE_WRITE; 329 if (pte_val(pte) & _PAGE_MODIFIED) 330 pte_val(pte) |= _PAGE_SILENT_WRITE; 331 return pte; 332} 333 334static inline pte_t pte_mkread(pte_t pte) 335{ 336 pte_val(pte) |= _PAGE_READ; 337 if (pte_val(pte) & _PAGE_ACCESSED) 338 pte_val(pte) |= _PAGE_SILENT_READ; 339 return pte; 340} 341 342static inline pte_t pte_mkdirty(pte_t pte) 343{ 344 pte_val(pte) |= _PAGE_MODIFIED; 345 if (pte_val(pte) & _PAGE_WRITE) 346 pte_val(pte) |= _PAGE_SILENT_WRITE; 347 return pte; 348} 349 350/* 351 * Macro to make mark a page protection value as "uncacheable". Note 352 * that "protection" is really a misnomer here as the protection value 353 * contains the memory attribute bits, dirty bits, and various other 354 * bits as well. 355 */ 356#define pgprot_noncached pgprot_noncached 357 358static inline pgprot_t pgprot_noncached(pgprot_t _prot) 359{ 360 unsigned long prot = pgprot_val(_prot); 361 362 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; 363 364 return __pgprot(prot); 365} 366 367static inline pte_t pte_mkyoung(pte_t pte) 368{ 369 pte_val(pte) |= _PAGE_ACCESSED; 370 if (pte_val(pte) & _PAGE_READ) 371 pte_val(pte) |= _PAGE_SILENT_READ; 372 return pte; 373} 374 375/* 376 * Conversion functions: convert a page and protection to a page entry, 377 * and a page entry and page directory to the page they refer to. 378 */ 379 380#ifdef CONFIG_CPU_VR41XX 381#define mk_pte(page, pgprot) \ 382({ \ 383 pte_t __pte; \ 384 \ 385 pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT + 2)) | \ 386 pgprot_val(pgprot); \ 387 \ 388 __pte; \ 389}) 390#else 391#define mk_pte(page, pgprot) \ 392({ \ 393 pte_t __pte; \ 394 \ 395 pte_val(__pte) = ((phys_t)(page - mem_map) << PAGE_SHIFT) | \ 396 pgprot_val(pgprot); \ 397 \ 398 __pte; \ 399}) 400#endif 401 402static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot) 403{ 404#ifdef CONFIG_CPU_VR41XX 405 return __pte((physpage << 2) | pgprot_val(pgprot)); 406#else 407 return __pte(physpage | pgprot_val(pgprot)); 408#endif 409} 410 411static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 412{ 413 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 414} 415 416#define page_pte(page) page_pte_prot(page, __pgprot(0)) 417 418#define __pgd_offset(address) pgd_index(address) 419#define __pmd_offset(address) \ 420 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 421 422/* to find an entry in a kernel page-table-directory */ 423#define pgd_offset_k(address) pgd_offset(&init_mm, address) 424 425#define pgd_index(address) ((address) >> PGDIR_SHIFT) 426 427/* to find an entry in a page-table-directory */ 428static inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address) 429{ 430 return mm->pgd + pgd_index(address); 431} 432 433/* Find an entry in the second-level page table.. */ 434static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) 435{ 436 return (pmd_t *) dir; 437} 438 439/* Find an entry in the third-level page table.. */ 440static inline pte_t *pte_offset(pmd_t * dir, unsigned long address) 441{ 442 return (pte_t *) (pmd_page(*dir)) + 443 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); 444} 445 446extern int do_check_pgt_cache(int, int); 447 448extern pgd_t swapper_pg_dir[1024]; 449extern void paging_init(void); 450 451extern void update_mmu_cache(struct vm_area_struct *vma, 452 unsigned long address, pte_t pte); 453 454/* Swap entries must have VALID and GLOBAL bits cleared. */ 455#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 456 457#define SWP_TYPE(x) (((x).val >> 1) & 0x7f) 458#define SWP_OFFSET(x) ((x).val >> 10) 459#define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 10) }) 460#else 461 462#define SWP_TYPE(x) (((x).val >> 1) & 0x1f) 463#define SWP_OFFSET(x) ((x).val >> 8) 464#define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) }) 465#endif 466 467#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 468#define swp_entry_to_pte(x) ((pte_t) { (x).val }) 469 470 471/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 472#define PageSkip(page) (0) 473#define kern_addr_valid(addr) (1) 474 475#include <asm-generic/pgtable.h> 476 477/* 478 * We provide our own get_unmapped area to cope with the virtual aliasing 479 * constraints placed on us by the cache architecture. 480 */ 481#define HAVE_ARCH_UNMAPPED_AREA 482 483#define io_remap_page_range remap_page_range 484 485/* 486 * No page table caches to initialise 487 */ 488#define pgtable_cache_init() do { } while (0) 489 490#endif /* _ASM_PGTABLE_H */ 491