1/* 2 * Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2000-2001 Toshiba Corporation 9 */ 10#ifndef __ASM_TX3927_JMR3927_H 11#define __ASM_TX3927_JMR3927_H 12 13#include <asm/jmr3927/tx3927.h> 14#include <asm/addrspace.h> 15#include <asm/jmr3927/irq.h> 16#ifndef __ASSEMBLY__ 17#include <asm/system.h> 18#endif 19 20/* CS */ 21#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ 22#define JMR3927_ROMCE1 0x1e000000 /* 4M */ 23#define JMR3927_ROMCE2 0x14000000 /* 16M */ 24#define JMR3927_ROMCE3 0x10000000 /* 64M */ 25#define JMR3927_ROMCE5 0x1d000000 /* 4M */ 26#define JMR3927_SDCS0 0x00000000 /* 32M */ 27#define JMR3927_SDCS1 0x02000000 /* 32M */ 28/* PCI Direct Mappings */ 29 30#define JMR3927_PCIMEM 0x08000000 31#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ 32#define JMR3927_PCIIO 0x15000000 33#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ 34 35#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ 36#define JMR3927_PORT_BASE KSEG1 37 38/* select indirect initiator access per errata */ 39#define JMR3927_INIT_INDIRECT_PCI 40#define PCI_ISTAT_IDICC 0x1000 41#define PCI_IPCIBE_IBE_LONG 0 42#define PCI_IPCIBE_ICMD_IOREAD 2 43#define PCI_IPCIBE_ICMD_IOWRITE 3 44#define PCI_IPCIBE_ICMD_MEMREAD 6 45#define PCI_IPCIBE_ICMD_MEMWRITE 7 46#define PCI_IPCIBE_ICMD_SHIFT 4 47 48/* Address map (virtual address) */ 49#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) 50#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) 51#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) 52#define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3) 53#define JMR3927_ISAMEM_BASE (JMR3927_IOB_BASE) 54#define JMR3927_ISAIO_BASE (JMR3927_IOB_BASE + 0x01000000) 55#define JMR3927_ISAC_BASE (JMR3927_IOB_BASE + 0x02000000) 56#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000) 57#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000) 58#define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5) 59#define JMR3927_PREMIER3_BASE (JMR3927_JMY1394_BASE + 0x00100000) 60#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) 61#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) 62 63#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) 64#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) 65#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) 66#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) 67#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) 68#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) 69#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) 70#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) 71#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) 72#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) 73#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) 74 75#define JMR3927_ISAC_REV_ADDR (JMR3927_ISAC_BASE + 0x00000000) 76#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000) 77#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000) 78#define JMR3927_ISAC_NMI_ADDR (JMR3927_ISAC_BASE + 0x00400000) 79#define JMR3927_ISAC_LED_ADDR (JMR3927_ISAC_BASE + 0x00500000) 80#define JMR3927_ISAC_INTP_ADDR (JMR3927_ISAC_BASE + 0x00800000) 81#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000) 82#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000) 83#define JMR3927_ISAC_INTM_ADDR (JMR3927_ISAC_BASE + 0x00b00000) 84 85/* Flash ROM */ 86#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) 87#define JMR3927_FLASH_SIZE 0x00400000 88 89/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */ 90#define JMR3927_IDT_MASK 0xfc 91#define JMR3927_REV_MASK 0x03 92#define JMR3927_IOC_IDT 0xe0 93#define JMR3927_ISAC_IDT 0x20 94 95/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ 96#define JMR3927_IOC_INTB_PCIA 0 97#define JMR3927_IOC_INTB_PCIB 1 98#define JMR3927_IOC_INTB_PCIC 2 99#define JMR3927_IOC_INTB_PCID 3 100#define JMR3927_IOC_INTB_MODEM 4 101#define JMR3927_IOC_INTB_INT6 5 102#define JMR3927_IOC_INTB_INT7 6 103#define JMR3927_IOC_INTB_SOFT 7 104#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) 105#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) 106#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) 107#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) 108#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) 109#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) 110#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) 111#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) 112 113/* bits for IOC_RESET (high byte) */ 114#define JMR3927_IOC_RESET_CPU 1 115#define JMR3927_IOC_RESET_PCI 2 116 117/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */ 118#define JMR3927_ISAC_EINTB_IOCHK 2 119#define JMR3927_ISAC_EINTB_BWTH 4 120#define JMR3927_ISAC_EINTF_IOCHK (1 << JMR3927_ISAC_EINTB_IOCHK) 121#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH) 122 123/* bits for ISAC_LED (high byte) */ 124#define JMR3927_ISAC_LED_ISALED 0x01 125#define JMR3927_ISAC_LED_USRLED 0x02 126 127/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */ 128#define JMR3927_ISAC_INTB_IRQ5 0 129#define JMR3927_ISAC_INTB_IRQKB 1 130#define JMR3927_ISAC_INTB_IRQMOUSE 2 131#define JMR3927_ISAC_INTB_IRQ4 3 132#define JMR3927_ISAC_INTB_IRQ12 4 133#define JMR3927_ISAC_INTB_IRQ3 5 134#define JMR3927_ISAC_INTB_IRQ10 6 135#define JMR3927_ISAC_INTB_ISAER 7 136#define JMR3927_ISAC_INTF_IRQ5 (1 << JMR3927_ISAC_INTB_IRQ5) 137#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB) 138#define JMR3927_ISAC_INTF_IRQMOUSE (1 << JMR3927_ISAC_INTB_IRQMOUSE) 139#define JMR3927_ISAC_INTF_IRQ4 (1 << JMR3927_ISAC_INTB_IRQ4) 140#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12) 141#define JMR3927_ISAC_INTF_IRQ3 (1 << JMR3927_ISAC_INTB_IRQ3) 142#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10) 143#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER) 144 145#ifndef __ASSEMBLY__ 146 147#if defined(__BIG_ENDIAN) 148#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) 149#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) 150#elif defined(__LITTLE_ENDIAN) 151#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) 152#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) 153#else 154#error "No Endian" 155#endif 156#define jmr3927_isac_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) 157#define jmr3927_isac_reg_in(a) (*(volatile unsigned char *)(a)) 158 159extern inline int jmr3927_have_isac(void) 160{ 161 unsigned char idt; 162 unsigned long flags; 163 unsigned long romcr3; 164 save_and_cli(flags); 165 romcr3 = tx3927_romcptr->cr[3]; 166 tx3927_romcptr->cr[3] &= 0xffffefff; /* do not wait infinitely */ 167 idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK; 168 tx3927_romcptr->cr[3] = romcr3; 169 restore_flags(flags); 170 return idt == JMR3927_ISAC_IDT; 171} 172#define jmr3927_have_nvram() \ 173 ((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT) 174 175/* NVRAM macro */ 176#define jmr3927_nvram_in(ofs) \ 177 jmr3927_ioc_reg_in(JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1)) 178#define jmr3927_nvram_out(d, ofs) \ 179 jmr3927_ioc_reg_out(d, JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1)) 180 181/* LED macro */ 182#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) 183#define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR) 184 185#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) 186 187/* DIPSW4 macro */ 188#define jmr3927_dipsw1() ((tx3927_pioptr->din & (1 << 11)) == 0) 189#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0) 190#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) 191#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) 192#define jmr3927_io_dipsw() (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4) 193 194 195#endif /* !__ASSEMBLY__ */ 196 197/* 198 * UART defines for serial.h 199 */ 200 201/* use Pre-scaler T0 (1/2) */ 202#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16) 203 204#define UART0_ADDR 0xfffef300 205#define UART1_ADDR 0xfffef400 206#define UART0_INT JMR3927_IRQ_IRC_SIO0 207#define UART1_INT JMR3927_IRQ_IRC_SIO1 208#define UART0_FLAGS ASYNC_BOOT_AUTOCONF 209#define UART1_FLAGS 0 210 211/* 212 * IRQ mappings 213 */ 214 215/* These are the virtual IRQ numbers, we divide all IRQ's into 216 * 'spaces', the 'space' determines where and how to enable/disable 217 * that particular IRQ on an JMR machine. Add new 'spaces' as new 218 * IRQ hardware is supported. 219 */ 220#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ 221#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ 222#define JMR3927_NR_IRQ_ISAC 8 /* ISA */ 223 224 225#define JMR3927_IRQ_IRC NR_ISA_IRQS 226#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) 227#define JMR3927_IRQ_ISAC (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) 228#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC) 229#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC) 230#define JMR3927_IRQ_IS_IOC(irq) (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC) 231#define JMR3927_IRQ_IS_ISAC(irq) (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END) 232 233#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) 234#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) 235#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) 236#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) 237#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) 238#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) 239#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) 240#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) 241#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) 242#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) 243#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) 244#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) 245#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0) 246#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1) 247#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2) 248#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) 249#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) 250#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) 251#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) 252#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) 253#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) 254#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) 255#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) 256#define JMR3927_IRQ_ISAC_IRQ5 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5) 257#define JMR3927_IRQ_ISAC_IRQKB (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB) 258#define JMR3927_IRQ_ISAC_IRQMOUSE (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE) 259#define JMR3927_IRQ_ISAC_IRQ4 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4) 260#define JMR3927_IRQ_ISAC_IRQ12 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12) 261#define JMR3927_IRQ_ISAC_IRQ3 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3) 262#define JMR3927_IRQ_ISAC_IRQ10 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10) 263#define JMR3927_IRQ_ISAC_ISAER (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER) 264 265/* IOC (PCI, MODEM) */ 266#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 267/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */ 268#define JMR3927_IRQ_ISACINT JMR3927_IRQ_IRC_INT2 269/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ 270#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 271/* Clock Tick (10ms) */ 272#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0 273#define JMR3927_IRQ_IDE JMR3927_IRQ_ISAC_IRQ12 274 275/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */ 276#define JMR3927_IRQ_PREMIER3 JMR3927_IRQ_IRC_INT0 277 278/* I/O Ports */ 279/* RTL8019AS 10M Ether */ 280#define JMR3927_ETHER1_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280) 281#define JMR3927_KBD_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060) 282#define JMR3927_IDE_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0) 283 284/* Clocks */ 285#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 286#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ 287#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ 288 289#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */ 290 291 292/* 293 * TX3927 Pin Configuration: 294 * 295 * PCFG bits Avail Dead 296 * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] 297 * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] 298 * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, 299 * GDBGE* PIO[2:1] 300 * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] 301 * SELTMR[2:0]:000 TIMER[1:0] 302 * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], 303 * DMAREQ[1],DMAACK[1] 304 * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] 305 * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] 306 * SELDONE:1 DMADONE PIO[7] 307 * 308 * Usable pins are: 309 * RXD[1;0],TXD[1:0],CTS[0],RTS[0], 310 * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] 311 * INT[3:0] 312 */ 313 314#endif /* __ASM_TX3927_JMR3927_H */ 315