1/*
2 *
3 */
4#ifndef _MIPS_EV96100_H
5#define _MIPS_EV96100_H
6
7#include <asm/addrspace.h>
8
9/*
10 *   GT64120 config space base address
11 */
12#define GT64120_BASE    (KSEG1ADDR(0x14000000))
13#define MIPS_GT_BASE    GT64120_BASE
14
15/*
16 *   PCI Bus allocation
17 */
18#define GT_PCI_MEM_BASE    0x12000000
19#define GT_PCI_MEM_SIZE    0x02000000
20#define GT_PCI_IO_BASE     0x10000000
21#define GT_PCI_IO_SIZE     0x02000000
22#define GT_ISA_IO_BASE     PCI_IO_BASE
23
24/*
25 *   Duart I/O ports.
26 */
27#define EV96100_COM1_BASE_ADDR  (0xBD000000 + 0x20)
28#define EV96100_COM2_BASE_ADDR  (0xBD000000 + 0x00)
29
30
31/*
32 *   EV96100 interrupt controller register base.
33 */
34#define EV96100_ICTRL_REGS_BASE   (KSEG1ADDR(0x1f000000))
35
36/*
37 *   EV96100 UART register base.
38 */
39#define EV96100_UART0_REGS_BASE    EV96100_COM1_BASE_ADDR
40#define EV96100_UART1_REGS_BASE    EV96100_COM2_BASE_ADDR
41#define EV96100_BASE_BAUD ( 3686400 / 16 )
42
43
44/*
45 * Because of an error/peculiarity in the Galileo chip, we need to swap the
46 * bytes when running bigendian.
47 */
48
49#define GT_WRITE(ofs, data)  \
50             *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
51#define GT_READ(ofs, data)   \
52             data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
53
54
55#endif /* !(_MIPS_EV96100_H) */
56