1/* 2 * BRIEF MODULE DESCRIPTION 3 * Defines for using and allocating dma channels on the Alchemy 4 * Au1000 mips processor. 5 * 6 * Copyright 2000 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. 8 * stevel@mvista.com or source@mvista.com 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * You should have received a copy of the GNU General Public License along 27 * with this program; if not, write to the Free Software Foundation, Inc., 28 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 30 */ 31#ifndef __ASM_AU1000_DMA_H 32#define __ASM_AU1000_DMA_H 33 34#include <linux/config.h> 35#include <asm/io.h> /* need byte IO */ 36#include <linux/spinlock.h> /* And spinlocks */ 37#include <linux/delay.h> 38#include <asm/system.h> 39 40#define NUM_AU1000_DMA_CHANNELS 8 41 42/* DMA Channel Base Addresses */ 43#define DMA_CHANNEL_BASE 0xB4002000 44#define DMA_CHANNEL_LEN 0x00000100 45 46/* DMA Channel Register Offsets */ 47#define DMA_MODE_SET 0x00000000 48#define DMA_MODE_READ DMA_MODE_SET 49#define DMA_MODE_CLEAR 0x00000004 50/* DMA Mode register bits follow */ 51#define DMA_DAH_MASK (0x0f << 20) 52#define DMA_DID_BIT 16 53#define DMA_DID_MASK (0x0f << DMA_DID_BIT) 54#define DMA_BE (1<<13) 55#define DMA_DR (1<<12) 56#define DMA_TS8 (1<<11) 57#define DMA_DW_BIT 9 58#define DMA_DW_MASK (0x03 << DMA_DW_BIT) 59#define DMA_DW8 (0 << DMA_DW_BIT) 60#define DMA_DW16 (1 << DMA_DW_BIT) 61#define DMA_DW32 (2 << DMA_DW_BIT) 62#define DMA_NC (1<<8) 63#define DMA_IE (1<<7) 64#define DMA_HALT (1<<6) 65#define DMA_GO (1<<5) 66#define DMA_AB (1<<4) 67#define DMA_D1 (1<<3) 68#define DMA_BE1 (1<<2) 69#define DMA_D0 (1<<1) 70#define DMA_BE0 (1<<0) 71 72#define DMA_PERIPHERAL_ADDR 0x00000008 73#define DMA_BUFFER0_START 0x0000000C 74#define DMA_BUFFER1_START 0x00000014 75#define DMA_BUFFER0_COUNT 0x00000010 76#define DMA_BUFFER1_COUNT 0x00000018 77#define DMA_BAH_BIT 16 78#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT) 79#define DMA_COUNT_BIT 0 80#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT) 81 82/* DMA Device ID's follow */ 83enum { 84 DMA_ID_UART0_TX = 0, 85 DMA_ID_UART0_RX, 86 DMA_ID_GP04, 87 DMA_ID_GP05, 88 DMA_ID_AC97C_TX, 89 DMA_ID_AC97C_RX, 90 DMA_ID_UART3_TX, 91 DMA_ID_UART3_RX, 92 DMA_ID_USBDEV_EP0_RX, 93 DMA_ID_USBDEV_EP0_TX, 94 DMA_ID_USBDEV_EP2_TX, 95 DMA_ID_USBDEV_EP3_TX, 96 DMA_ID_USBDEV_EP4_RX, 97 DMA_ID_USBDEV_EP5_RX, 98 DMA_ID_I2S_TX, 99 DMA_ID_I2S_RX, 100 DMA_NUM_DEV 101}; 102 103struct dma_chan { 104 int dev_id; // this channel is allocated if >=0, free otherwise 105 unsigned int io; 106 const char *dev_str; 107 int irq; 108 void *irq_dev; 109 unsigned int fifo_addr; 110 unsigned int mode; 111}; 112 113/* These are in arch/mips/au1000/common/dma.c */ 114extern struct dma_chan au1000_dma_table[]; 115extern int request_au1000_dma(int dev_id, 116 const char *dev_str, 117 void (*irqhandler)(int, void *, 118 struct pt_regs *), 119 unsigned long irqflags, 120 void *irq_dev_id); 121extern void free_au1000_dma(unsigned int dmanr); 122extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos, 123 int length, int *eof, void *data); 124extern void dump_au1000_dma_channel(unsigned int dmanr); 125extern spinlock_t au1000_dma_spin_lock; 126 127 128static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr) 129{ 130 if (dmanr > NUM_AU1000_DMA_CHANNELS 131 || au1000_dma_table[dmanr].dev_id < 0) 132 return NULL; 133 return &au1000_dma_table[dmanr]; 134} 135 136static __inline__ unsigned long claim_dma_lock(void) 137{ 138 unsigned long flags; 139 spin_lock_irqsave(&au1000_dma_spin_lock, flags); 140 return flags; 141} 142 143static __inline__ void release_dma_lock(unsigned long flags) 144{ 145 spin_unlock_irqrestore(&au1000_dma_spin_lock, flags); 146} 147 148/* 149 * Set the DMA buffer enable bits in the mode register. 150 */ 151static __inline__ void enable_dma_buffer0(unsigned int dmanr) 152{ 153 struct dma_chan *chan = get_dma_chan(dmanr); 154 if (!chan) 155 return; 156 au_writel(DMA_BE0, chan->io + DMA_MODE_SET); 157} 158static __inline__ void enable_dma_buffer1(unsigned int dmanr) 159{ 160 struct dma_chan *chan = get_dma_chan(dmanr); 161 if (!chan) 162 return; 163 au_writel(DMA_BE1, chan->io + DMA_MODE_SET); 164} 165static __inline__ void enable_dma_buffers(unsigned int dmanr) 166{ 167 struct dma_chan *chan = get_dma_chan(dmanr); 168 if (!chan) 169 return; 170 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); 171} 172 173static __inline__ void start_dma(unsigned int dmanr) 174{ 175 struct dma_chan *chan = get_dma_chan(dmanr); 176 if (!chan) 177 return; 178 179 au_writel(DMA_GO, chan->io + DMA_MODE_SET); 180} 181 182#define DMA_HALT_POLL 0x5000 183 184static __inline__ void halt_dma(unsigned int dmanr) 185{ 186 struct dma_chan *chan = get_dma_chan(dmanr); 187 int i; 188 if (!chan) 189 return; 190 191 au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); 192 // poll the halt bit 193 for (i = 0; i < DMA_HALT_POLL; i++) 194 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) 195 break; 196 if (i == DMA_HALT_POLL) 197 printk(KERN_INFO "halt_dma: HALT poll expired!\n"); 198} 199 200 201static __inline__ void disable_dma(unsigned int dmanr) 202{ 203 struct dma_chan *chan = get_dma_chan(dmanr); 204 if (!chan) 205 return; 206 207 halt_dma(dmanr); 208 209 // now we can disable the buffers 210 au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); 211} 212 213static __inline__ int dma_halted(unsigned int dmanr) 214{ 215 struct dma_chan *chan = get_dma_chan(dmanr); 216 if (!chan) 217 return 1; 218 return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; 219} 220 221/* initialize a DMA channel */ 222static __inline__ void init_dma(unsigned int dmanr) 223{ 224 struct dma_chan *chan = get_dma_chan(dmanr); 225 u32 mode; 226 if (!chan) 227 return; 228 229 disable_dma(dmanr); 230 231 // set device FIFO address 232 au_writel(PHYSADDR(chan->fifo_addr), 233 chan->io + DMA_PERIPHERAL_ADDR); 234 235 mode = chan->mode | (chan->dev_id << DMA_DID_BIT); 236 if (chan->irq) 237 mode |= DMA_IE; 238 239 au_writel(~mode, chan->io + DMA_MODE_CLEAR); 240 au_writel(mode, chan->io + DMA_MODE_SET); 241} 242 243/* 244 * set mode for a specific DMA channel 245 */ 246static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode) 247{ 248 struct dma_chan *chan = get_dma_chan(dmanr); 249 if (!chan) 250 return; 251 /* 252 * set_dma_mode is only allowed to change endianess, direction, 253 * transfer size, device FIFO width, and coherency settings. 254 * Make sure anything else is masked off. 255 */ 256 mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC); 257 chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC); 258 chan->mode |= mode; 259} 260 261static __inline__ unsigned int get_dma_mode(unsigned int dmanr) 262{ 263 struct dma_chan *chan = get_dma_chan(dmanr); 264 if (!chan) 265 return 0; 266 return chan->mode; 267} 268 269static __inline__ int get_dma_active_buffer(unsigned int dmanr) 270{ 271 struct dma_chan *chan = get_dma_chan(dmanr); 272 if (!chan) 273 return -1; 274 return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; 275} 276 277 278/* 279 * set the device FIFO address for a specific DMA channel - only 280 * applicable to GPO4 and GPO5. All the other devices have fixed 281 * FIFO addresses. 282 */ 283static __inline__ void set_dma_fifo_addr(unsigned int dmanr, 284 unsigned int a) 285{ 286 struct dma_chan *chan = get_dma_chan(dmanr); 287 if (!chan) 288 return; 289 290 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) 291 return; 292 293 au_writel(PHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); 294} 295 296/* 297 * Clear the DMA buffer done bits in the mode register. 298 */ 299static __inline__ void clear_dma_done0(unsigned int dmanr) 300{ 301 struct dma_chan *chan = get_dma_chan(dmanr); 302 if (!chan) 303 return; 304 au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); 305} 306static __inline__ void clear_dma_done1(unsigned int dmanr) 307{ 308 struct dma_chan *chan = get_dma_chan(dmanr); 309 if (!chan) 310 return; 311 au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); 312} 313 314/* 315 * This does nothing - not applicable to Au1000 DMA. 316 */ 317static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) 318{ 319} 320 321/* 322 * Set Buffer 0 transfer address for specific DMA channel. 323 */ 324static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a) 325{ 326 struct dma_chan *chan = get_dma_chan(dmanr); 327 if (!chan) 328 return; 329 au_writel(a, chan->io + DMA_BUFFER0_START); 330} 331 332/* 333 * Set Buffer 1 transfer address for specific DMA channel. 334 */ 335static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a) 336{ 337 struct dma_chan *chan = get_dma_chan(dmanr); 338 if (!chan) 339 return; 340 au_writel(a, chan->io + DMA_BUFFER1_START); 341} 342 343 344/* 345 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel. 346 */ 347static __inline__ void set_dma_count0(unsigned int dmanr, 348 unsigned int count) 349{ 350 struct dma_chan *chan = get_dma_chan(dmanr); 351 if (!chan) 352 return; 353 count &= DMA_COUNT_MASK; 354 au_writel(count, chan->io + DMA_BUFFER0_COUNT); 355} 356 357/* 358 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel. 359 */ 360static __inline__ void set_dma_count1(unsigned int dmanr, 361 unsigned int count) 362{ 363 struct dma_chan *chan = get_dma_chan(dmanr); 364 if (!chan) 365 return; 366 count &= DMA_COUNT_MASK; 367 au_writel(count, chan->io + DMA_BUFFER1_COUNT); 368} 369 370/* 371 * Set both buffer transfer sizes (max 64k) for a specific DMA channel. 372 */ 373static __inline__ void set_dma_count(unsigned int dmanr, 374 unsigned int count) 375{ 376 struct dma_chan *chan = get_dma_chan(dmanr); 377 if (!chan) 378 return; 379 count &= DMA_COUNT_MASK; 380 au_writel(count, chan->io + DMA_BUFFER0_COUNT); 381 au_writel(count, chan->io + DMA_BUFFER1_COUNT); 382} 383 384/* 385 * Returns which buffer has its done bit set in the mode register. 386 * Returns -1 if neither or both done bits set. 387 */ 388static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr) 389{ 390 struct dma_chan *chan = get_dma_chan(dmanr); 391 if (!chan) 392 return 0; 393 394 return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1); 395} 396 397 398/* 399 * Returns the DMA channel's Buffer Done IRQ number. 400 */ 401static __inline__ int get_dma_done_irq(unsigned int dmanr) 402{ 403 struct dma_chan *chan = get_dma_chan(dmanr); 404 if (!chan) 405 return -1; 406 407 return chan->irq; 408} 409 410/* 411 * Get DMA residue count. Returns the number of _bytes_ left to transfer. 412 */ 413static __inline__ int get_dma_residue(unsigned int dmanr) 414{ 415 int curBufCntReg, count; 416 struct dma_chan *chan = get_dma_chan(dmanr); 417 if (!chan) 418 return 0; 419 420 curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 421 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT; 422 423 count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK; 424 425 if ((chan->mode & DMA_DW_MASK) == DMA_DW16) 426 count <<= 1; 427 else if ((chan->mode & DMA_DW_MASK) == DMA_DW32) 428 count <<= 2; 429 430 return count; 431} 432 433#endif /* __ASM_AU1000_DMA_H */ 434