1/* $Id: hubio.h,v 1.1.1.1 2008/10/15 03:29:03 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. 8 */ 9 10/************************************************************************ 11 * * 12 * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * 13 * * 14 * This file is created by an automated script. Any (minimal) changes * 15 * made manually to this file should be made with care. * 16 * * 17 * MAKE ALL ADDITIONS TO THE END OF THIS FILE * 18 * * 19 ************************************************************************/ 20 21 22#ifndef _ASM_IA64_SN_SN1_HUBIO_H 23#define _ASM_IA64_SN_SN1_HUBIO_H 24 25 26#define IIO_WID 0x00400000 /* 27 * Crosstalk Widget 28 * Identification This 29 * register is also 30 * accessible from 31 * Crosstalk at 32 * address 0x0. 33 */ 34 35 36 37#define IIO_WSTAT 0x00400008 /* 38 * Crosstalk Widget 39 * Status 40 */ 41 42 43 44#define IIO_WCR 0x00400020 /* 45 * Crosstalk Widget 46 * Control Register 47 */ 48 49 50 51#define IIO_ILAPR 0x00400100 /* 52 * IO Local Access 53 * Protection Register 54 */ 55 56 57 58#define IIO_ILAPO 0x00400108 /* 59 * IO Local Access 60 * Protection Override 61 */ 62 63 64 65#define IIO_IOWA 0x00400110 /* 66 * IO Outbound Widget 67 * Access 68 */ 69 70 71 72#define IIO_IIWA 0x00400118 /* 73 * IO Inbound Widget 74 * Access 75 */ 76 77 78 79#define IIO_IIDEM 0x00400120 /* 80 * IO Inbound Device 81 * Error Mask 82 */ 83 84 85 86#define IIO_ILCSR 0x00400128 /* 87 * IO LLP Control and 88 * Status Register 89 */ 90 91 92 93#define IIO_ILLR 0x00400130 /* IO LLP Log Register */ 94 95 96 97#define IIO_IIDSR 0x00400138 /* 98 * IO Interrupt 99 * Destination 100 */ 101 102 103 104#define IIO_IGFX0 0x00400140 /* 105 * IO Graphics 106 * Node-Widget Map 0 107 */ 108 109 110 111#define IIO_IGFX1 0x00400148 /* 112 * IO Graphics 113 * Node-Widget Map 1 114 */ 115 116 117 118#define IIO_ISCR0 0x00400150 /* 119 * IO Scratch Register 120 * 0 121 */ 122 123 124 125#define IIO_ISCR1 0x00400158 /* 126 * IO Scratch Register 127 * 1 128 */ 129 130 131 132#define IIO_ITTE1 0x00400160 /* 133 * IO Translation 134 * Table Entry 1 135 */ 136 137 138 139#define IIO_ITTE2 0x00400168 /* 140 * IO Translation 141 * Table Entry 2 142 */ 143 144 145 146#define IIO_ITTE3 0x00400170 /* 147 * IO Translation 148 * Table Entry 3 149 */ 150 151 152 153#define IIO_ITTE4 0x00400178 /* 154 * IO Translation 155 * Table Entry 4 156 */ 157 158 159 160#define IIO_ITTE5 0x00400180 /* 161 * IO Translation 162 * Table Entry 5 163 */ 164 165 166 167#define IIO_ITTE6 0x00400188 /* 168 * IO Translation 169 * Table Entry 6 170 */ 171 172 173 174#define IIO_ITTE7 0x00400190 /* 175 * IO Translation 176 * Table Entry 7 177 */ 178 179 180 181#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ 182 183 184 185#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ 186 187 188 189#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ 190 191 192 193#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ 194 195 196 197#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ 198 199 200 201#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ 202 203 204 205#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ 206 207 208 209#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ 210 211 212 213#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ 214 215 216 217#define IIO_IXCC 0x004001E0 /* 218 * IO Crosstalk Credit 219 * Count Timeout 220 */ 221 222 223 224#define IIO_IMEM 0x004001E8 /* 225 * IO Miscellaneous 226 * Error Mask 227 */ 228 229 230 231#define IIO_IXTT 0x004001F0 /* 232 * IO Crosstalk 233 * Timeout Threshold 234 */ 235 236 237 238#define IIO_IECLR 0x004001F8 /* 239 * IO Error Clear 240 * Register 241 */ 242 243 244 245#define IIO_IBCR 0x00400200 /* 246 * IO BTE Control 247 * Register 248 */ 249 250 251 252#define IIO_IXSM 0x00400208 /* 253 * IO Crosstalk 254 * Spurious Message 255 */ 256 257 258 259#define IIO_IXSS 0x00400210 /* 260 * IO Crosstalk 261 * Spurious Sideband 262 */ 263 264 265 266#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ 267 268 269 270#define IIO_IIEPH1 0x00400220 /* 271 * IO Incoming Error 272 * Packet Header, Part 273 * 1 274 */ 275 276 277 278#define IIO_IIEPH2 0x00400228 /* 279 * IO Incoming Error 280 * Packet Header, Part 281 * 2 282 */ 283 284 285 286#define IIO_IPCA 0x00400300 /* 287 * IO PRB Counter 288 * Adjust 289 */ 290 291 292 293#define IIO_IPRTE0 0x00400308 /* 294 * IO PIO Read Address 295 * Table Entry 0 296 */ 297 298 299 300#define IIO_IPRTE1 0x00400310 /* 301 * IO PIO Read Address 302 * Table Entry 1 303 */ 304 305 306 307#define IIO_IPRTE2 0x00400318 /* 308 * IO PIO Read Address 309 * Table Entry 2 310 */ 311 312 313 314#define IIO_IPRTE3 0x00400320 /* 315 * IO PIO Read Address 316 * Table Entry 3 317 */ 318 319 320 321#define IIO_IPRTE4 0x00400328 /* 322 * IO PIO Read Address 323 * Table Entry 4 324 */ 325 326 327 328#define IIO_IPRTE5 0x00400330 /* 329 * IO PIO Read Address 330 * Table Entry 5 331 */ 332 333 334 335#define IIO_IPRTE6 0x00400338 /* 336 * IO PIO Read Address 337 * Table Entry 6 338 */ 339 340 341 342#define IIO_IPRTE7 0x00400340 /* 343 * IO PIO Read Address 344 * Table Entry 7 345 */ 346 347 348 349#define IIO_IPDR 0x00400388 /* 350 * IO PIO Deallocation 351 * Register 352 */ 353 354 355 356#define IIO_ICDR 0x00400390 /* 357 * IO CRB Entry 358 * Deallocation 359 * Register 360 */ 361 362 363 364#define IIO_IFDR 0x00400398 /* 365 * IO IOQ FIFO Depth 366 * Register 367 */ 368 369 370 371#define IIO_IIAP 0x004003A0 /* 372 * IO IIQ Arbitration 373 * Parameters 374 */ 375 376 377 378#define IIO_ICMR 0x004003A8 /* 379 * IO CRB Management 380 * Register 381 */ 382 383 384 385#define IIO_ICCR 0x004003B0 /* 386 * IO CRB Control 387 * Register 388 */ 389 390 391 392#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ 393 394 395 396#define IIO_ICTP 0x004003C0 /* 397 * IO CRB Timeout 398 * Prescalar 399 */ 400 401 402 403#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ 404 405 406 407#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ 408 409 410 411#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ 412 413 414 415#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ 416 417 418 419#define IIO_ICRB1_A 0x00400420 /* IO CRB Entry 1_A */ 420 421 422 423#define IIO_ICRB1_B 0x00400428 /* IO CRB Entry 1_B */ 424 425 426 427#define IIO_ICRB1_C 0x00400430 /* IO CRB Entry 1_C */ 428 429 430 431#define IIO_ICRB1_D 0x00400438 /* IO CRB Entry 1_D */ 432 433 434 435#define IIO_ICRB2_A 0x00400440 /* IO CRB Entry 2_A */ 436 437 438 439#define IIO_ICRB2_B 0x00400448 /* IO CRB Entry 2_B */ 440 441 442 443#define IIO_ICRB2_C 0x00400450 /* IO CRB Entry 2_C */ 444 445 446 447#define IIO_ICRB2_D 0x00400458 /* IO CRB Entry 2_D */ 448 449 450 451#define IIO_ICRB3_A 0x00400460 /* IO CRB Entry 3_A */ 452 453 454 455#define IIO_ICRB3_B 0x00400468 /* IO CRB Entry 3_B */ 456 457 458 459#define IIO_ICRB3_C 0x00400470 /* IO CRB Entry 3_C */ 460 461 462 463#define IIO_ICRB3_D 0x00400478 /* IO CRB Entry 3_D */ 464 465 466 467#define IIO_ICRB4_A 0x00400480 /* IO CRB Entry 4_A */ 468 469 470 471#define IIO_ICRB4_B 0x00400488 /* IO CRB Entry 4_B */ 472 473 474 475#define IIO_ICRB4_C 0x00400490 /* IO CRB Entry 4_C */ 476 477 478 479#define IIO_ICRB4_D 0x00400498 /* IO CRB Entry 4_D */ 480 481 482 483#define IIO_ICRB5_A 0x004004A0 /* IO CRB Entry 5_A */ 484 485 486 487#define IIO_ICRB5_B 0x004004A8 /* IO CRB Entry 5_B */ 488 489 490 491#define IIO_ICRB5_C 0x004004B0 /* IO CRB Entry 5_C */ 492 493 494 495#define IIO_ICRB5_D 0x004004B8 /* IO CRB Entry 5_D */ 496 497 498 499#define IIO_ICRB6_A 0x004004C0 /* IO CRB Entry 6_A */ 500 501 502 503#define IIO_ICRB6_B 0x004004C8 /* IO CRB Entry 6_B */ 504 505 506 507#define IIO_ICRB6_C 0x004004D0 /* IO CRB Entry 6_C */ 508 509 510 511#define IIO_ICRB6_D 0x004004D8 /* IO CRB Entry 6_D */ 512 513 514 515#define IIO_ICRB7_A 0x004004E0 /* IO CRB Entry 7_A */ 516 517 518 519#define IIO_ICRB7_B 0x004004E8 /* IO CRB Entry 7_B */ 520 521 522 523#define IIO_ICRB7_C 0x004004F0 /* IO CRB Entry 7_C */ 524 525 526 527#define IIO_ICRB7_D 0x004004F8 /* IO CRB Entry 7_D */ 528 529 530 531#define IIO_ICRB8_A 0x00400500 /* IO CRB Entry 8_A */ 532 533 534 535#define IIO_ICRB8_B 0x00400508 /* IO CRB Entry 8_B */ 536 537 538 539#define IIO_ICRB8_C 0x00400510 /* IO CRB Entry 8_C */ 540 541 542 543#define IIO_ICRB8_D 0x00400518 /* IO CRB Entry 8_D */ 544 545 546 547#define IIO_ICRB9_A 0x00400520 /* IO CRB Entry 9_A */ 548 549 550 551#define IIO_ICRB9_B 0x00400528 /* IO CRB Entry 9_B */ 552 553 554 555#define IIO_ICRB9_C 0x00400530 /* IO CRB Entry 9_C */ 556 557 558 559#define IIO_ICRB9_D 0x00400538 /* IO CRB Entry 9_D */ 560 561 562 563#define IIO_ICRBA_A 0x00400540 /* IO CRB Entry A_A */ 564 565 566 567#define IIO_ICRBA_B 0x00400548 /* IO CRB Entry A_B */ 568 569 570 571#define IIO_ICRBA_C 0x00400550 /* IO CRB Entry A_C */ 572 573 574 575#define IIO_ICRBA_D 0x00400558 /* IO CRB Entry A_D */ 576 577 578 579#define IIO_ICRBB_A 0x00400560 /* IO CRB Entry B_A */ 580 581 582 583#define IIO_ICRBB_B 0x00400568 /* IO CRB Entry B_B */ 584 585 586 587#define IIO_ICRBB_C 0x00400570 /* IO CRB Entry B_C */ 588 589 590 591#define IIO_ICRBB_D 0x00400578 /* IO CRB Entry B_D */ 592 593 594 595#define IIO_ICRBC_A 0x00400580 /* IO CRB Entry C_A */ 596 597 598 599#define IIO_ICRBC_B 0x00400588 /* IO CRB Entry C_B */ 600 601 602 603#define IIO_ICRBC_C 0x00400590 /* IO CRB Entry C_C */ 604 605 606 607#define IIO_ICRBC_D 0x00400598 /* IO CRB Entry C_D */ 608 609 610 611#define IIO_ICRBD_A 0x004005A0 /* IO CRB Entry D_A */ 612 613 614 615#define IIO_ICRBD_B 0x004005A8 /* IO CRB Entry D_B */ 616 617 618 619#define IIO_ICRBD_C 0x004005B0 /* IO CRB Entry D_C */ 620 621 622 623#define IIO_ICRBD_D 0x004005B8 /* IO CRB Entry D_D */ 624 625 626 627#define IIO_ICRBE_A 0x004005C0 /* IO CRB Entry E_A */ 628 629 630 631#define IIO_ICRBE_B 0x004005C8 /* IO CRB Entry E_B */ 632 633 634 635#define IIO_ICRBE_C 0x004005D0 /* IO CRB Entry E_C */ 636 637 638 639#define IIO_ICRBE_D 0x004005D8 /* IO CRB Entry E_D */ 640 641 642 643#define IIO_ICSML 0x00400600 /* 644 * IO CRB Spurious 645 * Message Low 646 */ 647 648 649 650#define IIO_ICSMH 0x00400608 /* 651 * IO CRB Spurious 652 * Message High 653 */ 654 655 656 657#define IIO_IDBSS 0x00400610 /* 658 * IO Debug Submenu 659 * Select 660 */ 661 662 663 664#define IIO_IBLS0 0x00410000 /* 665 * IO BTE Length 666 * Status 0 667 */ 668 669 670 671#define IIO_IBSA0 0x00410008 /* 672 * IO BTE Source 673 * Address 0 674 */ 675 676 677 678#define IIO_IBDA0 0x00410010 /* 679 * IO BTE Destination 680 * Address 0 681 */ 682 683 684 685#define IIO_IBCT0 0x00410018 /* 686 * IO BTE Control 687 * Terminate 0 688 */ 689 690 691 692#define IIO_IBNA0 0x00410020 /* 693 * IO BTE Notification 694 * Address 0 695 */ 696 697 698 699#define IIO_IBIA0 0x00410028 /* 700 * IO BTE Interrupt 701 * Address 0 702 */ 703 704 705 706#define IIO_IBLS1 0x00420000 /* 707 * IO BTE Length 708 * Status 1 709 */ 710 711 712 713#define IIO_IBSA1 0x00420008 /* 714 * IO BTE Source 715 * Address 1 716 */ 717 718 719 720#define IIO_IBDA1 0x00420010 /* 721 * IO BTE Destination 722 * Address 1 723 */ 724 725 726 727#define IIO_IBCT1 0x00420018 /* 728 * IO BTE Control 729 * Terminate 1 730 */ 731 732 733 734#define IIO_IBNA1 0x00420020 /* 735 * IO BTE Notification 736 * Address 1 737 */ 738 739 740 741#define IIO_IBIA1 0x00420028 /* 742 * IO BTE Interrupt 743 * Address 1 744 */ 745 746 747 748#define IIO_IPCR 0x00430000 /* 749 * IO Performance 750 * Control 751 */ 752 753 754 755#define IIO_IPPR 0x00430008 /* 756 * IO Performance 757 * Profiling 758 */ 759 760 761 762 763 764#ifndef __ASSEMBLY__ 765 766/************************************************************************ 767 * * 768 * Description: This register echoes some information from the * 769 * LB_REV_ID register. It is available through Crosstalk as described * 770 * above. The REV_NUM and MFG_NUM fields receive their values from * 771 * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * 772 * The PART_NUM field's value is the Crosstalk device ID number that * 773 * Steve Miller assigned to the Bedrock chip. * 774 * * 775 ************************************************************************/ 776 777 778 779 780#ifdef LITTLE_ENDIAN 781 782typedef union ii_wid_u { 783 bdrkreg_t ii_wid_regval; 784 struct { 785 bdrkreg_t w_rsvd_1 : 1; 786 bdrkreg_t w_mfg_num : 11; 787 bdrkreg_t w_part_num : 16; 788 bdrkreg_t w_rev_num : 4; 789 bdrkreg_t w_rsvd : 32; 790 } ii_wid_fld_s; 791} ii_wid_u_t; 792 793#else 794 795typedef union ii_wid_u { 796 bdrkreg_t ii_wid_regval; 797 struct { 798 bdrkreg_t w_rsvd : 32; 799 bdrkreg_t w_rev_num : 4; 800 bdrkreg_t w_part_num : 16; 801 bdrkreg_t w_mfg_num : 11; 802 bdrkreg_t w_rsvd_1 : 1; 803 } ii_wid_fld_s; 804} ii_wid_u_t; 805 806#endif 807 808 809 810 811/************************************************************************ 812 * * 813 * The fields in this register are set upon detection of an error * 814 * and cleared by various mechanisms, as explained in the * 815 * description. * 816 * * 817 ************************************************************************/ 818 819 820 821 822#ifdef LITTLE_ENDIAN 823 824typedef union ii_wstat_u { 825 bdrkreg_t ii_wstat_regval; 826 struct { 827 bdrkreg_t w_pending : 4; 828 bdrkreg_t w_xt_crd_to : 1; 829 bdrkreg_t w_xt_tail_to : 1; 830 bdrkreg_t w_rsvd_3 : 3; 831 bdrkreg_t w_tx_mx_rty : 1; 832 bdrkreg_t w_rsvd_2 : 6; 833 bdrkreg_t w_llp_tx_cnt : 8; 834 bdrkreg_t w_rsvd_1 : 8; 835 bdrkreg_t w_crazy : 1; 836 bdrkreg_t w_rsvd : 31; 837 } ii_wstat_fld_s; 838} ii_wstat_u_t; 839 840#else 841 842typedef union ii_wstat_u { 843 bdrkreg_t ii_wstat_regval; 844 struct { 845 bdrkreg_t w_rsvd : 31; 846 bdrkreg_t w_crazy : 1; 847 bdrkreg_t w_rsvd_1 : 8; 848 bdrkreg_t w_llp_tx_cnt : 8; 849 bdrkreg_t w_rsvd_2 : 6; 850 bdrkreg_t w_tx_mx_rty : 1; 851 bdrkreg_t w_rsvd_3 : 3; 852 bdrkreg_t w_xt_tail_to : 1; 853 bdrkreg_t w_xt_crd_to : 1; 854 bdrkreg_t w_pending : 4; 855 } ii_wstat_fld_s; 856} ii_wstat_u_t; 857 858#endif 859 860 861 862 863/************************************************************************ 864 * * 865 * Description: This is a read-write enabled register. It controls * 866 * various aspects of the Crosstalk flow control. * 867 * * 868 ************************************************************************/ 869 870 871 872 873#ifdef LITTLE_ENDIAN 874 875typedef union ii_wcr_u { 876 bdrkreg_t ii_wcr_regval; 877 struct { 878 bdrkreg_t w_wid : 4; 879 bdrkreg_t w_tag : 1; 880 bdrkreg_t w_rsvd_1 : 8; 881 bdrkreg_t w_dst_crd : 3; 882 bdrkreg_t w_f_bad_pkt : 1; 883 bdrkreg_t w_dir_con : 1; 884 bdrkreg_t w_e_thresh : 5; 885 bdrkreg_t w_rsvd : 41; 886 } ii_wcr_fld_s; 887} ii_wcr_u_t; 888 889#else 890 891typedef union ii_wcr_u { 892 bdrkreg_t ii_wcr_regval; 893 struct { 894 bdrkreg_t w_rsvd : 41; 895 bdrkreg_t w_e_thresh : 5; 896 bdrkreg_t w_dir_con : 1; 897 bdrkreg_t w_f_bad_pkt : 1; 898 bdrkreg_t w_dst_crd : 3; 899 bdrkreg_t w_rsvd_1 : 8; 900 bdrkreg_t w_tag : 1; 901 bdrkreg_t w_wid : 4; 902 } ii_wcr_fld_s; 903} ii_wcr_u_t; 904 905#endif 906 907 908 909 910/************************************************************************ 911 * * 912 * Description: This register's value is a bit vector that guards * 913 * access to local registers within the II as well as to external * 914 * Crosstalk widgets. Each bit in the register corresponds to a * 915 * particular region in the system; a region consists of one, two or * 916 * four nodes (depending on the value of the REGION_SIZE field in the * 917 * LB_REV_ID register, which is documented in Section 8.3.1.1). The * 918 * protection provided by this register applies to PIO read * 919 * operations as well as PIO write operations. The II will perform a * 920 * PIO read or write request only if the bit for the requestor's * 921 * region is set; otherwise, the II will not perform the requested * 922 * operation and will return an error response. When a PIO read or * 923 * write request targets an external Crosstalk widget, then not only * 924 * must the bit for the requestor's region be set in the ILAPR, but * 925 * also the target widget's bit in the IOWA register must be set in * 926 * order for the II to perform the requested operation; otherwise, * 927 * the II will return an error response. Hence, the protection * 928 * provided by the IOWA register supplements the protection provided * 929 * by the ILAPR for requests that target external Crosstalk widgets. * 930 * This register itself can be accessed only by the nodes whose * 931 * region ID bits are enabled in this same register. It can also be * 932 * accessed through the IAlias space by the local processors. * 933 * The reset value of this register allows access by all nodes. * 934 * * 935 ************************************************************************/ 936 937 938 939 940typedef union ii_ilapr_u { 941 bdrkreg_t ii_ilapr_regval; 942 struct { 943 bdrkreg_t i_region : 64; 944 } ii_ilapr_fld_s; 945} ii_ilapr_u_t; 946 947 948 949 950/************************************************************************ 951 * * 952 * Description: A write to this register of the 64-bit value * 953 * "SGIrules" in ASCII, will cause the bit in the ILAPR register * 954 * corresponding to the region of the requestor to be set (allow * 955 * access). A write of any other value will be ignored. Access * 956 * protection for this register is "SGIrules". * 957 * This register can also be accessed through the IAlias space. * 958 * However, this access will not change the access permissions in the * 959 * ILAPR. * 960 * * 961 ************************************************************************/ 962 963 964 965 966#ifdef LITTLE_ENDIAN 967 968typedef union ii_ilapo_u { 969 bdrkreg_t ii_ilapo_regval; 970 struct { 971 bdrkreg_t i_io_ovrride : 9; 972 bdrkreg_t i_rsvd : 55; 973 } ii_ilapo_fld_s; 974} ii_ilapo_u_t; 975 976#else 977 978typedef union ii_ilapo_u { 979 bdrkreg_t ii_ilapo_regval; 980 struct { 981 bdrkreg_t i_rsvd : 55; 982 bdrkreg_t i_io_ovrride : 9; 983 } ii_ilapo_fld_s; 984} ii_ilapo_u_t; 985 986#endif 987 988 989 990 991/************************************************************************ 992 * * 993 * This register qualifies all the PIO and Graphics writes launched * 994 * from the Bedrock towards a widget. * 995 * * 996 ************************************************************************/ 997 998 999 1000 1001#ifdef LITTLE_ENDIAN 1002 1003typedef union ii_iowa_u { 1004 bdrkreg_t ii_iowa_regval; 1005 struct { 1006 bdrkreg_t i_w0_oac : 1; 1007 bdrkreg_t i_rsvd_1 : 7; 1008 bdrkreg_t i_wx_oac : 8; 1009 bdrkreg_t i_rsvd : 48; 1010 } ii_iowa_fld_s; 1011} ii_iowa_u_t; 1012 1013#else 1014 1015typedef union ii_iowa_u { 1016 bdrkreg_t ii_iowa_regval; 1017 struct { 1018 bdrkreg_t i_rsvd : 48; 1019 bdrkreg_t i_wx_oac : 8; 1020 bdrkreg_t i_rsvd_1 : 7; 1021 bdrkreg_t i_w0_oac : 1; 1022 } ii_iowa_fld_s; 1023} ii_iowa_u_t; 1024 1025#endif 1026 1027 1028 1029 1030/************************************************************************ 1031 * * 1032 * Description: This register qualifies all the requests launched * 1033 * from a widget towards the Bedrock. This register is intended to be * 1034 * used by software in case of misbehaving widgets. * 1035 * * 1036 * * 1037 ************************************************************************/ 1038 1039 1040 1041 1042#ifdef LITTLE_ENDIAN 1043 1044typedef union ii_iiwa_u { 1045 bdrkreg_t ii_iiwa_regval; 1046 struct { 1047 bdrkreg_t i_w0_iac : 1; 1048 bdrkreg_t i_rsvd_1 : 7; 1049 bdrkreg_t i_wx_iac : 8; 1050 bdrkreg_t i_rsvd : 48; 1051 } ii_iiwa_fld_s; 1052} ii_iiwa_u_t; 1053 1054#else 1055 1056typedef union ii_iiwa_u { 1057 bdrkreg_t ii_iiwa_regval; 1058 struct { 1059 bdrkreg_t i_rsvd : 48; 1060 bdrkreg_t i_wx_iac : 8; 1061 bdrkreg_t i_rsvd_1 : 7; 1062 bdrkreg_t i_w0_iac : 1; 1063 } ii_iiwa_fld_s; 1064} ii_iiwa_u_t; 1065 1066#endif 1067 1068 1069 1070 1071/************************************************************************ 1072 * * 1073 * Description: This register qualifies all the operations launched * 1074 * from a widget towards the Bedrock. It allows individual access * 1075 * control for up to 8 devices per widget. A device refers to * 1076 * individual DMA master hosted by a widget. * 1077 * The bits in each field of this register are cleared by the Bedrock * 1078 * upon detection of an error which requires the device to be * 1079 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric * 1080 * Crosstalk). Whether or not a device has access rights to this * 1081 * Bedrock is determined by an AND of the device enable bit in the * 1082 * appropriate field of this register and the corresponding bit in * 1083 * the Wx_IAC field (for the widget which this device belongs to). * 1084 * The bits in this field are set by writing a 1 to them. Incoming * 1085 * replies from Crosstalk are not subject to this access control * 1086 * mechanism. * 1087 * * 1088 ************************************************************************/ 1089 1090 1091 1092 1093#ifdef LITTLE_ENDIAN 1094 1095typedef union ii_iidem_u { 1096 bdrkreg_t ii_iidem_regval; 1097 struct { 1098 bdrkreg_t i_w8_dxs : 8; 1099 bdrkreg_t i_w9_dxs : 8; 1100 bdrkreg_t i_wa_dxs : 8; 1101 bdrkreg_t i_wb_dxs : 8; 1102 bdrkreg_t i_wc_dxs : 8; 1103 bdrkreg_t i_wd_dxs : 8; 1104 bdrkreg_t i_we_dxs : 8; 1105 bdrkreg_t i_wf_dxs : 8; 1106 } ii_iidem_fld_s; 1107} ii_iidem_u_t; 1108 1109#else 1110 1111typedef union ii_iidem_u { 1112 bdrkreg_t ii_iidem_regval; 1113 struct { 1114 bdrkreg_t i_wf_dxs : 8; 1115 bdrkreg_t i_we_dxs : 8; 1116 bdrkreg_t i_wd_dxs : 8; 1117 bdrkreg_t i_wc_dxs : 8; 1118 bdrkreg_t i_wb_dxs : 8; 1119 bdrkreg_t i_wa_dxs : 8; 1120 bdrkreg_t i_w9_dxs : 8; 1121 bdrkreg_t i_w8_dxs : 8; 1122 } ii_iidem_fld_s; 1123} ii_iidem_u_t; 1124 1125#endif 1126 1127 1128 1129 1130/************************************************************************ 1131 * * 1132 * This register contains the various programmable fields necessary * 1133 * for controlling and observing the LLP signals. * 1134 * * 1135 ************************************************************************/ 1136 1137 1138 1139 1140#ifdef LITTLE_ENDIAN 1141 1142typedef union ii_ilcsr_u { 1143 bdrkreg_t ii_ilcsr_regval; 1144 struct { 1145 bdrkreg_t i_nullto : 6; 1146 bdrkreg_t i_rsvd_4 : 2; 1147 bdrkreg_t i_wrmrst : 1; 1148 bdrkreg_t i_rsvd_3 : 1; 1149 bdrkreg_t i_llp_en : 1; 1150 bdrkreg_t i_bm8 : 1; 1151 bdrkreg_t i_llp_stat : 2; 1152 bdrkreg_t i_remote_power : 1; 1153 bdrkreg_t i_rsvd_2 : 1; 1154 bdrkreg_t i_maxrtry : 10; 1155 bdrkreg_t i_d_avail_sel : 2; 1156 bdrkreg_t i_rsvd_1 : 4; 1157 bdrkreg_t i_maxbrst : 10; 1158 bdrkreg_t i_rsvd : 22; 1159 1160 } ii_ilcsr_fld_s; 1161} ii_ilcsr_u_t; 1162 1163#else 1164 1165typedef union ii_ilcsr_u { 1166 bdrkreg_t ii_ilcsr_regval; 1167 struct { 1168 bdrkreg_t i_rsvd : 22; 1169 bdrkreg_t i_maxbrst : 10; 1170 bdrkreg_t i_rsvd_1 : 4; 1171 bdrkreg_t i_d_avail_sel : 2; 1172 bdrkreg_t i_maxrtry : 10; 1173 bdrkreg_t i_rsvd_2 : 1; 1174 bdrkreg_t i_remote_power : 1; 1175 bdrkreg_t i_llp_stat : 2; 1176 bdrkreg_t i_bm8 : 1; 1177 bdrkreg_t i_llp_en : 1; 1178 bdrkreg_t i_rsvd_3 : 1; 1179 bdrkreg_t i_wrmrst : 1; 1180 bdrkreg_t i_rsvd_4 : 2; 1181 bdrkreg_t i_nullto : 6; 1182 } ii_ilcsr_fld_s; 1183} ii_ilcsr_u_t; 1184 1185#endif 1186 1187 1188 1189 1190/************************************************************************ 1191 * * 1192 * This is simply a status registers that monitors the LLP error * 1193 * rate. * 1194 * * 1195 ************************************************************************/ 1196 1197 1198 1199 1200#ifdef LITTLE_ENDIAN 1201 1202typedef union ii_illr_u { 1203 bdrkreg_t ii_illr_regval; 1204 struct { 1205 bdrkreg_t i_sn_cnt : 16; 1206 bdrkreg_t i_cb_cnt : 16; 1207 bdrkreg_t i_rsvd : 32; 1208 } ii_illr_fld_s; 1209} ii_illr_u_t; 1210 1211#else 1212 1213typedef union ii_illr_u { 1214 bdrkreg_t ii_illr_regval; 1215 struct { 1216 bdrkreg_t i_rsvd : 32; 1217 bdrkreg_t i_cb_cnt : 16; 1218 bdrkreg_t i_sn_cnt : 16; 1219 } ii_illr_fld_s; 1220} ii_illr_u_t; 1221 1222#endif 1223 1224 1225 1226 1227/************************************************************************ 1228 * * 1229 * Description: All II-detected non-BTE error interrupts are * 1230 * specified via this register. * 1231 * NOTE: The PI interrupt register address is hardcoded in the II. If * 1232 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI * 1233 * packet) to address offset 0x0180_0090 within the local register * 1234 * address space of PI0 on the node specified by the NODE field. If * 1235 * PI_ID==1, then the II sends the interrupt request to address * 1236 * offset 0x01A0_0090 within the local register address space of PI1 * 1237 * on the node specified by the NODE field. * 1238 * * 1239 ************************************************************************/ 1240 1241 1242 1243 1244#ifdef LITTLE_ENDIAN 1245 1246typedef union ii_iidsr_u { 1247 bdrkreg_t ii_iidsr_regval; 1248 struct { 1249 bdrkreg_t i_level : 7; 1250 bdrkreg_t i_rsvd_4 : 1; 1251 bdrkreg_t i_pi_id : 1; 1252 bdrkreg_t i_node : 8; 1253 bdrkreg_t i_rsvd_3 : 7; 1254 bdrkreg_t i_enable : 1; 1255 bdrkreg_t i_rsvd_2 : 3; 1256 bdrkreg_t i_int_sent : 1; 1257 bdrkreg_t i_rsvd_1 : 3; 1258 bdrkreg_t i_pi0_forward_int : 1; 1259 bdrkreg_t i_pi1_forward_int : 1; 1260 bdrkreg_t i_rsvd : 30; 1261 } ii_iidsr_fld_s; 1262} ii_iidsr_u_t; 1263 1264#else 1265 1266typedef union ii_iidsr_u { 1267 bdrkreg_t ii_iidsr_regval; 1268 struct { 1269 bdrkreg_t i_rsvd : 30; 1270 bdrkreg_t i_pi1_forward_int : 1; 1271 bdrkreg_t i_pi0_forward_int : 1; 1272 bdrkreg_t i_rsvd_1 : 3; 1273 bdrkreg_t i_int_sent : 1; 1274 bdrkreg_t i_rsvd_2 : 3; 1275 bdrkreg_t i_enable : 1; 1276 bdrkreg_t i_rsvd_3 : 7; 1277 bdrkreg_t i_node : 8; 1278 bdrkreg_t i_pi_id : 1; 1279 bdrkreg_t i_rsvd_4 : 1; 1280 bdrkreg_t i_level : 7; 1281 } ii_iidsr_fld_s; 1282} ii_iidsr_u_t; 1283 1284#endif 1285 1286 1287 1288 1289/************************************************************************ 1290 * * 1291 * There are two instances of this register. This register is used * 1292 * for matching up the incoming responses from the graphics widget to * 1293 * the processor that initiated the graphics operation. The * 1294 * write-responses are converted to graphics credits and returned to * 1295 * the processor so that the processor interface can manage the flow * 1296 * control. * 1297 * * 1298 ************************************************************************/ 1299 1300 1301 1302 1303#ifdef LITTLE_ENDIAN 1304 1305typedef union ii_igfx0_u { 1306 bdrkreg_t ii_igfx0_regval; 1307 struct { 1308 bdrkreg_t i_w_num : 4; 1309 bdrkreg_t i_pi_id : 1; 1310 bdrkreg_t i_n_num : 8; 1311 bdrkreg_t i_rsvd_1 : 3; 1312 bdrkreg_t i_p_num : 1; 1313 bdrkreg_t i_rsvd : 47; 1314 } ii_igfx0_fld_s; 1315} ii_igfx0_u_t; 1316 1317#else 1318 1319typedef union ii_igfx0_u { 1320 bdrkreg_t ii_igfx0_regval; 1321 struct { 1322 bdrkreg_t i_rsvd : 47; 1323 bdrkreg_t i_p_num : 1; 1324 bdrkreg_t i_rsvd_1 : 3; 1325 bdrkreg_t i_n_num : 8; 1326 bdrkreg_t i_pi_id : 1; 1327 bdrkreg_t i_w_num : 4; 1328 } ii_igfx0_fld_s; 1329} ii_igfx0_u_t; 1330 1331#endif 1332 1333 1334 1335 1336/************************************************************************ 1337 * * 1338 * There are two instances of this register. This register is used * 1339 * for matching up the incoming responses from the graphics widget to * 1340 * the processor that initiated the graphics operation. The * 1341 * write-responses are converted to graphics credits and returned to * 1342 * the processor so that the processor interface can manage the flow * 1343 * control. * 1344 * * 1345 ************************************************************************/ 1346 1347 1348 1349 1350#ifdef LITTLE_ENDIAN 1351 1352typedef union ii_igfx1_u { 1353 bdrkreg_t ii_igfx1_regval; 1354 struct { 1355 bdrkreg_t i_w_num : 4; 1356 bdrkreg_t i_pi_id : 1; 1357 bdrkreg_t i_n_num : 8; 1358 bdrkreg_t i_rsvd_1 : 3; 1359 bdrkreg_t i_p_num : 1; 1360 bdrkreg_t i_rsvd : 47; 1361 } ii_igfx1_fld_s; 1362} ii_igfx1_u_t; 1363 1364#else 1365 1366typedef union ii_igfx1_u { 1367 bdrkreg_t ii_igfx1_regval; 1368 struct { 1369 bdrkreg_t i_rsvd : 47; 1370 bdrkreg_t i_p_num : 1; 1371 bdrkreg_t i_rsvd_1 : 3; 1372 bdrkreg_t i_n_num : 8; 1373 bdrkreg_t i_pi_id : 1; 1374 bdrkreg_t i_w_num : 4; 1375 } ii_igfx1_fld_s; 1376} ii_igfx1_u_t; 1377 1378#endif 1379 1380 1381 1382 1383/************************************************************************ 1384 * * 1385 * There are two instances of this registers. These registers are * 1386 * used as scratch registers for software use. * 1387 * * 1388 ************************************************************************/ 1389 1390 1391 1392 1393typedef union ii_iscr0_u { 1394 bdrkreg_t ii_iscr0_regval; 1395 struct { 1396 bdrkreg_t i_scratch : 64; 1397 } ii_iscr0_fld_s; 1398} ii_iscr0_u_t; 1399 1400 1401 1402 1403/************************************************************************ 1404 * * 1405 * There are two instances of this registers. These registers are * 1406 * used as scratch registers for software use. * 1407 * * 1408 ************************************************************************/ 1409 1410 1411 1412 1413typedef union ii_iscr1_u { 1414 bdrkreg_t ii_iscr1_regval; 1415 struct { 1416 bdrkreg_t i_scratch : 64; 1417 } ii_iscr1_fld_s; 1418} ii_iscr1_u_t; 1419 1420 1421 1422 1423/************************************************************************ 1424 * * 1425 * Description: There are seven instances of translation table entry * 1426 * registers. Each register maps a Bedrock Big Window to a 48-bit * 1427 * address on Crosstalk. * 1428 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 1429 * number) are used to select one of these 7 registers. The Widget * 1430 * number field is then derived from the W_NUM field for synthesizing * 1431 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 1432 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 1433 * are padded with zeros. Although the maximum Crosstalk space * 1434 * addressable by the Bedrock is thus the lower 16 GBytes per widget * 1435 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 1436 * space can be accessed. * 1437 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 1438 * Window number) are used to select one of these 7 registers. The * 1439 * Widget number field is then derived from the W_NUM field for * 1440 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 1441 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 1442 * field is used as Crosstalk[47], and remainder of the Crosstalk * 1443 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 1444 * Crosstalk space addressable by the Bedrock is thus the lower * 1445 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 1446 * of this space can be accessed. * 1447 * * 1448 ************************************************************************/ 1449 1450 1451 1452 1453#ifdef LITTLE_ENDIAN 1454 1455typedef union ii_itte1_u { 1456 bdrkreg_t ii_itte1_regval; 1457 struct { 1458 bdrkreg_t i_offset : 5; 1459 bdrkreg_t i_rsvd_1 : 3; 1460 bdrkreg_t i_w_num : 4; 1461 bdrkreg_t i_iosp : 1; 1462 bdrkreg_t i_rsvd : 51; 1463 } ii_itte1_fld_s; 1464} ii_itte1_u_t; 1465 1466#else 1467 1468typedef union ii_itte1_u { 1469 bdrkreg_t ii_itte1_regval; 1470 struct { 1471 bdrkreg_t i_rsvd : 51; 1472 bdrkreg_t i_iosp : 1; 1473 bdrkreg_t i_w_num : 4; 1474 bdrkreg_t i_rsvd_1 : 3; 1475 bdrkreg_t i_offset : 5; 1476 } ii_itte1_fld_s; 1477} ii_itte1_u_t; 1478 1479#endif 1480 1481 1482 1483 1484/************************************************************************ 1485 * * 1486 * Description: There are seven instances of translation table entry * 1487 * registers. Each register maps a Bedrock Big Window to a 48-bit * 1488 * address on Crosstalk. * 1489 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 1490 * number) are used to select one of these 7 registers. The Widget * 1491 * number field is then derived from the W_NUM field for synthesizing * 1492 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 1493 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 1494 * are padded with zeros. Although the maximum Crosstalk space * 1495 * addressable by the Bedrock is thus the lower 16 GBytes per widget * 1496 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 1497 * space can be accessed. * 1498 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 1499 * Window number) are used to select one of these 7 registers. The * 1500 * Widget number field is then derived from the W_NUM field for * 1501 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 1502 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 1503 * field is used as Crosstalk[47], and remainder of the Crosstalk * 1504 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 1505 * Crosstalk space addressable by the Bedrock is thus the lower * 1506 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 1507 * of this space can be accessed. * 1508 * * 1509 ************************************************************************/ 1510 1511 1512 1513 1514#ifdef LITTLE_ENDIAN 1515 1516typedef union ii_itte2_u { 1517 bdrkreg_t ii_itte2_regval; 1518 struct { 1519 bdrkreg_t i_offset : 5; 1520 bdrkreg_t i_rsvd_1 : 3; 1521 bdrkreg_t i_w_num : 4; 1522 bdrkreg_t i_iosp : 1; 1523 bdrkreg_t i_rsvd : 51; 1524 } ii_itte2_fld_s; 1525} ii_itte2_u_t; 1526 1527#else 1528typedef union ii_itte2_u { 1529 bdrkreg_t ii_itte2_regval; 1530 struct { 1531 bdrkreg_t i_rsvd : 51; 1532 bdrkreg_t i_iosp : 1; 1533 bdrkreg_t i_w_num : 4; 1534 bdrkreg_t i_rsvd_1 : 3; 1535 bdrkreg_t i_offset : 5; 1536 } ii_itte2_fld_s; 1537} ii_itte2_u_t; 1538 1539#endif 1540 1541 1542 1543 1544/************************************************************************ 1545 * * 1546 * Description: There are seven instances of translation table entry * 1547 * registers. Each register maps a Bedrock Big Window to a 48-bit * 1548 * address on Crosstalk. * 1549 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 1550 * number) are used to select one of these 7 registers. The Widget * 1551 * number field is then derived from the W_NUM field for synthesizing * 1552 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 1553 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 1554 * are padded with zeros. Although the maximum Crosstalk space * 1555 * addressable by the Bedrock is thus the lower 16 GBytes per widget * 1556 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 1557 * space can be accessed. * 1558 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 1559 * Window number) are used to select one of these 7 registers. The * 1560 * Widget number field is then derived from the W_NUM field for * 1561 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 1562 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 1563 * field is used as Crosstalk[47], and remainder of the Crosstalk * 1564 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 1565 * Crosstalk space addressable by the Bedrock is thus the lower * 1566 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 1567 * of this space can be accessed. * 1568 * * 1569 ************************************************************************/ 1570 1571 1572 1573 1574#ifdef LITTLE_ENDIAN 1575 1576typedef union ii_itte3_u { 1577 bdrkreg_t ii_itte3_regval; 1578 struct { 1579 bdrkreg_t i_offset : 5; 1580 bdrkreg_t i_rsvd_1 : 3; 1581 bdrkreg_t i_w_num : 4; 1582 bdrkreg_t i_iosp : 1; 1583 bdrkreg_t i_rsvd : 51; 1584 } ii_itte3_fld_s; 1585} ii_itte3_u_t; 1586 1587#else 1588 1589typedef union ii_itte3_u { 1590 bdrkreg_t ii_itte3_regval; 1591 struct { 1592 bdrkreg_t i_rsvd : 51; 1593 bdrkreg_t i_iosp : 1; 1594 bdrkreg_t i_w_num : 4; 1595 bdrkreg_t i_rsvd_1 : 3; 1596 bdrkreg_t i_offset : 5; 1597 } ii_itte3_fld_s; 1598} ii_itte3_u_t; 1599 1600#endif 1601 1602 1603 1604 1605/************************************************************************ 1606 * * 1607 * Description: There are seven instances of translation table entry * 1608 * registers. Each register maps a Bedrock Big Window to a 48-bit * 1609 * address on Crosstalk. * 1610 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 1611 * number) are used to select one of these 7 registers. The Widget * 1612 * number field is then derived from the W_NUM field for synthesizing * 1613 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 1614 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 1615 * are padded with zeros. Although the maximum Crosstalk space * 1616 * addressable by the Bedrock is thus the lower 16 GBytes per widget * 1617 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 1618 * space can be accessed. * 1619 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 1620 * Window number) are used to select one of these 7 registers. The * 1621 * Widget number field is then derived from the W_NUM field for * 1622 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 1623 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 1624 * field is used as Crosstalk[47], and remainder of the Crosstalk * 1625 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 1626 * Crosstalk space addressable by the Bedrock is thus the lower * 1627 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 1628 * of this space can be accessed. * 1629 * * 1630 ************************************************************************/ 1631 1632 1633 1634 1635#ifdef LITTLE_ENDIAN 1636 1637typedef union ii_itte4_u { 1638 bdrkreg_t ii_itte4_regval; 1639 struct { 1640 bdrkreg_t i_offset : 5; 1641 bdrkreg_t i_rsvd_1 : 3; 1642 bdrkreg_t i_w_num : 4; 1643 bdrkreg_t i_iosp : 1; 1644 bdrkreg_t i_rsvd : 51; 1645 } ii_itte4_fld_s; 1646} ii_itte4_u_t; 1647 1648#else 1649 1650typedef union ii_itte4_u { 1651 bdrkreg_t ii_itte4_regval; 1652 struct { 1653 bdrkreg_t i_rsvd : 51; 1654 bdrkreg_t i_iosp : 1; 1655 bdrkreg_t i_w_num : 4; 1656 bdrkreg_t i_rsvd_1 : 3; 1657 bdrkreg_t i_offset : 5; 1658 } ii_itte4_fld_s; 1659} ii_itte4_u_t; 1660 1661#endif 1662 1663 1664 1665 1666/************************************************************************ 1667 * * 1668 * Description: There are seven instances of translation table entry * 1669 * registers. Each register maps a Bedrock Big Window to a 48-bit * 1670 * address on Crosstalk. * 1671 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 1672 * number) are used to select one of these 7 registers. The Widget * 1673 * number field is then derived from the W_NUM field for synthesizing * 1674 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 1675 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 1676 * are padded with zeros. Although the maximum Crosstalk space * 1677 * addressable by the Bedrock is thus the lower 16 GBytes per widget * 1678 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 1679 * space can be accessed. * 1680 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 1681 * Window number) are used to select one of these 7 registers. The * 1682 * Widget number field is then derived from the W_NUM field for * 1683 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 1684 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 1685 * field is used as Crosstalk[47], and remainder of the Crosstalk * 1686 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 1687 * Crosstalk space addressable by the Bedrock is thus the lower * 1688 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 1689 * of this space can be accessed. * 1690 * * 1691 ************************************************************************/ 1692 1693 1694 1695 1696#ifdef LITTLE_ENDIAN 1697 1698typedef union ii_itte5_u { 1699 bdrkreg_t ii_itte5_regval; 1700 struct { 1701 bdrkreg_t i_offset : 5; 1702 bdrkreg_t i_rsvd_1 : 3; 1703 bdrkreg_t i_w_num : 4; 1704 bdrkreg_t i_iosp : 1; 1705 bdrkreg_t i_rsvd : 51; 1706 } ii_itte5_fld_s; 1707} ii_itte5_u_t; 1708 1709#else 1710 1711typedef union ii_itte5_u { 1712 bdrkreg_t ii_itte5_regval; 1713 struct { 1714 bdrkreg_t i_rsvd : 51; 1715 bdrkreg_t i_iosp : 1; 1716 bdrkreg_t i_w_num : 4; 1717 bdrkreg_t i_rsvd_1 : 3; 1718 bdrkreg_t i_offset : 5; 1719 } ii_itte5_fld_s; 1720} ii_itte5_u_t; 1721 1722#endif 1723 1724 1725 1726 1727/************************************************************************ 1728 * * 1729 * Description: There are seven instances of translation table entry * 1730 * registers. Each register maps a Bedrock Big Window to a 48-bit * 1731 * address on Crosstalk. * 1732 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 1733 * number) are used to select one of these 7 registers. The Widget * 1734 * number field is then derived from the W_NUM field for synthesizing * 1735 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 1736 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 1737 * are padded with zeros. Although the maximum Crosstalk space * 1738 * addressable by the Bedrock is thus the lower 16 GBytes per widget * 1739 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 1740 * space can be accessed. * 1741 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 1742 * Window number) are used to select one of these 7 registers. The * 1743 * Widget number field is then derived from the W_NUM field for * 1744 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 1745 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 1746 * field is used as Crosstalk[47], and remainder of the Crosstalk * 1747 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 1748 * Crosstalk space addressable by the Bedrock is thus the lower * 1749 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 1750 * of this space can be accessed. * 1751 * * 1752 ************************************************************************/ 1753 1754 1755 1756 1757#ifdef LITTLE_ENDIAN 1758 1759typedef union ii_itte6_u { 1760 bdrkreg_t ii_itte6_regval; 1761 struct { 1762 bdrkreg_t i_offset : 5; 1763 bdrkreg_t i_rsvd_1 : 3; 1764 bdrkreg_t i_w_num : 4; 1765 bdrkreg_t i_iosp : 1; 1766 bdrkreg_t i_rsvd : 51; 1767 } ii_itte6_fld_s; 1768} ii_itte6_u_t; 1769 1770#else 1771 1772typedef union ii_itte6_u { 1773 bdrkreg_t ii_itte6_regval; 1774 struct { 1775 bdrkreg_t i_rsvd : 51; 1776 bdrkreg_t i_iosp : 1; 1777 bdrkreg_t i_w_num : 4; 1778 bdrkreg_t i_rsvd_1 : 3; 1779 bdrkreg_t i_offset : 5; 1780 } ii_itte6_fld_s; 1781} ii_itte6_u_t; 1782 1783#endif 1784 1785 1786 1787 1788/************************************************************************ 1789 * * 1790 * Description: There are seven instances of translation table entry * 1791 * registers. Each register maps a Bedrock Big Window to a 48-bit * 1792 * address on Crosstalk. * 1793 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 1794 * number) are used to select one of these 7 registers. The Widget * 1795 * number field is then derived from the W_NUM field for synthesizing * 1796 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 1797 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 1798 * are padded with zeros. Although the maximum Crosstalk space * 1799 * addressable by the Bedrock is thus the lower 16 GBytes per widget * 1800 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 1801 * space can be accessed. * 1802 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 1803 * Window number) are used to select one of these 7 registers. The * 1804 * Widget number field is then derived from the W_NUM field for * 1805 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 1806 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 1807 * field is used as Crosstalk[47], and remainder of the Crosstalk * 1808 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 1809 * Crosstalk space addressable by the Bedrock is thus the lower * 1810 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 1811 * of this space can be accessed. * 1812 * * 1813 ************************************************************************/ 1814 1815 1816 1817 1818#ifdef LITTLE_ENDIAN 1819 1820typedef union ii_itte7_u { 1821 bdrkreg_t ii_itte7_regval; 1822 struct { 1823 bdrkreg_t i_offset : 5; 1824 bdrkreg_t i_rsvd_1 : 3; 1825 bdrkreg_t i_w_num : 4; 1826 bdrkreg_t i_iosp : 1; 1827 bdrkreg_t i_rsvd : 51; 1828 } ii_itte7_fld_s; 1829} ii_itte7_u_t; 1830 1831#else 1832 1833typedef union ii_itte7_u { 1834 bdrkreg_t ii_itte7_regval; 1835 struct { 1836 bdrkreg_t i_rsvd : 51; 1837 bdrkreg_t i_iosp : 1; 1838 bdrkreg_t i_w_num : 4; 1839 bdrkreg_t i_rsvd_1 : 3; 1840 bdrkreg_t i_offset : 5; 1841 } ii_itte7_fld_s; 1842} ii_itte7_u_t; 1843 1844#endif 1845 1846 1847 1848 1849/************************************************************************ 1850 * * 1851 * Description: There are 9 instances of this register, one per * 1852 * actual widget in this implementation of Bedrock and Crossbow. * 1853 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1854 * refers to Crossbow's internal space. * 1855 * This register contains the state elements per widget that are * 1856 * necessary to manage the PIO flow control on Crosstalk and on the * 1857 * Router Network. See the PIO Flow Control chapter for a complete * 1858 * description of this register * 1859 * The SPUR_WR bit requires some explanation. When this register is * 1860 * written, the new value of the C field is captured in an internal * 1861 * register so the hardware can remember what the programmer wrote * 1862 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1863 * increments above this stored value, which indicates that there * 1864 * have been more responses received than requests sent. The SPUR_WR * 1865 * bit cannot be cleared until a value is written to the IPRBx * 1866 * register; the write will correct the C field and capture its new * 1867 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1868 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1869 * . * 1870 * * 1871 ************************************************************************/ 1872 1873 1874 1875 1876#ifdef LITTLE_ENDIAN 1877 1878typedef union ii_iprb0_u { 1879 bdrkreg_t ii_iprb0_regval; 1880 struct { 1881 bdrkreg_t i_c : 8; 1882 bdrkreg_t i_na : 14; 1883 bdrkreg_t i_rsvd_2 : 2; 1884 bdrkreg_t i_nb : 14; 1885 bdrkreg_t i_rsvd_1 : 2; 1886 bdrkreg_t i_m : 2; 1887 bdrkreg_t i_f : 1; 1888 bdrkreg_t i_of_cnt : 5; 1889 bdrkreg_t i_error : 1; 1890 bdrkreg_t i_rd_to : 1; 1891 bdrkreg_t i_spur_wr : 1; 1892 bdrkreg_t i_spur_rd : 1; 1893 bdrkreg_t i_rsvd : 11; 1894 bdrkreg_t i_mult_err : 1; 1895 } ii_iprb0_fld_s; 1896} ii_iprb0_u_t; 1897 1898#else 1899 1900typedef union ii_iprb0_u { 1901 bdrkreg_t ii_iprb0_regval; 1902 struct { 1903 bdrkreg_t i_mult_err : 1; 1904 bdrkreg_t i_rsvd : 11; 1905 bdrkreg_t i_spur_rd : 1; 1906 bdrkreg_t i_spur_wr : 1; 1907 bdrkreg_t i_rd_to : 1; 1908 bdrkreg_t i_error : 1; 1909 bdrkreg_t i_of_cnt : 5; 1910 bdrkreg_t i_f : 1; 1911 bdrkreg_t i_m : 2; 1912 bdrkreg_t i_rsvd_1 : 2; 1913 bdrkreg_t i_nb : 14; 1914 bdrkreg_t i_rsvd_2 : 2; 1915 bdrkreg_t i_na : 14; 1916 bdrkreg_t i_c : 8; 1917 } ii_iprb0_fld_s; 1918} ii_iprb0_u_t; 1919 1920#endif 1921 1922 1923 1924 1925/************************************************************************ 1926 * * 1927 * Description: There are 9 instances of this register, one per * 1928 * actual widget in this implementation of Bedrock and Crossbow. * 1929 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1930 * refers to Crossbow's internal space. * 1931 * This register contains the state elements per widget that are * 1932 * necessary to manage the PIO flow control on Crosstalk and on the * 1933 * Router Network. See the PIO Flow Control chapter for a complete * 1934 * description of this register * 1935 * The SPUR_WR bit requires some explanation. When this register is * 1936 * written, the new value of the C field is captured in an internal * 1937 * register so the hardware can remember what the programmer wrote * 1938 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1939 * increments above this stored value, which indicates that there * 1940 * have been more responses received than requests sent. The SPUR_WR * 1941 * bit cannot be cleared until a value is written to the IPRBx * 1942 * register; the write will correct the C field and capture its new * 1943 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1944 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1945 * . * 1946 * * 1947 ************************************************************************/ 1948 1949 1950 1951 1952#ifdef LITTLE_ENDIAN 1953 1954typedef union ii_iprb8_u { 1955 bdrkreg_t ii_iprb8_regval; 1956 struct { 1957 bdrkreg_t i_c : 8; 1958 bdrkreg_t i_na : 14; 1959 bdrkreg_t i_rsvd_2 : 2; 1960 bdrkreg_t i_nb : 14; 1961 bdrkreg_t i_rsvd_1 : 2; 1962 bdrkreg_t i_m : 2; 1963 bdrkreg_t i_f : 1; 1964 bdrkreg_t i_of_cnt : 5; 1965 bdrkreg_t i_error : 1; 1966 bdrkreg_t i_rd_to : 1; 1967 bdrkreg_t i_spur_wr : 1; 1968 bdrkreg_t i_spur_rd : 1; 1969 bdrkreg_t i_rsvd : 11; 1970 bdrkreg_t i_mult_err : 1; 1971 } ii_iprb8_fld_s; 1972} ii_iprb8_u_t; 1973 1974#else 1975 1976 1977typedef union ii_iprb8_u { 1978 bdrkreg_t ii_iprb8_regval; 1979 struct { 1980 bdrkreg_t i_mult_err : 1; 1981 bdrkreg_t i_rsvd : 11; 1982 bdrkreg_t i_spur_rd : 1; 1983 bdrkreg_t i_spur_wr : 1; 1984 bdrkreg_t i_rd_to : 1; 1985 bdrkreg_t i_error : 1; 1986 bdrkreg_t i_of_cnt : 5; 1987 bdrkreg_t i_f : 1; 1988 bdrkreg_t i_m : 2; 1989 bdrkreg_t i_rsvd_1 : 2; 1990 bdrkreg_t i_nb : 14; 1991 bdrkreg_t i_rsvd_2 : 2; 1992 bdrkreg_t i_na : 14; 1993 bdrkreg_t i_c : 8; 1994 } ii_iprb8_fld_s; 1995} ii_iprb8_u_t; 1996 1997#endif 1998 1999 2000 2001 2002/************************************************************************ 2003 * * 2004 * Description: There are 9 instances of this register, one per * 2005 * actual widget in this implementation of Bedrock and Crossbow. * 2006 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 2007 * refers to Crossbow's internal space. * 2008 * This register contains the state elements per widget that are * 2009 * necessary to manage the PIO flow control on Crosstalk and on the * 2010 * Router Network. See the PIO Flow Control chapter for a complete * 2011 * description of this register * 2012 * The SPUR_WR bit requires some explanation. When this register is * 2013 * written, the new value of the C field is captured in an internal * 2014 * register so the hardware can remember what the programmer wrote * 2015 * into the credit counter. The SPUR_WR bit sets whenever the C field * 2016 * increments above this stored value, which indicates that there * 2017 * have been more responses received than requests sent. The SPUR_WR * 2018 * bit cannot be cleared until a value is written to the IPRBx * 2019 * register; the write will correct the C field and capture its new * 2020 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 2021 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 2022 * . * 2023 * * 2024 ************************************************************************/ 2025 2026 2027 2028 2029#ifdef LITTLE_ENDIAN 2030 2031typedef union ii_iprb9_u { 2032 bdrkreg_t ii_iprb9_regval; 2033 struct { 2034 bdrkreg_t i_c : 8; 2035 bdrkreg_t i_na : 14; 2036 bdrkreg_t i_rsvd_2 : 2; 2037 bdrkreg_t i_nb : 14; 2038 bdrkreg_t i_rsvd_1 : 2; 2039 bdrkreg_t i_m : 2; 2040 bdrkreg_t i_f : 1; 2041 bdrkreg_t i_of_cnt : 5; 2042 bdrkreg_t i_error : 1; 2043 bdrkreg_t i_rd_to : 1; 2044 bdrkreg_t i_spur_wr : 1; 2045 bdrkreg_t i_spur_rd : 1; 2046 bdrkreg_t i_rsvd : 11; 2047 bdrkreg_t i_mult_err : 1; 2048 } ii_iprb9_fld_s; 2049} ii_iprb9_u_t; 2050 2051#else 2052 2053typedef union ii_iprb9_u { 2054 bdrkreg_t ii_iprb9_regval; 2055 struct { 2056 bdrkreg_t i_mult_err : 1; 2057 bdrkreg_t i_rsvd : 11; 2058 bdrkreg_t i_spur_rd : 1; 2059 bdrkreg_t i_spur_wr : 1; 2060 bdrkreg_t i_rd_to : 1; 2061 bdrkreg_t i_error : 1; 2062 bdrkreg_t i_of_cnt : 5; 2063 bdrkreg_t i_f : 1; 2064 bdrkreg_t i_m : 2; 2065 bdrkreg_t i_rsvd_1 : 2; 2066 bdrkreg_t i_nb : 14; 2067 bdrkreg_t i_rsvd_2 : 2; 2068 bdrkreg_t i_na : 14; 2069 bdrkreg_t i_c : 8; 2070 } ii_iprb9_fld_s; 2071} ii_iprb9_u_t; 2072 2073#endif 2074 2075 2076 2077/************************************************************************ 2078 * * 2079 * Description: There are 9 instances of this register, one per * 2080 * actual widget in this implementation of Bedrock and Crossbow. * 2081 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 2082 * refers to Crossbow's internal space. * 2083 * This register contains the state elements per widget that are * 2084 * necessary to manage the PIO flow control on Crosstalk and on the * 2085 * Router Network. See the PIO Flow Control chapter for a complete * 2086 * description of this register * 2087 * The SPUR_WR bit requires some explanation. When this register is * 2088 * written, the new value of the C field is captured in an internal * 2089 * register so the hardware can remember what the programmer wrote * 2090 * into the credit counter. The SPUR_WR bit sets whenever the C field * 2091 * increments above this stored value, which indicates that there * 2092 * have been more responses received than requests sent. The SPUR_WR * 2093 * bit cannot be cleared until a value is written to the IPRBx * 2094 * register; the write will correct the C field and capture its new * 2095 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 2096 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 2097 * . * 2098 * * 2099 ************************************************************************/ 2100 2101 2102 2103 2104#ifdef LITTLE_ENDIAN 2105 2106typedef union ii_iprba_u { 2107 bdrkreg_t ii_iprba_regval; 2108 struct { 2109 bdrkreg_t i_c : 8; 2110 bdrkreg_t i_na : 14; 2111 bdrkreg_t i_rsvd_2 : 2; 2112 bdrkreg_t i_nb : 14; 2113 bdrkreg_t i_rsvd_1 : 2; 2114 bdrkreg_t i_m : 2; 2115 bdrkreg_t i_f : 1; 2116 bdrkreg_t i_of_cnt : 5; 2117 bdrkreg_t i_error : 1; 2118 bdrkreg_t i_rd_to : 1; 2119 bdrkreg_t i_spur_wr : 1; 2120 bdrkreg_t i_spur_rd : 1; 2121 bdrkreg_t i_rsvd : 11; 2122 bdrkreg_t i_mult_err : 1; 2123 } ii_iprba_fld_s; 2124} ii_iprba_u_t; 2125 2126#else 2127 2128typedef union ii_iprba_u { 2129 bdrkreg_t ii_iprba_regval; 2130 struct { 2131 bdrkreg_t i_mult_err : 1; 2132 bdrkreg_t i_rsvd : 11; 2133 bdrkreg_t i_spur_rd : 1; 2134 bdrkreg_t i_spur_wr : 1; 2135 bdrkreg_t i_rd_to : 1; 2136 bdrkreg_t i_error : 1; 2137 bdrkreg_t i_of_cnt : 5; 2138 bdrkreg_t i_f : 1; 2139 bdrkreg_t i_m : 2; 2140 bdrkreg_t i_rsvd_1 : 2; 2141 bdrkreg_t i_nb : 14; 2142 bdrkreg_t i_rsvd_2 : 2; 2143 bdrkreg_t i_na : 14; 2144 bdrkreg_t i_c : 8; 2145 } ii_iprba_fld_s; 2146} ii_iprba_u_t; 2147 2148#endif 2149 2150 2151 2152 2153/************************************************************************ 2154 * * 2155 * Description: There are 9 instances of this register, one per * 2156 * actual widget in this implementation of Bedrock and Crossbow. * 2157 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 2158 * refers to Crossbow's internal space. * 2159 * This register contains the state elements per widget that are * 2160 * necessary to manage the PIO flow control on Crosstalk and on the * 2161 * Router Network. See the PIO Flow Control chapter for a complete * 2162 * description of this register * 2163 * The SPUR_WR bit requires some explanation. When this register is * 2164 * written, the new value of the C field is captured in an internal * 2165 * register so the hardware can remember what the programmer wrote * 2166 * into the credit counter. The SPUR_WR bit sets whenever the C field * 2167 * increments above this stored value, which indicates that there * 2168 * have been more responses received than requests sent. The SPUR_WR * 2169 * bit cannot be cleared until a value is written to the IPRBx * 2170 * register; the write will correct the C field and capture its new * 2171 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 2172 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 2173 * . * 2174 * * 2175 ************************************************************************/ 2176 2177 2178 2179 2180#ifdef LITTLE_ENDIAN 2181 2182typedef union ii_iprbb_u { 2183 bdrkreg_t ii_iprbb_regval; 2184 struct { 2185 bdrkreg_t i_c : 8; 2186 bdrkreg_t i_na : 14; 2187 bdrkreg_t i_rsvd_2 : 2; 2188 bdrkreg_t i_nb : 14; 2189 bdrkreg_t i_rsvd_1 : 2; 2190 bdrkreg_t i_m : 2; 2191 bdrkreg_t i_f : 1; 2192 bdrkreg_t i_of_cnt : 5; 2193 bdrkreg_t i_error : 1; 2194 bdrkreg_t i_rd_to : 1; 2195 bdrkreg_t i_spur_wr : 1; 2196 bdrkreg_t i_spur_rd : 1; 2197 bdrkreg_t i_rsvd : 11; 2198 bdrkreg_t i_mult_err : 1; 2199 } ii_iprbb_fld_s; 2200} ii_iprbb_u_t; 2201 2202#else 2203 2204typedef union ii_iprbb_u { 2205 bdrkreg_t ii_iprbb_regval; 2206 struct { 2207 bdrkreg_t i_mult_err : 1; 2208 bdrkreg_t i_rsvd : 11; 2209 bdrkreg_t i_spur_rd : 1; 2210 bdrkreg_t i_spur_wr : 1; 2211 bdrkreg_t i_rd_to : 1; 2212 bdrkreg_t i_error : 1; 2213 bdrkreg_t i_of_cnt : 5; 2214 bdrkreg_t i_f : 1; 2215 bdrkreg_t i_m : 2; 2216 bdrkreg_t i_rsvd_1 : 2; 2217 bdrkreg_t i_nb : 14; 2218 bdrkreg_t i_rsvd_2 : 2; 2219 bdrkreg_t i_na : 14; 2220 bdrkreg_t i_c : 8; 2221 } ii_iprbb_fld_s; 2222} ii_iprbb_u_t; 2223 2224#endif 2225 2226 2227 2228 2229/************************************************************************ 2230 * * 2231 * Description: There are 9 instances of this register, one per * 2232 * actual widget in this implementation of Bedrock and Crossbow. * 2233 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 2234 * refers to Crossbow's internal space. * 2235 * This register contains the state elements per widget that are * 2236 * necessary to manage the PIO flow control on Crosstalk and on the * 2237 * Router Network. See the PIO Flow Control chapter for a complete * 2238 * description of this register * 2239 * The SPUR_WR bit requires some explanation. When this register is * 2240 * written, the new value of the C field is captured in an internal * 2241 * register so the hardware can remember what the programmer wrote * 2242 * into the credit counter. The SPUR_WR bit sets whenever the C field * 2243 * increments above this stored value, which indicates that there * 2244 * have been more responses received than requests sent. The SPUR_WR * 2245 * bit cannot be cleared until a value is written to the IPRBx * 2246 * register; the write will correct the C field and capture its new * 2247 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 2248 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 2249 * . * 2250 * * 2251 ************************************************************************/ 2252 2253 2254 2255 2256#ifdef LITTLE_ENDIAN 2257 2258typedef union ii_iprbc_u { 2259 bdrkreg_t ii_iprbc_regval; 2260 struct { 2261 bdrkreg_t i_c : 8; 2262 bdrkreg_t i_na : 14; 2263 bdrkreg_t i_rsvd_2 : 2; 2264 bdrkreg_t i_nb : 14; 2265 bdrkreg_t i_rsvd_1 : 2; 2266 bdrkreg_t i_m : 2; 2267 bdrkreg_t i_f : 1; 2268 bdrkreg_t i_of_cnt : 5; 2269 bdrkreg_t i_error : 1; 2270 bdrkreg_t i_rd_to : 1; 2271 bdrkreg_t i_spur_wr : 1; 2272 bdrkreg_t i_spur_rd : 1; 2273 bdrkreg_t i_rsvd : 11; 2274 bdrkreg_t i_mult_err : 1; 2275 } ii_iprbc_fld_s; 2276} ii_iprbc_u_t; 2277 2278#else 2279 2280typedef union ii_iprbc_u { 2281 bdrkreg_t ii_iprbc_regval; 2282 struct { 2283 bdrkreg_t i_mult_err : 1; 2284 bdrkreg_t i_rsvd : 11; 2285 bdrkreg_t i_spur_rd : 1; 2286 bdrkreg_t i_spur_wr : 1; 2287 bdrkreg_t i_rd_to : 1; 2288 bdrkreg_t i_error : 1; 2289 bdrkreg_t i_of_cnt : 5; 2290 bdrkreg_t i_f : 1; 2291 bdrkreg_t i_m : 2; 2292 bdrkreg_t i_rsvd_1 : 2; 2293 bdrkreg_t i_nb : 14; 2294 bdrkreg_t i_rsvd_2 : 2; 2295 bdrkreg_t i_na : 14; 2296 bdrkreg_t i_c : 8; 2297 } ii_iprbc_fld_s; 2298} ii_iprbc_u_t; 2299 2300#endif 2301 2302 2303 2304 2305/************************************************************************ 2306 * * 2307 * Description: There are 9 instances of this register, one per * 2308 * actual widget in this implementation of Bedrock and Crossbow. * 2309 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 2310 * refers to Crossbow's internal space. * 2311 * This register contains the state elements per widget that are * 2312 * necessary to manage the PIO flow control on Crosstalk and on the * 2313 * Router Network. See the PIO Flow Control chapter for a complete * 2314 * description of this register * 2315 * The SPUR_WR bit requires some explanation. When this register is * 2316 * written, the new value of the C field is captured in an internal * 2317 * register so the hardware can remember what the programmer wrote * 2318 * into the credit counter. The SPUR_WR bit sets whenever the C field * 2319 * increments above this stored value, which indicates that there * 2320 * have been more responses received than requests sent. The SPUR_WR * 2321 * bit cannot be cleared until a value is written to the IPRBx * 2322 * register; the write will correct the C field and capture its new * 2323 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 2324 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 2325 * . * 2326 * * 2327 ************************************************************************/ 2328 2329 2330 2331 2332#ifdef LITTLE_ENDIAN 2333 2334typedef union ii_iprbd_u { 2335 bdrkreg_t ii_iprbd_regval; 2336 struct { 2337 bdrkreg_t i_c : 8; 2338 bdrkreg_t i_na : 14; 2339 bdrkreg_t i_rsvd_2 : 2; 2340 bdrkreg_t i_nb : 14; 2341 bdrkreg_t i_rsvd_1 : 2; 2342 bdrkreg_t i_m : 2; 2343 bdrkreg_t i_f : 1; 2344 bdrkreg_t i_of_cnt : 5; 2345 bdrkreg_t i_error : 1; 2346 bdrkreg_t i_rd_to : 1; 2347 bdrkreg_t i_spur_wr : 1; 2348 bdrkreg_t i_spur_rd : 1; 2349 bdrkreg_t i_rsvd : 11; 2350 bdrkreg_t i_mult_err : 1; 2351 } ii_iprbd_fld_s; 2352} ii_iprbd_u_t; 2353 2354#else 2355 2356typedef union ii_iprbd_u { 2357 bdrkreg_t ii_iprbd_regval; 2358 struct { 2359 bdrkreg_t i_mult_err : 1; 2360 bdrkreg_t i_rsvd : 11; 2361 bdrkreg_t i_spur_rd : 1; 2362 bdrkreg_t i_spur_wr : 1; 2363 bdrkreg_t i_rd_to : 1; 2364 bdrkreg_t i_error : 1; 2365 bdrkreg_t i_of_cnt : 5; 2366 bdrkreg_t i_f : 1; 2367 bdrkreg_t i_m : 2; 2368 bdrkreg_t i_rsvd_1 : 2; 2369 bdrkreg_t i_nb : 14; 2370 bdrkreg_t i_rsvd_2 : 2; 2371 bdrkreg_t i_na : 14; 2372 bdrkreg_t i_c : 8; 2373 } ii_iprbd_fld_s; 2374} ii_iprbd_u_t; 2375 2376#endif 2377 2378 2379 2380 2381/************************************************************************ 2382 * * 2383 * Description: There are 9 instances of this register, one per * 2384 * actual widget in this implementation of Bedrock and Crossbow. * 2385 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 2386 * refers to Crossbow's internal space. * 2387 * This register contains the state elements per widget that are * 2388 * necessary to manage the PIO flow control on Crosstalk and on the * 2389 * Router Network. See the PIO Flow Control chapter for a complete * 2390 * description of this register * 2391 * The SPUR_WR bit requires some explanation. When this register is * 2392 * written, the new value of the C field is captured in an internal * 2393 * register so the hardware can remember what the programmer wrote * 2394 * into the credit counter. The SPUR_WR bit sets whenever the C field * 2395 * increments above this stored value, which indicates that there * 2396 * have been more responses received than requests sent. The SPUR_WR * 2397 * bit cannot be cleared until a value is written to the IPRBx * 2398 * register; the write will correct the C field and capture its new * 2399 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 2400 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 2401 * . * 2402 * * 2403 ************************************************************************/ 2404 2405 2406 2407 2408#ifdef LITTLE_ENDIAN 2409 2410typedef union ii_iprbe_u { 2411 bdrkreg_t ii_iprbe_regval; 2412 struct { 2413 bdrkreg_t i_c : 8; 2414 bdrkreg_t i_na : 14; 2415 bdrkreg_t i_rsvd_2 : 2; 2416 bdrkreg_t i_nb : 14; 2417 bdrkreg_t i_rsvd_1 : 2; 2418 bdrkreg_t i_m : 2; 2419 bdrkreg_t i_f : 1; 2420 bdrkreg_t i_of_cnt : 5; 2421 bdrkreg_t i_error : 1; 2422 bdrkreg_t i_rd_to : 1; 2423 bdrkreg_t i_spur_wr : 1; 2424 bdrkreg_t i_spur_rd : 1; 2425 bdrkreg_t i_rsvd : 11; 2426 bdrkreg_t i_mult_err : 1; 2427 } ii_iprbe_fld_s; 2428} ii_iprbe_u_t; 2429 2430#else 2431 2432typedef union ii_iprbe_u { 2433 bdrkreg_t ii_iprbe_regval; 2434 struct { 2435 bdrkreg_t i_mult_err : 1; 2436 bdrkreg_t i_rsvd : 11; 2437 bdrkreg_t i_spur_rd : 1; 2438 bdrkreg_t i_spur_wr : 1; 2439 bdrkreg_t i_rd_to : 1; 2440 bdrkreg_t i_error : 1; 2441 bdrkreg_t i_of_cnt : 5; 2442 bdrkreg_t i_f : 1; 2443 bdrkreg_t i_m : 2; 2444 bdrkreg_t i_rsvd_1 : 2; 2445 bdrkreg_t i_nb : 14; 2446 bdrkreg_t i_rsvd_2 : 2; 2447 bdrkreg_t i_na : 14; 2448 bdrkreg_t i_c : 8; 2449 } ii_iprbe_fld_s; 2450} ii_iprbe_u_t; 2451 2452#endif 2453 2454 2455 2456 2457/************************************************************************ 2458 * * 2459 * Description: There are 9 instances of this register, one per * 2460 * actual widget in this implementation of Bedrock and Crossbow. * 2461 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 2462 * refers to Crossbow's internal space. * 2463 * This register contains the state elements per widget that are * 2464 * necessary to manage the PIO flow control on Crosstalk and on the * 2465 * Router Network. See the PIO Flow Control chapter for a complete * 2466 * description of this register * 2467 * The SPUR_WR bit requires some explanation. When this register is * 2468 * written, the new value of the C field is captured in an internal * 2469 * register so the hardware can remember what the programmer wrote * 2470 * into the credit counter. The SPUR_WR bit sets whenever the C field * 2471 * increments above this stored value, which indicates that there * 2472 * have been more responses received than requests sent. The SPUR_WR * 2473 * bit cannot be cleared until a value is written to the IPRBx * 2474 * register; the write will correct the C field and capture its new * 2475 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 2476 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 2477 * . * 2478 * * 2479 ************************************************************************/ 2480 2481 2482 2483 2484#ifdef LITTLE_ENDIAN 2485 2486typedef union ii_iprbf_u { 2487 bdrkreg_t ii_iprbf_regval; 2488 struct { 2489 bdrkreg_t i_c : 8; 2490 bdrkreg_t i_na : 14; 2491 bdrkreg_t i_rsvd_2 : 2; 2492 bdrkreg_t i_nb : 14; 2493 bdrkreg_t i_rsvd_1 : 2; 2494 bdrkreg_t i_m : 2; 2495 bdrkreg_t i_f : 1; 2496 bdrkreg_t i_of_cnt : 5; 2497 bdrkreg_t i_error : 1; 2498 bdrkreg_t i_rd_to : 1; 2499 bdrkreg_t i_spur_wr : 1; 2500 bdrkreg_t i_spur_rd : 1; 2501 bdrkreg_t i_rsvd : 11; 2502 bdrkreg_t i_mult_err : 1; 2503 } ii_iprbe_fld_s; 2504} ii_iprbf_u_t; 2505 2506#else 2507 2508typedef union ii_iprbf_u { 2509 bdrkreg_t ii_iprbf_regval; 2510 struct { 2511 bdrkreg_t i_mult_err : 1; 2512 bdrkreg_t i_rsvd : 11; 2513 bdrkreg_t i_spur_rd : 1; 2514 bdrkreg_t i_spur_wr : 1; 2515 bdrkreg_t i_rd_to : 1; 2516 bdrkreg_t i_error : 1; 2517 bdrkreg_t i_of_cnt : 5; 2518 bdrkreg_t i_f : 1; 2519 bdrkreg_t i_m : 2; 2520 bdrkreg_t i_rsvd_1 : 2; 2521 bdrkreg_t i_nb : 14; 2522 bdrkreg_t i_rsvd_2 : 2; 2523 bdrkreg_t i_na : 14; 2524 bdrkreg_t i_c : 8; 2525 } ii_iprbf_fld_s; 2526} ii_iprbf_u_t; 2527 2528#endif 2529 2530 2531 2532 2533/************************************************************************ 2534 * * 2535 * This register specifies the timeout value to use for monitoring * 2536 * Crosstalk credits which are used outbound to Crosstalk. An * 2537 * internal counter called the Crosstalk Credit Timeout Counter * 2538 * increments every 128 II clocks. The counter starts counting * 2539 * anytime the credit count drops below a threshold, and resets to * 2540 * zero (stops counting) anytime the credit count is at or above the * 2541 * threshold. The threshold is 1 credit in direct connect mode and 2 * 2542 * in Crossbow connect mode. When the internal Crosstalk Credit * 2543 * Timeout Counter reaches the value programmed in this register, a * 2544 * Crosstalk Credit Timeout has occurred. The internal counter is not * 2545 * readable from software, and stops counting at its maximum value, * 2546 * so it cannot cause more than one interrupt. * 2547 * * 2548 ************************************************************************/ 2549 2550 2551 2552 2553#ifdef LITTLE_ENDIAN 2554 2555typedef union ii_ixcc_u { 2556 bdrkreg_t ii_ixcc_regval; 2557 struct { 2558 bdrkreg_t i_time_out : 26; 2559 bdrkreg_t i_rsvd : 38; 2560 } ii_ixcc_fld_s; 2561} ii_ixcc_u_t; 2562 2563#else 2564 2565typedef union ii_ixcc_u { 2566 bdrkreg_t ii_ixcc_regval; 2567 struct { 2568 bdrkreg_t i_rsvd : 38; 2569 bdrkreg_t i_time_out : 26; 2570 } ii_ixcc_fld_s; 2571} ii_ixcc_u_t; 2572 2573#endif 2574 2575 2576 2577/************************************************************************ 2578 * * 2579 * Description: This register qualifies all the PIO and DMA * 2580 * operations launched from widget 0 towards the Bedrock. In * 2581 * addition, it also qualifies accesses by the BTE streams. * 2582 * The bits in each field of this register are cleared by the Bedrock * 2583 * upon detection of an error which requires widget 0 or the BTE * 2584 * streams to be terminated. Whether or not widget x has access * 2585 * rights to this Bedrock is determined by an AND of the device * 2586 * enable bit in the appropriate field of this register and bit 0 in * 2587 * the Wx_IAC field. The bits in this field are set by writing a 1 to * 2588 * them. Incoming replies from Crosstalk are not subject to this * 2589 * access control mechanism. * 2590 * * 2591 ************************************************************************/ 2592 2593 2594 2595 2596#ifdef LITTLE_ENDIAN 2597 2598typedef union ii_imem_u { 2599 bdrkreg_t ii_imem_regval; 2600 struct { 2601 bdrkreg_t i_w0_esd : 1; 2602 bdrkreg_t i_rsvd_3 : 3; 2603 bdrkreg_t i_b0_esd : 1; 2604 bdrkreg_t i_rsvd_2 : 3; 2605 bdrkreg_t i_b1_esd : 1; 2606 bdrkreg_t i_rsvd_1 : 3; 2607 bdrkreg_t i_clr_precise : 1; 2608 bdrkreg_t i_rsvd : 51; 2609 } ii_imem_fld_s; 2610} ii_imem_u_t; 2611 2612#else 2613 2614typedef union ii_imem_u { 2615 bdrkreg_t ii_imem_regval; 2616 struct { 2617 bdrkreg_t i_rsvd : 51; 2618 bdrkreg_t i_clr_precise : 1; 2619 bdrkreg_t i_rsvd_1 : 3; 2620 bdrkreg_t i_b1_esd : 1; 2621 bdrkreg_t i_rsvd_2 : 3; 2622 bdrkreg_t i_b0_esd : 1; 2623 bdrkreg_t i_rsvd_3 : 3; 2624 bdrkreg_t i_w0_esd : 1; 2625 } ii_imem_fld_s; 2626} ii_imem_u_t; 2627 2628#endif 2629 2630 2631 2632 2633/************************************************************************ 2634 * * 2635 * Description: This register specifies the timeout value to use for * 2636 * monitoring Crosstalk tail flits coming into the Bedrock in the * 2637 * TAIL_TO field. An internal counter associated with this register * 2638 * is incremented every 128 II internal clocks (7 bits). The counter * 2639 * starts counting anytime a header micropacket is received and stops * 2640 * counting (and resets to zero) any time a micropacket with a Tail * 2641 * bit is received. Once the counter reaches the threshold value * 2642 * programmed in this register, it generates an interrupt to the * 2643 * processor that is programmed into the IIDSR. The counter saturates * 2644 * (does not roll over) at its maximum value, so it cannot cause * 2645 * another interrupt until after it is cleared. * 2646 * The register also contains the Read Response Timeout values. The * 2647 * Prescalar is 23 bits, and counts II clocks. An internal counter * 2648 * increments on every II clock and when it reaches the value in the * 2649 * Prescalar field, all IPRTE registers with their valid bits set * 2650 * have their Read Response timers bumped. Whenever any of them match * 2651 * the value in the RRSP_TO field, a Read Response Timeout has * 2652 * occurred, and error handling occurs as described in the Error * 2653 * Handling section of this document. * 2654 * * 2655 ************************************************************************/ 2656 2657 2658 2659 2660#ifdef LITTLE_ENDIAN 2661 2662typedef union ii_ixtt_u { 2663 bdrkreg_t ii_ixtt_regval; 2664 struct { 2665 bdrkreg_t i_tail_to : 26; 2666 bdrkreg_t i_rsvd_1 : 6; 2667 bdrkreg_t i_rrsp_ps : 23; 2668 bdrkreg_t i_rrsp_to : 5; 2669 bdrkreg_t i_rsvd : 4; 2670 } ii_ixtt_fld_s; 2671} ii_ixtt_u_t; 2672 2673#else 2674 2675typedef union ii_ixtt_u { 2676 bdrkreg_t ii_ixtt_regval; 2677 struct { 2678 bdrkreg_t i_rsvd : 4; 2679 bdrkreg_t i_rrsp_to : 5; 2680 bdrkreg_t i_rrsp_ps : 23; 2681 bdrkreg_t i_rsvd_1 : 6; 2682 bdrkreg_t i_tail_to : 26; 2683 } ii_ixtt_fld_s; 2684} ii_ixtt_u_t; 2685 2686#endif 2687 2688 2689 2690 2691/************************************************************************ 2692 * * 2693 * Writing a 1 to the fields of this register clears the appropriate * 2694 * error bits in other areas of Bedrock_II. Note that when the * 2695 * E_PRB_x bits are used to clear error bits in PRB registers, * 2696 * SPUR_RD and SPUR_WR may persist, because they require additional * 2697 * action to clear them. See the IPRBx and IXSS Register * 2698 * specifications. * 2699 * * 2700 ************************************************************************/ 2701 2702 2703 2704 2705#ifdef LITTLE_ENDIAN 2706 2707typedef union ii_ieclr_u { 2708 bdrkreg_t ii_ieclr_regval; 2709 struct { 2710 bdrkreg_t i_e_prb_0 : 1; 2711 bdrkreg_t i_rsvd : 7; 2712 bdrkreg_t i_e_prb_8 : 1; 2713 bdrkreg_t i_e_prb_9 : 1; 2714 bdrkreg_t i_e_prb_a : 1; 2715 bdrkreg_t i_e_prb_b : 1; 2716 bdrkreg_t i_e_prb_c : 1; 2717 bdrkreg_t i_e_prb_d : 1; 2718 bdrkreg_t i_e_prb_e : 1; 2719 bdrkreg_t i_e_prb_f : 1; 2720 bdrkreg_t i_e_crazy : 1; 2721 bdrkreg_t i_e_bte_0 : 1; 2722 bdrkreg_t i_e_bte_1 : 1; 2723 bdrkreg_t i_reserved_1 : 9; 2724 bdrkreg_t i_ii_internal : 1; 2725 bdrkreg_t i_spur_rd_hdr : 1; 2726 bdrkreg_t i_pi0_forward_int : 1; 2727 bdrkreg_t i_pi1_forward_int : 1; 2728 bdrkreg_t i_reserved : 32; 2729 } ii_ieclr_fld_s; 2730} ii_ieclr_u_t; 2731 2732#else 2733 2734typedef union ii_ieclr_u { 2735 bdrkreg_t ii_ieclr_regval; 2736 struct { 2737 bdrkreg_t i_reserved : 32; 2738 bdrkreg_t i_pi1_forward_int : 1; 2739 bdrkreg_t i_pi0_forward_int : 1; 2740 bdrkreg_t i_spur_rd_hdr : 1; 2741 bdrkreg_t i_ii_internal : 1; 2742 bdrkreg_t i_reserved_1 : 9; 2743 bdrkreg_t i_e_bte_1 : 1; 2744 bdrkreg_t i_e_bte_0 : 1; 2745 bdrkreg_t i_e_crazy : 1; 2746 bdrkreg_t i_e_prb_f : 1; 2747 bdrkreg_t i_e_prb_e : 1; 2748 bdrkreg_t i_e_prb_d : 1; 2749 bdrkreg_t i_e_prb_c : 1; 2750 bdrkreg_t i_e_prb_b : 1; 2751 bdrkreg_t i_e_prb_a : 1; 2752 bdrkreg_t i_e_prb_9 : 1; 2753 bdrkreg_t i_e_prb_8 : 1; 2754 bdrkreg_t i_rsvd : 7; 2755 bdrkreg_t i_e_prb_0 : 1; 2756 } ii_ieclr_fld_s; 2757} ii_ieclr_u_t; 2758 2759#endif 2760 2761 2762 2763 2764 2765/************************************************************************ 2766 * * 2767 * This register controls both BTEs. SOFT_RESET is intended for * 2768 * recovery after an error. COUNT controls the total number of CRBs * 2769 * that both BTEs (combined) can use, which affects total BTE * 2770 * bandwidth. * 2771 * * 2772 ************************************************************************/ 2773 2774 2775 2776 2777#ifdef LITTLE_ENDIAN 2778 2779typedef union ii_ibcr_u { 2780 bdrkreg_t ii_ibcr_regval; 2781 struct { 2782 bdrkreg_t i_count : 4; 2783 bdrkreg_t i_rsvd_1 : 4; 2784 bdrkreg_t i_soft_reset : 1; 2785 bdrkreg_t i_rsvd : 55; 2786 } ii_ibcr_fld_s; 2787} ii_ibcr_u_t; 2788 2789#else 2790 2791typedef union ii_ibcr_u { 2792 bdrkreg_t ii_ibcr_regval; 2793 struct { 2794 bdrkreg_t i_rsvd : 55; 2795 bdrkreg_t i_soft_reset : 1; 2796 bdrkreg_t i_rsvd_1 : 4; 2797 bdrkreg_t i_count : 4; 2798 } ii_ibcr_fld_s; 2799} ii_ibcr_u_t; 2800 2801#endif 2802 2803 2804 2805 2806/************************************************************************ 2807 * * 2808 * This register contains the header of a spurious read response * 2809 * received from Crosstalk. A spurious read response is defined as a * 2810 * read response received by II from a widget for which (1) the SIDN * 2811 * has a value between 1 and 7, inclusive (II never sends requests to * 2812 * these widgets (2) there is no valid IPRTE register which * 2813 * corresponds to the TNUM, or (3) the widget indicated in SIDN is * 2814 * not the same as the widget recorded in the IPRTE register * 2815 * referenced by the TNUM. If this condition is true, and if the * 2816 * IXSS[VALID] bit is clear, then the header of the spurious read * 2817 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The * 2818 * errant header is thereby captured, and no further spurious read * 2819 * respones are captured until IXSS[VALID] is cleared by setting the * 2820 * appropriate bit in IECLR.Everytime a spurious read response is * 2821 * detected, the SPUR_RD bit of the PRB corresponding to the incoming * 2822 * message's SIDN field is set. This always happens, regarless of * 2823 * whether a header is captured. The programmer should check * 2824 * IXSM[SIDN] to determine which widget sent the spurious response, * 2825 * because there may be more than one SPUR_RD bit set in the PRB * 2826 * registers. The widget indicated by IXSM[SIDN] was the first * 2827 * spurious read response to be received since the last time * 2828 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB * 2829 * will be set. Any SPUR_RD bits in any other PRB registers indicate * 2830 * spurious messages from other widets which were detected after the * 2831 * header was captured.. * 2832 * * 2833 ************************************************************************/ 2834 2835 2836 2837 2838#ifdef LITTLE_ENDIAN 2839 2840typedef union ii_ixsm_u { 2841 bdrkreg_t ii_ixsm_regval; 2842 struct { 2843 bdrkreg_t i_byte_en : 32; 2844 bdrkreg_t i_reserved : 1; 2845 bdrkreg_t i_tag : 3; 2846 bdrkreg_t i_alt_pactyp : 4; 2847 bdrkreg_t i_bo : 1; 2848 bdrkreg_t i_error : 1; 2849 bdrkreg_t i_vbpm : 1; 2850 bdrkreg_t i_gbr : 1; 2851 bdrkreg_t i_ds : 2; 2852 bdrkreg_t i_ct : 1; 2853 bdrkreg_t i_tnum : 5; 2854 bdrkreg_t i_pactyp : 4; 2855 bdrkreg_t i_sidn : 4; 2856 bdrkreg_t i_didn : 4; 2857 } ii_ixsm_fld_s; 2858} ii_ixsm_u_t; 2859 2860#else 2861 2862typedef union ii_ixsm_u { 2863 bdrkreg_t ii_ixsm_regval; 2864 struct { 2865 bdrkreg_t i_didn : 4; 2866 bdrkreg_t i_sidn : 4; 2867 bdrkreg_t i_pactyp : 4; 2868 bdrkreg_t i_tnum : 5; 2869 bdrkreg_t i_ct : 1; 2870 bdrkreg_t i_ds : 2; 2871 bdrkreg_t i_gbr : 1; 2872 bdrkreg_t i_vbpm : 1; 2873 bdrkreg_t i_error : 1; 2874 bdrkreg_t i_bo : 1; 2875 bdrkreg_t i_alt_pactyp : 4; 2876 bdrkreg_t i_tag : 3; 2877 bdrkreg_t i_reserved : 1; 2878 bdrkreg_t i_byte_en : 32; 2879 } ii_ixsm_fld_s; 2880} ii_ixsm_u_t; 2881 2882#endif 2883 2884 2885 2886 2887/************************************************************************ 2888 * * 2889 * This register contains the sideband bits of a spurious read * 2890 * response received from Crosstalk. * 2891 * * 2892 ************************************************************************/ 2893 2894 2895 2896 2897#ifdef LITTLE_ENDIAN 2898 2899typedef union ii_ixss_u { 2900 bdrkreg_t ii_ixss_regval; 2901 struct { 2902 bdrkreg_t i_sideband : 8; 2903 bdrkreg_t i_rsvd : 55; 2904 bdrkreg_t i_valid : 1; 2905 } ii_ixss_fld_s; 2906} ii_ixss_u_t; 2907 2908#else 2909 2910typedef union ii_ixss_u { 2911 bdrkreg_t ii_ixss_regval; 2912 struct { 2913 bdrkreg_t i_valid : 1; 2914 bdrkreg_t i_rsvd : 55; 2915 bdrkreg_t i_sideband : 8; 2916 } ii_ixss_fld_s; 2917} ii_ixss_u_t; 2918 2919#endif 2920 2921 2922 2923 2924/************************************************************************ 2925 * * 2926 * This register enables software to access the II LLP's test port. * 2927 * Refer to the LLP 2.5 documentation for an explanation of the test * 2928 * port. Software can write to this register to program the values * 2929 * for the control fields (TestErrCapture, TestClear, TestFlit, * 2930 * TestMask and TestSeed). Similarly, software can read from this * 2931 * register to obtain the values of the test port's status outputs * 2932 * (TestCBerr, TestValid and TestData). * 2933 * * 2934 ************************************************************************/ 2935 2936 2937 2938 2939#ifdef LITTLE_ENDIAN 2940 2941typedef union ii_ilct_u { 2942 bdrkreg_t ii_ilct_regval; 2943 struct { 2944 bdrkreg_t i_test_seed : 20; 2945 bdrkreg_t i_test_mask : 8; 2946 bdrkreg_t i_test_data : 20; 2947 bdrkreg_t i_test_valid : 1; 2948 bdrkreg_t i_test_cberr : 1; 2949 bdrkreg_t i_test_flit : 3; 2950 bdrkreg_t i_test_clear : 1; 2951 bdrkreg_t i_test_err_capture : 1; 2952 bdrkreg_t i_rsvd : 9; 2953 } ii_ilct_fld_s; 2954} ii_ilct_u_t; 2955 2956#else 2957 2958typedef union ii_ilct_u { 2959 bdrkreg_t ii_ilct_regval; 2960 struct { 2961 bdrkreg_t i_rsvd : 9; 2962 bdrkreg_t i_test_err_capture : 1; 2963 bdrkreg_t i_test_clear : 1; 2964 bdrkreg_t i_test_flit : 3; 2965 bdrkreg_t i_test_cberr : 1; 2966 bdrkreg_t i_test_valid : 1; 2967 bdrkreg_t i_test_data : 20; 2968 bdrkreg_t i_test_mask : 8; 2969 bdrkreg_t i_test_seed : 20; 2970 } ii_ilct_fld_s; 2971} ii_ilct_u_t; 2972 2973#endif 2974 2975 2976 2977 2978/************************************************************************ 2979 * * 2980 * If the II detects an illegal incoming Duplonet packet (request or * 2981 * reply) when VALID==0 in the IIEPH1 register, then it saves the * 2982 * contents of the packet's header flit in the IIEPH1 and IIEPH2 * 2983 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, * 2984 * and assigns a value to the ERR_TYPE field which indicates the * 2985 * specific nature of the error. The II recognizes four different * 2986 * types of errors: short request packets (ERR_TYPE==2), short reply * 2987 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long * 2988 * reply packets (ERR_TYPE==5). The encodings for these types of * 2989 * errors were chosen to be consistent with the same types of errors * 2990 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in * 2991 * the LB unit). If the II detects an illegal incoming Duplonet * 2992 * packet when VALID==1 in the IIEPH1 register, then it merely sets * 2993 * the OVERRUN bit to indicate that a subsequent error has happened, * 2994 * and does nothing further. * 2995 * * 2996 ************************************************************************/ 2997 2998 2999 3000 3001#ifdef LITTLE_ENDIAN 3002 3003typedef union ii_iieph1_u { 3004 bdrkreg_t ii_iieph1_regval; 3005 struct { 3006 bdrkreg_t i_command : 7; 3007 bdrkreg_t i_rsvd_5 : 1; 3008 bdrkreg_t i_suppl : 11; 3009 bdrkreg_t i_rsvd_4 : 1; 3010 bdrkreg_t i_source : 11; 3011 bdrkreg_t i_rsvd_3 : 1; 3012 bdrkreg_t i_err_type : 4; 3013 bdrkreg_t i_rsvd_2 : 4; 3014 bdrkreg_t i_overrun : 1; 3015 bdrkreg_t i_rsvd_1 : 3; 3016 bdrkreg_t i_valid : 1; 3017 bdrkreg_t i_rsvd : 19; 3018 } ii_iieph1_fld_s; 3019} ii_iieph1_u_t; 3020 3021#else 3022 3023typedef union ii_iieph1_u { 3024 bdrkreg_t ii_iieph1_regval; 3025 struct { 3026 bdrkreg_t i_rsvd : 19; 3027 bdrkreg_t i_valid : 1; 3028 bdrkreg_t i_rsvd_1 : 3; 3029 bdrkreg_t i_overrun : 1; 3030 bdrkreg_t i_rsvd_2 : 4; 3031 bdrkreg_t i_err_type : 4; 3032 bdrkreg_t i_rsvd_3 : 1; 3033 bdrkreg_t i_source : 11; 3034 bdrkreg_t i_rsvd_4 : 1; 3035 bdrkreg_t i_suppl : 11; 3036 bdrkreg_t i_rsvd_5 : 1; 3037 bdrkreg_t i_command : 7; 3038 } ii_iieph1_fld_s; 3039} ii_iieph1_u_t; 3040 3041#endif 3042 3043 3044 3045 3046/************************************************************************ 3047 * * 3048 * This register holds the Address field from the header flit of an * 3049 * incoming erroneous Duplonet packet, along with the tail bit which * 3050 * accompanied this header flit. This register is essentially an * 3051 * extension of IIEPH1. Two registers were necessary because the 64 * 3052 * bits available in only a single register were insufficient to * 3053 * capture the entire header flit of an erroneous packet. * 3054 * * 3055 ************************************************************************/ 3056 3057 3058 3059 3060#ifdef LITTLE_ENDIAN 3061 3062typedef union ii_iieph2_u { 3063 bdrkreg_t ii_iieph2_regval; 3064 struct { 3065 bdrkreg_t i_address : 38; 3066 bdrkreg_t i_rsvd_1 : 2; 3067 bdrkreg_t i_tail : 1; 3068 bdrkreg_t i_rsvd : 23; 3069 } ii_iieph2_fld_s; 3070} ii_iieph2_u_t; 3071 3072#else 3073 3074typedef union ii_iieph2_u { 3075 bdrkreg_t ii_iieph2_regval; 3076 struct { 3077 bdrkreg_t i_rsvd : 23; 3078 bdrkreg_t i_tail : 1; 3079 bdrkreg_t i_rsvd_1 : 2; 3080 bdrkreg_t i_address : 38; 3081 } ii_iieph2_fld_s; 3082} ii_iieph2_u_t; 3083 3084#endif 3085 3086 3087 3088 3089/************************************************************************ 3090 * * 3091 * A write to this register causes a particular field in the * 3092 * corresponding widget's PRB entry to be adjusted up or down by 1. * 3093 * This counter should be used when recovering from error and reset * 3094 * conditions. Note that software would be capable of causing * 3095 * inadvertent overflow or underflow of these counters. * 3096 * * 3097 ************************************************************************/ 3098 3099 3100 3101 3102#ifdef LITTLE_ENDIAN 3103 3104typedef union ii_ipca_u { 3105 bdrkreg_t ii_ipca_regval; 3106 struct { 3107 bdrkreg_t i_wid : 4; 3108 bdrkreg_t i_adjust : 1; 3109 bdrkreg_t i_rsvd_1 : 3; 3110 bdrkreg_t i_field : 2; 3111 bdrkreg_t i_rsvd : 54; 3112 } ii_ipca_fld_s; 3113} ii_ipca_u_t; 3114 3115#else 3116 3117typedef union ii_ipca_u { 3118 bdrkreg_t ii_ipca_regval; 3119 struct { 3120 bdrkreg_t i_rsvd : 54; 3121 bdrkreg_t i_field : 2; 3122 bdrkreg_t i_rsvd_1 : 3; 3123 bdrkreg_t i_adjust : 1; 3124 bdrkreg_t i_wid : 4; 3125 } ii_ipca_fld_s; 3126} ii_ipca_u_t; 3127 3128#endif 3129 3130 3131 3132 3133/************************************************************************ 3134 * * 3135 * There are 8 instances of this register. This register contains * 3136 * the information that the II has to remember once it has launched a * 3137 * PIO Read operation. The contents are used to form the correct * 3138 * Router Network packet and direct the Crosstalk reply to the * 3139 * appropriate processor. * 3140 * * 3141 ************************************************************************/ 3142 3143 3144 3145 3146#ifdef LITTLE_ENDIAN 3147 3148typedef union ii_iprte0_u { 3149 bdrkreg_t ii_iprte0_regval; 3150 struct { 3151 bdrkreg_t i_rsvd_1 : 3; 3152 bdrkreg_t i_addr : 38; 3153 bdrkreg_t i_init : 3; 3154 bdrkreg_t i_source : 8; 3155 bdrkreg_t i_rsvd : 2; 3156 bdrkreg_t i_widget : 4; 3157 bdrkreg_t i_to_cnt : 5; 3158 bdrkreg_t i_vld : 1; 3159 } ii_iprte0_fld_s; 3160} ii_iprte0_u_t; 3161 3162#else 3163 3164typedef union ii_iprte0_u { 3165 bdrkreg_t ii_iprte0_regval; 3166 struct { 3167 bdrkreg_t i_vld : 1; 3168 bdrkreg_t i_to_cnt : 5; 3169 bdrkreg_t i_widget : 4; 3170 bdrkreg_t i_rsvd : 2; 3171 bdrkreg_t i_source : 8; 3172 bdrkreg_t i_init : 3; 3173 bdrkreg_t i_addr : 38; 3174 bdrkreg_t i_rsvd_1 : 3; 3175 } ii_iprte0_fld_s; 3176} ii_iprte0_u_t; 3177 3178#endif 3179 3180 3181 3182 3183/************************************************************************ 3184 * * 3185 * There are 8 instances of this register. This register contains * 3186 * the information that the II has to remember once it has launched a * 3187 * PIO Read operation. The contents are used to form the correct * 3188 * Router Network packet and direct the Crosstalk reply to the * 3189 * appropriate processor. * 3190 * * 3191 ************************************************************************/ 3192 3193 3194 3195 3196#ifdef LITTLE_ENDIAN 3197 3198typedef union ii_iprte1_u { 3199 bdrkreg_t ii_iprte1_regval; 3200 struct { 3201 bdrkreg_t i_rsvd_1 : 3; 3202 bdrkreg_t i_addr : 38; 3203 bdrkreg_t i_init : 3; 3204 bdrkreg_t i_source : 8; 3205 bdrkreg_t i_rsvd : 2; 3206 bdrkreg_t i_widget : 4; 3207 bdrkreg_t i_to_cnt : 5; 3208 bdrkreg_t i_vld : 1; 3209 } ii_iprte1_fld_s; 3210} ii_iprte1_u_t; 3211 3212#else 3213 3214typedef union ii_iprte1_u { 3215 bdrkreg_t ii_iprte1_regval; 3216 struct { 3217 bdrkreg_t i_vld : 1; 3218 bdrkreg_t i_to_cnt : 5; 3219 bdrkreg_t i_widget : 4; 3220 bdrkreg_t i_rsvd : 2; 3221 bdrkreg_t i_source : 8; 3222 bdrkreg_t i_init : 3; 3223 bdrkreg_t i_addr : 38; 3224 bdrkreg_t i_rsvd_1 : 3; 3225 } ii_iprte1_fld_s; 3226} ii_iprte1_u_t; 3227 3228#endif 3229 3230 3231 3232 3233/************************************************************************ 3234 * * 3235 * There are 8 instances of this register. This register contains * 3236 * the information that the II has to remember once it has launched a * 3237 * PIO Read operation. The contents are used to form the correct * 3238 * Router Network packet and direct the Crosstalk reply to the * 3239 * appropriate processor. * 3240 * * 3241 ************************************************************************/ 3242 3243 3244 3245 3246#ifdef LITTLE_ENDIAN 3247 3248typedef union ii_iprte2_u { 3249 bdrkreg_t ii_iprte2_regval; 3250 struct { 3251 bdrkreg_t i_rsvd_1 : 3; 3252 bdrkreg_t i_addr : 38; 3253 bdrkreg_t i_init : 3; 3254 bdrkreg_t i_source : 8; 3255 bdrkreg_t i_rsvd : 2; 3256 bdrkreg_t i_widget : 4; 3257 bdrkreg_t i_to_cnt : 5; 3258 bdrkreg_t i_vld : 1; 3259 } ii_iprte2_fld_s; 3260} ii_iprte2_u_t; 3261 3262#else 3263 3264typedef union ii_iprte2_u { 3265 bdrkreg_t ii_iprte2_regval; 3266 struct { 3267 bdrkreg_t i_vld : 1; 3268 bdrkreg_t i_to_cnt : 5; 3269 bdrkreg_t i_widget : 4; 3270 bdrkreg_t i_rsvd : 2; 3271 bdrkreg_t i_source : 8; 3272 bdrkreg_t i_init : 3; 3273 bdrkreg_t i_addr : 38; 3274 bdrkreg_t i_rsvd_1 : 3; 3275 } ii_iprte2_fld_s; 3276} ii_iprte2_u_t; 3277 3278#endif 3279 3280 3281 3282 3283/************************************************************************ 3284 * * 3285 * There are 8 instances of this register. This register contains * 3286 * the information that the II has to remember once it has launched a * 3287 * PIO Read operation. The contents are used to form the correct * 3288 * Router Network packet and direct the Crosstalk reply to the * 3289 * appropriate processor. * 3290 * * 3291 ************************************************************************/ 3292 3293 3294 3295 3296#ifdef LITTLE_ENDIAN 3297 3298typedef union ii_iprte3_u { 3299 bdrkreg_t ii_iprte3_regval; 3300 struct { 3301 bdrkreg_t i_rsvd_1 : 3; 3302 bdrkreg_t i_addr : 38; 3303 bdrkreg_t i_init : 3; 3304 bdrkreg_t i_source : 8; 3305 bdrkreg_t i_rsvd : 2; 3306 bdrkreg_t i_widget : 4; 3307 bdrkreg_t i_to_cnt : 5; 3308 bdrkreg_t i_vld : 1; 3309 } ii_iprte3_fld_s; 3310} ii_iprte3_u_t; 3311 3312#else 3313 3314typedef union ii_iprte3_u { 3315 bdrkreg_t ii_iprte3_regval; 3316 struct { 3317 bdrkreg_t i_vld : 1; 3318 bdrkreg_t i_to_cnt : 5; 3319 bdrkreg_t i_widget : 4; 3320 bdrkreg_t i_rsvd : 2; 3321 bdrkreg_t i_source : 8; 3322 bdrkreg_t i_init : 3; 3323 bdrkreg_t i_addr : 38; 3324 bdrkreg_t i_rsvd_1 : 3; 3325 } ii_iprte3_fld_s; 3326} ii_iprte3_u_t; 3327 3328#endif 3329 3330 3331 3332 3333/************************************************************************ 3334 * * 3335 * There are 8 instances of this register. This register contains * 3336 * the information that the II has to remember once it has launched a * 3337 * PIO Read operation. The contents are used to form the correct * 3338 * Router Network packet and direct the Crosstalk reply to the * 3339 * appropriate processor. * 3340 * * 3341 ************************************************************************/ 3342 3343 3344 3345 3346#ifdef LITTLE_ENDIAN 3347 3348typedef union ii_iprte4_u { 3349 bdrkreg_t ii_iprte4_regval; 3350 struct { 3351 bdrkreg_t i_rsvd_1 : 3; 3352 bdrkreg_t i_addr : 38; 3353 bdrkreg_t i_init : 3; 3354 bdrkreg_t i_source : 8; 3355 bdrkreg_t i_rsvd : 2; 3356 bdrkreg_t i_widget : 4; 3357 bdrkreg_t i_to_cnt : 5; 3358 bdrkreg_t i_vld : 1; 3359 } ii_iprte4_fld_s; 3360} ii_iprte4_u_t; 3361 3362#else 3363 3364typedef union ii_iprte4_u { 3365 bdrkreg_t ii_iprte4_regval; 3366 struct { 3367 bdrkreg_t i_vld : 1; 3368 bdrkreg_t i_to_cnt : 5; 3369 bdrkreg_t i_widget : 4; 3370 bdrkreg_t i_rsvd : 2; 3371 bdrkreg_t i_source : 8; 3372 bdrkreg_t i_init : 3; 3373 bdrkreg_t i_addr : 38; 3374 bdrkreg_t i_rsvd_1 : 3; 3375 } ii_iprte4_fld_s; 3376} ii_iprte4_u_t; 3377 3378#endif 3379 3380 3381 3382 3383/************************************************************************ 3384 * * 3385 * There are 8 instances of this register. This register contains * 3386 * the information that the II has to remember once it has launched a * 3387 * PIO Read operation. The contents are used to form the correct * 3388 * Router Network packet and direct the Crosstalk reply to the * 3389 * appropriate processor. * 3390 * * 3391 ************************************************************************/ 3392 3393 3394 3395 3396#ifdef LITTLE_ENDIAN 3397 3398typedef union ii_iprte5_u { 3399 bdrkreg_t ii_iprte5_regval; 3400 struct { 3401 bdrkreg_t i_rsvd_1 : 3; 3402 bdrkreg_t i_addr : 38; 3403 bdrkreg_t i_init : 3; 3404 bdrkreg_t i_source : 8; 3405 bdrkreg_t i_rsvd : 2; 3406 bdrkreg_t i_widget : 4; 3407 bdrkreg_t i_to_cnt : 5; 3408 bdrkreg_t i_vld : 1; 3409 } ii_iprte5_fld_s; 3410} ii_iprte5_u_t; 3411 3412#else 3413 3414typedef union ii_iprte5_u { 3415 bdrkreg_t ii_iprte5_regval; 3416 struct { 3417 bdrkreg_t i_vld : 1; 3418 bdrkreg_t i_to_cnt : 5; 3419 bdrkreg_t i_widget : 4; 3420 bdrkreg_t i_rsvd : 2; 3421 bdrkreg_t i_source : 8; 3422 bdrkreg_t i_init : 3; 3423 bdrkreg_t i_addr : 38; 3424 bdrkreg_t i_rsvd_1 : 3; 3425 } ii_iprte5_fld_s; 3426} ii_iprte5_u_t; 3427 3428#endif 3429 3430 3431 3432 3433/************************************************************************ 3434 * * 3435 * There are 8 instances of this register. This register contains * 3436 * the information that the II has to remember once it has launched a * 3437 * PIO Read operation. The contents are used to form the correct * 3438 * Router Network packet and direct the Crosstalk reply to the * 3439 * appropriate processor. * 3440 * * 3441 ************************************************************************/ 3442 3443 3444 3445 3446#ifdef LITTLE_ENDIAN 3447 3448typedef union ii_iprte6_u { 3449 bdrkreg_t ii_iprte6_regval; 3450 struct { 3451 bdrkreg_t i_rsvd_1 : 3; 3452 bdrkreg_t i_addr : 38; 3453 bdrkreg_t i_init : 3; 3454 bdrkreg_t i_source : 8; 3455 bdrkreg_t i_rsvd : 2; 3456 bdrkreg_t i_widget : 4; 3457 bdrkreg_t i_to_cnt : 5; 3458 bdrkreg_t i_vld : 1; 3459 } ii_iprte6_fld_s; 3460} ii_iprte6_u_t; 3461 3462#else 3463 3464typedef union ii_iprte6_u { 3465 bdrkreg_t ii_iprte6_regval; 3466 struct { 3467 bdrkreg_t i_vld : 1; 3468 bdrkreg_t i_to_cnt : 5; 3469 bdrkreg_t i_widget : 4; 3470 bdrkreg_t i_rsvd : 2; 3471 bdrkreg_t i_source : 8; 3472 bdrkreg_t i_init : 3; 3473 bdrkreg_t i_addr : 38; 3474 bdrkreg_t i_rsvd_1 : 3; 3475 } ii_iprte6_fld_s; 3476} ii_iprte6_u_t; 3477 3478#endif 3479 3480 3481 3482 3483/************************************************************************ 3484 * * 3485 * There are 8 instances of this register. This register contains * 3486 * the information that the II has to remember once it has launched a * 3487 * PIO Read operation. The contents are used to form the correct * 3488 * Router Network packet and direct the Crosstalk reply to the * 3489 * appropriate processor. * 3490 * * 3491 ************************************************************************/ 3492 3493 3494 3495 3496#ifdef LITTLE_ENDIAN 3497 3498typedef union ii_iprte7_u { 3499 bdrkreg_t ii_iprte7_regval; 3500 struct { 3501 bdrkreg_t i_rsvd_1 : 3; 3502 bdrkreg_t i_addr : 38; 3503 bdrkreg_t i_init : 3; 3504 bdrkreg_t i_source : 8; 3505 bdrkreg_t i_rsvd : 2; 3506 bdrkreg_t i_widget : 4; 3507 bdrkreg_t i_to_cnt : 5; 3508 bdrkreg_t i_vld : 1; 3509 } ii_iprte7_fld_s; 3510} ii_iprte7_u_t; 3511 3512#else 3513 3514typedef union ii_iprte7_u { 3515 bdrkreg_t ii_iprte7_regval; 3516 struct { 3517 bdrkreg_t i_vld : 1; 3518 bdrkreg_t i_to_cnt : 5; 3519 bdrkreg_t i_widget : 4; 3520 bdrkreg_t i_rsvd : 2; 3521 bdrkreg_t i_source : 8; 3522 bdrkreg_t i_init : 3; 3523 bdrkreg_t i_addr : 38; 3524 bdrkreg_t i_rsvd_1 : 3; 3525 } ii_iprte7_fld_s; 3526} ii_iprte7_u_t; 3527 3528#endif 3529 3530 3531 3532 3533/************************************************************************ 3534 * * 3535 * Description: Bedrock_II contains a feature which did not exist in * 3536 * the Hub which automatically cleans up after a Read Response * 3537 * timeout, including deallocation of the IPRTE and recovery of IBuf * 3538 * space. The inclusion of this register in Bedrock is for backward * 3539 * compatibility * 3540 * A write to this register causes an entry from the table of * 3541 * outstanding PIO Read Requests to be freed and returned to the * 3542 * stack of free entries. This register is used in handling the * 3543 * timeout errors that result in a PIO Reply never returning from * 3544 * Crosstalk. * 3545 * Note that this register does not affect the contents of the IPRTE * 3546 * registers. The Valid bits in those registers have to be * 3547 * specifically turned off by software. * 3548 * * 3549 ************************************************************************/ 3550 3551 3552 3553 3554#ifdef LITTLE_ENDIAN 3555 3556typedef union ii_ipdr_u { 3557 bdrkreg_t ii_ipdr_regval; 3558 struct { 3559 bdrkreg_t i_te : 3; 3560 bdrkreg_t i_rsvd_1 : 1; 3561 bdrkreg_t i_pnd : 1; 3562 bdrkreg_t i_init_rpcnt : 1; 3563 bdrkreg_t i_rsvd : 58; 3564 } ii_ipdr_fld_s; 3565} ii_ipdr_u_t; 3566 3567#else 3568 3569typedef union ii_ipdr_u { 3570 bdrkreg_t ii_ipdr_regval; 3571 struct { 3572 bdrkreg_t i_rsvd : 58; 3573 bdrkreg_t i_init_rpcnt : 1; 3574 bdrkreg_t i_pnd : 1; 3575 bdrkreg_t i_rsvd_1 : 1; 3576 bdrkreg_t i_te : 3; 3577 } ii_ipdr_fld_s; 3578} ii_ipdr_u_t; 3579 3580#endif 3581 3582 3583 3584 3585/************************************************************************ 3586 * * 3587 * A write to this register causes a CRB entry to be returned to the * 3588 * queue of free CRBs. The entry should have previously been cleared * 3589 * (mark bit) via backdoor access to the pertinent CRB entry. This * 3590 * register is used in the last step of handling the errors that are * 3591 * captured and marked in CRB entries. Briefly: 1) first error for * 3592 * DMA write from a particular device, and first error for a * 3593 * particular BTE stream, lead to a marked CRB entry, and processor * 3594 * interrupt, 2) software reads the error information captured in the * 3595 * CRB entry, and presumably takes some corrective action, 3) * 3596 * software clears the mark bit, and finally 4) software writes to * 3597 * the ICDR register to return the CRB entry to the list of free CRB * 3598 * entries. * 3599 * * 3600 ************************************************************************/ 3601 3602 3603 3604 3605#ifdef LITTLE_ENDIAN 3606 3607typedef union ii_icdr_u { 3608 bdrkreg_t ii_icdr_regval; 3609 struct { 3610 bdrkreg_t i_crb_num : 4; 3611 bdrkreg_t i_pnd : 1; 3612 bdrkreg_t i_rsvd : 59; 3613 } ii_icdr_fld_s; 3614} ii_icdr_u_t; 3615 3616#else 3617 3618typedef union ii_icdr_u { 3619 bdrkreg_t ii_icdr_regval; 3620 struct { 3621 bdrkreg_t i_rsvd : 59; 3622 bdrkreg_t i_pnd : 1; 3623 bdrkreg_t i_crb_num : 4; 3624 } ii_icdr_fld_s; 3625} ii_icdr_u_t; 3626 3627#endif 3628 3629 3630 3631 3632/************************************************************************ 3633 * * 3634 * This register provides debug access to two FIFOs inside of II. * 3635 * Both IOQ_MAX* fields of this register contain the instantaneous * 3636 * depth (in units of the number of available entries) of the * 3637 * associated IOQ FIFO. A read of this register will return the * 3638 * number of free entries on each FIFO at the time of the read. So * 3639 * when a FIFO is idle, the associated field contains the maximum * 3640 * depth of the FIFO. This register is writable for debug reasons * 3641 * and is intended to be written with the maximum desired FIFO depth * 3642 * while the FIFO is idle. Software must assure that II is idle when * 3643 * this register is written. If there are any active entries in any * 3644 * of these FIFOs when this register is written, the results are * 3645 * undefined. * 3646 * * 3647 ************************************************************************/ 3648 3649 3650 3651 3652#ifdef LITTLE_ENDIAN 3653 3654typedef union ii_ifdr_u { 3655 bdrkreg_t ii_ifdr_regval; 3656 struct { 3657 bdrkreg_t i_ioq_max_rq : 7; 3658 bdrkreg_t i_set_ioq_rq : 1; 3659 bdrkreg_t i_ioq_max_rp : 7; 3660 bdrkreg_t i_set_ioq_rp : 1; 3661 bdrkreg_t i_rsvd : 48; 3662 } ii_ifdr_fld_s; 3663} ii_ifdr_u_t; 3664 3665#else 3666 3667typedef union ii_ifdr_u { 3668 bdrkreg_t ii_ifdr_regval; 3669 struct { 3670 bdrkreg_t i_rsvd : 48; 3671 bdrkreg_t i_set_ioq_rp : 1; 3672 bdrkreg_t i_ioq_max_rp : 7; 3673 bdrkreg_t i_set_ioq_rq : 1; 3674 bdrkreg_t i_ioq_max_rq : 7; 3675 } ii_ifdr_fld_s; 3676} ii_ifdr_u_t; 3677 3678#endif 3679 3680 3681 3682 3683/************************************************************************ 3684 * * 3685 * This register allows the II to become sluggish in removing * 3686 * messages from its inbound queue (IIQ). This will cause messages to * 3687 * back up in either virtual channel. Disabling the "molasses" mode * 3688 * subsequently allows the II to be tested under stress. In the * 3689 * sluggish ("Molasses") mode, the localized effects of congestion * 3690 * can be observed. * 3691 * * 3692 ************************************************************************/ 3693 3694 3695 3696 3697#ifdef LITTLE_ENDIAN 3698 3699typedef union ii_iiap_u { 3700 bdrkreg_t ii_iiap_regval; 3701 struct { 3702 bdrkreg_t i_rq_mls : 6; 3703 bdrkreg_t i_rsvd_1 : 2; 3704 bdrkreg_t i_rp_mls : 6; 3705 bdrkreg_t i_rsvd : 50; 3706 } ii_iiap_fld_s; 3707} ii_iiap_u_t; 3708 3709#else 3710 3711typedef union ii_iiap_u { 3712 bdrkreg_t ii_iiap_regval; 3713 struct { 3714 bdrkreg_t i_rsvd : 50; 3715 bdrkreg_t i_rp_mls : 6; 3716 bdrkreg_t i_rsvd_1 : 2; 3717 bdrkreg_t i_rq_mls : 6; 3718 } ii_iiap_fld_s; 3719} ii_iiap_u_t; 3720 3721#endif 3722 3723 3724 3725 3726/************************************************************************ 3727 * * 3728 * This register allows several parameters of CRB operation to be * 3729 * set. Note that writing to this register can have catastrophic side * 3730 * effects, if the CRB is not quiescent, i.e. if the CRB is * 3731 * processing protocol messages when the write occurs. * 3732 * * 3733 ************************************************************************/ 3734 3735 3736 3737 3738#ifdef LITTLE_ENDIAN 3739 3740typedef union ii_icmr_u { 3741 bdrkreg_t ii_icmr_regval; 3742 struct { 3743 bdrkreg_t i_sp_msg : 1; 3744 bdrkreg_t i_rd_hdr : 1; 3745 bdrkreg_t i_rsvd_4 : 2; 3746 bdrkreg_t i_c_cnt : 4; 3747 bdrkreg_t i_rsvd_3 : 4; 3748 bdrkreg_t i_clr_rqpd : 1; 3749 bdrkreg_t i_clr_rppd : 1; 3750 bdrkreg_t i_rsvd_2 : 2; 3751 bdrkreg_t i_fc_cnt : 4; 3752 bdrkreg_t i_crb_vld : 15; 3753 bdrkreg_t i_crb_mark : 15; 3754 bdrkreg_t i_rsvd_1 : 2; 3755 bdrkreg_t i_precise : 1; 3756 bdrkreg_t i_rsvd : 11; 3757 } ii_icmr_fld_s; 3758} ii_icmr_u_t; 3759 3760#else 3761 3762typedef union ii_icmr_u { 3763 bdrkreg_t ii_icmr_regval; 3764 struct { 3765 bdrkreg_t i_rsvd : 11; 3766 bdrkreg_t i_precise : 1; 3767 bdrkreg_t i_rsvd_1 : 2; 3768 bdrkreg_t i_crb_mark : 15; 3769 bdrkreg_t i_crb_vld : 15; 3770 bdrkreg_t i_fc_cnt : 4; 3771 bdrkreg_t i_rsvd_2 : 2; 3772 bdrkreg_t i_clr_rppd : 1; 3773 bdrkreg_t i_clr_rqpd : 1; 3774 bdrkreg_t i_rsvd_3 : 4; 3775 bdrkreg_t i_c_cnt : 4; 3776 bdrkreg_t i_rsvd_4 : 2; 3777 bdrkreg_t i_rd_hdr : 1; 3778 bdrkreg_t i_sp_msg : 1; 3779 } ii_icmr_fld_s; 3780} ii_icmr_u_t; 3781 3782#endif 3783 3784 3785 3786 3787/************************************************************************ 3788 * * 3789 * This register allows control of the table portion of the CRB * 3790 * logic via software. Control operations from this register have * 3791 * priority over all incoming Crosstalk or BTE requests. * 3792 * * 3793 ************************************************************************/ 3794 3795 3796 3797 3798#ifdef LITTLE_ENDIAN 3799 3800typedef union ii_iccr_u { 3801 bdrkreg_t ii_iccr_regval; 3802 struct { 3803 bdrkreg_t i_crb_num : 4; 3804 bdrkreg_t i_rsvd_1 : 4; 3805 bdrkreg_t i_cmd : 8; 3806 bdrkreg_t i_pending : 1; 3807 bdrkreg_t i_rsvd : 47; 3808 } ii_iccr_fld_s; 3809} ii_iccr_u_t; 3810 3811#else 3812 3813typedef union ii_iccr_u { 3814 bdrkreg_t ii_iccr_regval; 3815 struct { 3816 bdrkreg_t i_rsvd : 47; 3817 bdrkreg_t i_pending : 1; 3818 bdrkreg_t i_cmd : 8; 3819 bdrkreg_t i_rsvd_1 : 4; 3820 bdrkreg_t i_crb_num : 4; 3821 } ii_iccr_fld_s; 3822} ii_iccr_u_t; 3823 3824#endif 3825 3826 3827 3828 3829/************************************************************************ 3830 * * 3831 * This register allows the maximum timeout value to be programmed. * 3832 * * 3833 ************************************************************************/ 3834 3835 3836 3837 3838#ifdef LITTLE_ENDIAN 3839 3840typedef union ii_icto_u { 3841 bdrkreg_t ii_icto_regval; 3842 struct { 3843 bdrkreg_t i_timeout : 8; 3844 bdrkreg_t i_rsvd : 56; 3845 } ii_icto_fld_s; 3846} ii_icto_u_t; 3847 3848#else 3849 3850typedef union ii_icto_u { 3851 bdrkreg_t ii_icto_regval; 3852 struct { 3853 bdrkreg_t i_rsvd : 56; 3854 bdrkreg_t i_timeout : 8; 3855 } ii_icto_fld_s; 3856} ii_icto_u_t; 3857 3858#endif 3859 3860 3861 3862 3863/************************************************************************ 3864 * * 3865 * This register allows the timeout prescalar to be programmed. An * 3866 * internal counter is associated with this register. When the * 3867 * internal counter reaches the value of the PRESCALE field, the * 3868 * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * 3869 * field). The internal counter resets to zero, and then continues * 3870 * counting. * 3871 * * 3872 ************************************************************************/ 3873 3874 3875 3876 3877#ifdef LITTLE_ENDIAN 3878 3879typedef union ii_ictp_u { 3880 bdrkreg_t ii_ictp_regval; 3881 struct { 3882 bdrkreg_t i_prescale : 24; 3883 bdrkreg_t i_rsvd : 40; 3884 } ii_ictp_fld_s; 3885} ii_ictp_u_t; 3886 3887#else 3888 3889typedef union ii_ictp_u { 3890 bdrkreg_t ii_ictp_regval; 3891 struct { 3892 bdrkreg_t i_rsvd : 40; 3893 bdrkreg_t i_prescale : 24; 3894 } ii_ictp_fld_s; 3895} ii_ictp_u_t; 3896 3897#endif 3898 3899 3900 3901 3902/************************************************************************ 3903 * * 3904 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 3905 * used for Crosstalk operations (both cacheline and partial * 3906 * operations) or BTE/IO. Because the CRB entries are very wide, four * 3907 * registers (_A to _D) are required to read and write each entry. * 3908 * The CRB Entry registers can be conceptualized as rows and columns * 3909 * (illustrated in the table above). Each row contains the 4 * 3910 * registers required for a single CRB Entry. The first doubleword * 3911 * (column) for each entry is labeled A, and the second doubleword * 3912 * (higher address) is labeled B, the third doubleword is labeled C, * 3913 * and the fourth doubleword is labeled D. All CRB entries have their * 3914 * addresses on a quarter cacheline aligned boundary. * 3915 * Upon reset, only the following fields are initialized: valid * 3916 * (VLD), priority count, timeout, timeout valid, and context valid. * 3917 * All other bits should be cleared by software before use (after * 3918 * recovering any potential error state from before the reset). * 3919 * The following four tables summarize the format for the four * 3920 * registers that are used for each ICRB# Entry. * 3921 * * 3922 ************************************************************************/ 3923 3924 3925 3926 3927#ifdef LITTLE_ENDIAN 3928 3929typedef union ii_icrb0_a_u { 3930 bdrkreg_t ii_icrb0_a_regval; 3931 struct { 3932 bdrkreg_t ia_iow : 1; 3933 bdrkreg_t ia_vld : 1; 3934 bdrkreg_t ia_addr : 38; 3935 bdrkreg_t ia_tnum : 5; 3936 bdrkreg_t ia_sidn : 4; 3937 bdrkreg_t ia_xt_err : 1; 3938 bdrkreg_t ia_mark : 1; 3939 bdrkreg_t ia_ln_uce : 1; 3940 bdrkreg_t ia_errcode : 3; 3941 bdrkreg_t ia_error : 1; 3942 bdrkreg_t ia_stall__bte_1 : 1; 3943 bdrkreg_t ia_stall__bte_0 : 1; 3944 bdrkreg_t ia_rsvd : 6; 3945 } ii_icrb0_a_fld_s; 3946} ii_icrb0_a_u_t; 3947 3948#else 3949 3950typedef union ii_icrb0_a_u { 3951 bdrkreg_t ii_icrb0_a_regval; 3952 struct { 3953 bdrkreg_t ia_rsvd : 6; 3954 bdrkreg_t ia_stall__bte_0 : 1; 3955 bdrkreg_t ia_stall__bte_1 : 1; 3956 bdrkreg_t ia_error : 1; 3957 bdrkreg_t ia_errcode : 3; 3958 bdrkreg_t ia_ln_uce : 1; 3959 bdrkreg_t ia_mark : 1; 3960 bdrkreg_t ia_xt_err : 1; 3961 bdrkreg_t ia_sidn : 4; 3962 bdrkreg_t ia_tnum : 5; 3963 bdrkreg_t ia_addr : 38; 3964 bdrkreg_t ia_vld : 1; 3965 bdrkreg_t ia_iow : 1; 3966 } ii_icrb0_a_fld_s; 3967} ii_icrb0_a_u_t; 3968 3969#endif 3970 3971 3972 3973 3974/************************************************************************ 3975 * * 3976 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 3977 * used for Crosstalk operations (both cacheline and partial * 3978 * operations) or BTE/IO. Because the CRB entries are very wide, four * 3979 * registers (_A to _D) are required to read and write each entry. * 3980 * * 3981 ************************************************************************/ 3982 3983 3984 3985 3986 3987#ifdef LITTLE_ENDIAN 3988 3989typedef union ii_icrb0_b_u { 3990 bdrkreg_t ii_icrb0_b_regval; 3991 struct { 3992 bdrkreg_t ib_stall__intr : 1; 3993 bdrkreg_t ib_stall_ib : 1; 3994 bdrkreg_t ib_intvn : 1; 3995 bdrkreg_t ib_wb : 1; 3996 bdrkreg_t ib_hold : 1; 3997 bdrkreg_t ib_ack : 1; 3998 bdrkreg_t ib_resp : 1; 3999 bdrkreg_t ib_ack_cnt : 11; 4000 bdrkreg_t ib_rsvd_1 : 7; 4001 bdrkreg_t ib_exc : 5; 4002 bdrkreg_t ib_init : 3; 4003 bdrkreg_t ib_imsg : 8; 4004 bdrkreg_t ib_imsgtype : 2; 4005 bdrkreg_t ib_use_old : 1; 4006 bdrkreg_t ib_source : 12; 4007 bdrkreg_t ib_size : 2; 4008 bdrkreg_t ib_ct : 1; 4009 bdrkreg_t ib_bte_num : 1; 4010 bdrkreg_t ib_rsvd : 4; 4011 } ii_icrb0_b_fld_s; 4012} ii_icrb0_b_u_t; 4013 4014#else 4015 4016typedef union ii_icrb0_b_u { 4017 bdrkreg_t ii_icrb0_b_regval; 4018 struct { 4019 bdrkreg_t ib_rsvd : 4; 4020 bdrkreg_t ib_bte_num : 1; 4021 bdrkreg_t ib_ct : 1; 4022 bdrkreg_t ib_size : 2; 4023 bdrkreg_t ib_source : 12; 4024 bdrkreg_t ib_use_old : 1; 4025 bdrkreg_t ib_imsgtype : 2; 4026 bdrkreg_t ib_imsg : 8; 4027 bdrkreg_t ib_init : 3; 4028 bdrkreg_t ib_exc : 5; 4029 bdrkreg_t ib_rsvd_1 : 7; 4030 bdrkreg_t ib_ack_cnt : 11; 4031 bdrkreg_t ib_resp : 1; 4032 bdrkreg_t ib_ack : 1; 4033 bdrkreg_t ib_hold : 1; 4034 bdrkreg_t ib_wb : 1; 4035 bdrkreg_t ib_intvn : 1; 4036 bdrkreg_t ib_stall_ib : 1; 4037 bdrkreg_t ib_stall__intr : 1; 4038 } ii_icrb0_b_fld_s; 4039} ii_icrb0_b_u_t; 4040 4041#endif 4042 4043 4044 4045 4046/************************************************************************ 4047 * * 4048 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 4049 * used for Crosstalk operations (both cacheline and partial * 4050 * operations) or BTE/IO. Because the CRB entries are very wide, four * 4051 * registers (_A to _D) are required to read and write each entry. * 4052 * * 4053 ************************************************************************/ 4054 4055 4056 4057 4058#ifdef LITTLE_ENDIAN 4059 4060typedef union ii_icrb0_c_u { 4061 bdrkreg_t ii_icrb0_c_regval; 4062 struct { 4063 bdrkreg_t ic_gbr : 1; 4064 bdrkreg_t ic_resprqd : 1; 4065 bdrkreg_t ic_bo : 1; 4066 bdrkreg_t ic_suppl : 12; 4067 bdrkreg_t ic_pa_be : 34; 4068 bdrkreg_t ic_bte_op : 1; 4069 bdrkreg_t ic_pr_psc : 4; 4070 bdrkreg_t ic_pr_cnt : 4; 4071 bdrkreg_t ic_sleep : 1; 4072 bdrkreg_t ic_rsvd : 5; 4073 } ii_icrb0_c_fld_s; 4074} ii_icrb0_c_u_t; 4075 4076#else 4077 4078typedef union ii_icrb0_c_u { 4079 bdrkreg_t ii_icrb0_c_regval; 4080 struct { 4081 bdrkreg_t ic_rsvd : 5; 4082 bdrkreg_t ic_sleep : 1; 4083 bdrkreg_t ic_pr_cnt : 4; 4084 bdrkreg_t ic_pr_psc : 4; 4085 bdrkreg_t ic_bte_op : 1; 4086 bdrkreg_t ic_pa_be : 34; 4087 bdrkreg_t ic_suppl : 12; 4088 bdrkreg_t ic_bo : 1; 4089 bdrkreg_t ic_resprqd : 1; 4090 bdrkreg_t ic_gbr : 1; 4091 } ii_icrb0_c_fld_s; 4092} ii_icrb0_c_u_t; 4093 4094#endif 4095 4096 4097 4098/************************************************************************ 4099 * * 4100 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 4101 * used for Crosstalk operations (both cacheline and partial * 4102 * operations) or BTE/IO. Because the CRB entries are very wide, four * 4103 * registers (_A to _D) are required to read and write each entry. * 4104 * * 4105 ************************************************************************/ 4106 4107 4108 4109 4110#ifdef LITTLE_ENDIAN 4111 4112typedef union ii_icrb0_d_u { 4113 bdrkreg_t ii_icrb0_d_regval; 4114 struct { 4115 bdrkreg_t id_timeout : 8; 4116 bdrkreg_t id_context : 15; 4117 bdrkreg_t id_rsvd_1 : 1; 4118 bdrkreg_t id_tvld : 1; 4119 bdrkreg_t id_cvld : 1; 4120 bdrkreg_t id_rsvd : 38; 4121 } ii_icrb0_d_fld_s; 4122} ii_icrb0_d_u_t; 4123 4124#else 4125 4126typedef union ii_icrb0_d_u { 4127 bdrkreg_t ii_icrb0_d_regval; 4128 struct { 4129 bdrkreg_t id_rsvd : 38; 4130 bdrkreg_t id_cvld : 1; 4131 bdrkreg_t id_tvld : 1; 4132 bdrkreg_t id_rsvd_1 : 1; 4133 bdrkreg_t id_context : 15; 4134 bdrkreg_t id_timeout : 8; 4135 } ii_icrb0_d_fld_s; 4136} ii_icrb0_d_u_t; 4137 4138#endif 4139 4140 4141 4142 4143/************************************************************************ 4144 * * 4145 * This register contains the lower 64 bits of the header of the * 4146 * spurious message captured by II. Valid when the SP_MSG bit in ICMR * 4147 * register is set. * 4148 * * 4149 ************************************************************************/ 4150 4151 4152 4153 4154#ifdef LITTLE_ENDIAN 4155 4156typedef union ii_icsml_u { 4157 bdrkreg_t ii_icsml_regval; 4158 struct { 4159 bdrkreg_t i_tt_addr : 38; 4160 bdrkreg_t i_tt_ack_cnt : 11; 4161 bdrkreg_t i_newsuppl_ex : 11; 4162 bdrkreg_t i_reserved : 3; 4163 bdrkreg_t i_overflow : 1; 4164 } ii_icsml_fld_s; 4165} ii_icsml_u_t; 4166 4167#else 4168 4169typedef union ii_icsml_u { 4170 bdrkreg_t ii_icsml_regval; 4171 struct { 4172 bdrkreg_t i_overflow : 1; 4173 bdrkreg_t i_reserved : 3; 4174 bdrkreg_t i_newsuppl_ex : 11; 4175 bdrkreg_t i_tt_ack_cnt : 11; 4176 bdrkreg_t i_tt_addr : 38; 4177 } ii_icsml_fld_s; 4178} ii_icsml_u_t; 4179 4180#endif 4181 4182 4183 4184 4185/************************************************************************ 4186 * * 4187 * This register contains the microscopic state, all the inputs to * 4188 * the protocol table, captured with the spurious message. Valid when * 4189 * the SP_MSG bit in the ICMR register is set. * 4190 * * 4191 ************************************************************************/ 4192 4193 4194 4195 4196#ifdef LITTLE_ENDIAN 4197 4198typedef union ii_icsmh_u { 4199 bdrkreg_t ii_icsmh_regval; 4200 struct { 4201 bdrkreg_t i_tt_vld : 1; 4202 bdrkreg_t i_xerr : 1; 4203 bdrkreg_t i_ft_cwact_o : 1; 4204 bdrkreg_t i_ft_wact_o : 1; 4205 bdrkreg_t i_ft_active_o : 1; 4206 bdrkreg_t i_sync : 1; 4207 bdrkreg_t i_mnusg : 1; 4208 bdrkreg_t i_mnusz : 1; 4209 bdrkreg_t i_plusz : 1; 4210 bdrkreg_t i_plusg : 1; 4211 bdrkreg_t i_tt_exc : 5; 4212 bdrkreg_t i_tt_wb : 1; 4213 bdrkreg_t i_tt_hold : 1; 4214 bdrkreg_t i_tt_ack : 1; 4215 bdrkreg_t i_tt_resp : 1; 4216 bdrkreg_t i_tt_intvn : 1; 4217 bdrkreg_t i_g_stall_bte1 : 1; 4218 bdrkreg_t i_g_stall_bte0 : 1; 4219 bdrkreg_t i_g_stall_il : 1; 4220 bdrkreg_t i_g_stall_ib : 1; 4221 bdrkreg_t i_tt_imsg : 8; 4222 bdrkreg_t i_tt_imsgtype : 2; 4223 bdrkreg_t i_tt_use_old : 1; 4224 bdrkreg_t i_tt_respreqd : 1; 4225 bdrkreg_t i_tt_bte_num : 1; 4226 bdrkreg_t i_cbn : 1; 4227 bdrkreg_t i_match : 1; 4228 bdrkreg_t i_rpcnt_lt_34 : 1; 4229 bdrkreg_t i_rpcnt_ge_34 : 1; 4230 bdrkreg_t i_rpcnt_lt_18 : 1; 4231 bdrkreg_t i_rpcnt_ge_18 : 1; 4232 bdrkreg_t i_rpcnt_lt_2 : 1; 4233 bdrkreg_t i_rpcnt_ge_2 : 1; 4234 bdrkreg_t i_rqcnt_lt_18 : 1; 4235 bdrkreg_t i_rqcnt_ge_18 : 1; 4236 bdrkreg_t i_rqcnt_lt_2 : 1; 4237 bdrkreg_t i_rqcnt_ge_2 : 1; 4238 bdrkreg_t i_tt_device : 7; 4239 bdrkreg_t i_tt_init : 3; 4240 bdrkreg_t i_reserved : 5; 4241 } ii_icsmh_fld_s; 4242} ii_icsmh_u_t; 4243 4244#else 4245 4246typedef union ii_icsmh_u { 4247 bdrkreg_t ii_icsmh_regval; 4248 struct { 4249 bdrkreg_t i_reserved : 5; 4250 bdrkreg_t i_tt_init : 3; 4251 bdrkreg_t i_tt_device : 7; 4252 bdrkreg_t i_rqcnt_ge_2 : 1; 4253 bdrkreg_t i_rqcnt_lt_2 : 1; 4254 bdrkreg_t i_rqcnt_ge_18 : 1; 4255 bdrkreg_t i_rqcnt_lt_18 : 1; 4256 bdrkreg_t i_rpcnt_ge_2 : 1; 4257 bdrkreg_t i_rpcnt_lt_2 : 1; 4258 bdrkreg_t i_rpcnt_ge_18 : 1; 4259 bdrkreg_t i_rpcnt_lt_18 : 1; 4260 bdrkreg_t i_rpcnt_ge_34 : 1; 4261 bdrkreg_t i_rpcnt_lt_34 : 1; 4262 bdrkreg_t i_match : 1; 4263 bdrkreg_t i_cbn : 1; 4264 bdrkreg_t i_tt_bte_num : 1; 4265 bdrkreg_t i_tt_respreqd : 1; 4266 bdrkreg_t i_tt_use_old : 1; 4267 bdrkreg_t i_tt_imsgtype : 2; 4268 bdrkreg_t i_tt_imsg : 8; 4269 bdrkreg_t i_g_stall_ib : 1; 4270 bdrkreg_t i_g_stall_il : 1; 4271 bdrkreg_t i_g_stall_bte0 : 1; 4272 bdrkreg_t i_g_stall_bte1 : 1; 4273 bdrkreg_t i_tt_intvn : 1; 4274 bdrkreg_t i_tt_resp : 1; 4275 bdrkreg_t i_tt_ack : 1; 4276 bdrkreg_t i_tt_hold : 1; 4277 bdrkreg_t i_tt_wb : 1; 4278 bdrkreg_t i_tt_exc : 5; 4279 bdrkreg_t i_plusg : 1; 4280 bdrkreg_t i_plusz : 1; 4281 bdrkreg_t i_mnusz : 1; 4282 bdrkreg_t i_mnusg : 1; 4283 bdrkreg_t i_sync : 1; 4284 bdrkreg_t i_ft_active_o : 1; 4285 bdrkreg_t i_ft_wact_o : 1; 4286 bdrkreg_t i_ft_cwact_o : 1; 4287 bdrkreg_t i_xerr : 1; 4288 bdrkreg_t i_tt_vld : 1; 4289 } ii_icsmh_fld_s; 4290} ii_icsmh_u_t; 4291 4292#endif 4293 4294 4295/************************************************************************ 4296 * * 4297 * The Bedrock DEBUG unit provides a 3-bit selection signal to the * 4298 * II unit, thus allowing a choice of one set of debug signal outputs * 4299 * from a menu of 8 options. Each option is limited to 32 bits in * 4300 * size. There are more signals of interest than can be accommodated * 4301 * in this 8*32 framework, so the IDBSS register has been defined to * 4302 * extend the range of choices available. For each menu option * 4303 * available to the DEBUG unit, the II provides a "submenu" of * 4304 * several options. The value of the SUBMENU field in the IDBSS * 4305 * register selects the desired submenu. Hence, the particular debug * 4306 * signals provided by the II are determined by the 3-bit selection * 4307 * signal from the DEBUG unit and the value of the SUBMENU field * 4308 * within the IDBSS register. For a detailed description of the * 4309 * available menus and submenus for II debug signals, refer to the * 4310 * documentation in ii_interface.doc.. * 4311 * * 4312 ************************************************************************/ 4313 4314 4315 4316 4317#ifdef LIITLE_ENDIAN 4318 4319typedef union ii_idbss_u { 4320 bdrkreg_t ii_idbss_regval; 4321 struct { 4322 bdrkreg_t i_submenu : 3; 4323 bdrkreg_t i_rsvd : 61; 4324 } ii_idbss_fld_s; 4325} ii_idbss_u_t; 4326 4327#else 4328 4329typedef union ii_idbss_u { 4330 bdrkreg_t ii_idbss_regval; 4331 struct { 4332 bdrkreg_t i_rsvd : 61; 4333 bdrkreg_t i_submenu : 3; 4334 } ii_idbss_fld_s; 4335} ii_idbss_u_t; 4336 4337#endif 4338 4339 4340 4341 4342/************************************************************************ 4343 * * 4344 * Description: This register is used to set up the length for a * 4345 * transfer and then to monitor the progress of that transfer. This * 4346 * register needs to be initialized before a transfer is started. A * 4347 * legitimate write to this register will set the Busy bit, clear the * 4348 * Error bit, and initialize the length to the value desired. * 4349 * While the transfer is in progress, hardware will decrement the * 4350 * length field with each successful block that is copied. Once the * 4351 * transfer completes, hardware will clear the Busy bit. The length * 4352 * field will also contain the number of cache lines left to be * 4353 * transferred. * 4354 * * 4355 ************************************************************************/ 4356 4357 4358 4359 4360#ifdef LIITLE_ENDIAN 4361 4362typedef union ii_ibls0_u { 4363 bdrkreg_t ii_ibls0_regval; 4364 struct { 4365 bdrkreg_t i_length : 16; 4366 bdrkreg_t i_error : 1; 4367 bdrkreg_t i_rsvd_1 : 3; 4368 bdrkreg_t i_busy : 1; 4369 bdrkreg_t i_rsvd : 43; 4370 } ii_ibls0_fld_s; 4371} ii_ibls0_u_t; 4372 4373#else 4374 4375typedef union ii_ibls0_u { 4376 bdrkreg_t ii_ibls0_regval; 4377 struct { 4378 bdrkreg_t i_rsvd : 43; 4379 bdrkreg_t i_busy : 1; 4380 bdrkreg_t i_rsvd_1 : 3; 4381 bdrkreg_t i_error : 1; 4382 bdrkreg_t i_length : 16; 4383 } ii_ibls0_fld_s; 4384} ii_ibls0_u_t; 4385 4386#endif 4387 4388 4389 4390 4391/************************************************************************ 4392 * * 4393 * This register should be loaded before a transfer is started. The * 4394 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 4395 * address as described in Section 1.3, Figure2 and Figure3. Since * 4396 * the bottom 7 bits of the address are always taken to be zero, BTE * 4397 * transfers are always cacheline-aligned. * 4398 * * 4399 ************************************************************************/ 4400 4401 4402 4403 4404#ifdef LITTLE_ENDIAN 4405 4406typedef union ii_ibsa0_u { 4407 bdrkreg_t ii_ibsa0_regval; 4408 struct { 4409 bdrkreg_t i_rsvd_1 : 7; 4410 bdrkreg_t i_addr : 33; 4411 bdrkreg_t i_rsvd : 24; 4412 } ii_ibsa0_fld_s; 4413} ii_ibsa0_u_t; 4414 4415#else 4416 4417typedef union ii_ibsa0_u { 4418 bdrkreg_t ii_ibsa0_regval; 4419 struct { 4420 bdrkreg_t i_rsvd : 24; 4421 bdrkreg_t i_addr : 33; 4422 bdrkreg_t i_rsvd_1 : 7; 4423 } ii_ibsa0_fld_s; 4424} ii_ibsa0_u_t; 4425 4426#endif 4427 4428 4429 4430 4431/************************************************************************ 4432 * * 4433 * This register should be loaded before a transfer is started. The * 4434 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 4435 * address as described in Section 1.3, Figure2 and Figure3. Since * 4436 * the bottom 7 bits of the address are always taken to be zero, BTE * 4437 * transfers are always cacheline-aligned. * 4438 * * 4439 ************************************************************************/ 4440 4441 4442 4443 4444#ifdef LITTLE_ENDIAN 4445 4446typedef union ii_ibda0_u { 4447 bdrkreg_t ii_ibda0_regval; 4448 struct { 4449 bdrkreg_t i_rsvd_1 : 7; 4450 bdrkreg_t i_addr : 33; 4451 bdrkreg_t i_rsvd : 24; 4452 } ii_ibda0_fld_s; 4453} ii_ibda0_u_t; 4454 4455#else 4456 4457typedef union ii_ibda0_u { 4458 bdrkreg_t ii_ibda0_regval; 4459 struct { 4460 bdrkreg_t i_rsvd : 24; 4461 bdrkreg_t i_addr : 33; 4462 bdrkreg_t i_rsvd_1 : 7; 4463 } ii_ibda0_fld_s; 4464} ii_ibda0_u_t; 4465 4466#endif 4467 4468 4469 4470 4471/************************************************************************ 4472 * * 4473 * Writing to this register sets up the attributes of the transfer * 4474 * and initiates the transfer operation. Reading this register has * 4475 * the side effect of terminating any transfer in progress. Note: * 4476 * stopping a transfer midstream could have an adverse impact on the * 4477 * other BTE. If a BTE stream has to be stopped (due to error * 4478 * handling for example), both BTE streams should be stopped and * 4479 * their transfers discarded. * 4480 * * 4481 ************************************************************************/ 4482 4483 4484 4485 4486#ifdef LITTLE_ENDIAN 4487 4488typedef union ii_ibct0_u { 4489 bdrkreg_t ii_ibct0_regval; 4490 struct { 4491 bdrkreg_t i_zerofill : 1; 4492 bdrkreg_t i_rsvd_2 : 3; 4493 bdrkreg_t i_notify : 1; 4494 bdrkreg_t i_rsvd_1 : 3; 4495 bdrkreg_t i_poison : 1; 4496 bdrkreg_t i_rsvd : 55; 4497 } ii_ibct0_fld_s; 4498} ii_ibct0_u_t; 4499 4500#else 4501 4502typedef union ii_ibct0_u { 4503 bdrkreg_t ii_ibct0_regval; 4504 struct { 4505 bdrkreg_t i_rsvd : 55; 4506 bdrkreg_t i_poison : 1; 4507 bdrkreg_t i_rsvd_1 : 3; 4508 bdrkreg_t i_notify : 1; 4509 bdrkreg_t i_rsvd_2 : 3; 4510 bdrkreg_t i_zerofill : 1; 4511 } ii_ibct0_fld_s; 4512} ii_ibct0_u_t; 4513 4514#endif 4515 4516 4517 4518 4519/************************************************************************ 4520 * * 4521 * This register contains the address to which the WINV is sent. * 4522 * This address has to be cache line aligned. * 4523 * * 4524 ************************************************************************/ 4525 4526 4527 4528 4529#ifdef LITTLE_ENDIAN 4530 4531typedef union ii_ibna0_u { 4532 bdrkreg_t ii_ibna0_regval; 4533 struct { 4534 bdrkreg_t i_rsvd_1 : 7; 4535 bdrkreg_t i_addr : 33; 4536 bdrkreg_t i_rsvd : 24; 4537 } ii_ibna0_fld_s; 4538} ii_ibna0_u_t; 4539 4540#else 4541 4542typedef union ii_ibna0_u { 4543 bdrkreg_t ii_ibna0_regval; 4544 struct { 4545 bdrkreg_t i_rsvd : 24; 4546 bdrkreg_t i_addr : 33; 4547 bdrkreg_t i_rsvd_1 : 7; 4548 } ii_ibna0_fld_s; 4549} ii_ibna0_u_t; 4550 4551#endif 4552 4553 4554 4555 4556/************************************************************************ 4557 * * 4558 * This register contains the programmable level as well as the node * 4559 * ID and PI unit of the processor to which the interrupt will be * 4560 * sent. * 4561 * * 4562 ************************************************************************/ 4563 4564 4565 4566 4567#ifdef LITTLE_ENDIAN 4568 4569typedef union ii_ibia0_u { 4570 bdrkreg_t ii_ibia0_regval; 4571 struct { 4572 bdrkreg_t i_pi_id : 1; 4573 bdrkreg_t i_node_id : 8; 4574 bdrkreg_t i_rsvd_1 : 7; 4575 bdrkreg_t i_level : 7; 4576 bdrkreg_t i_rsvd : 41; 4577 } ii_ibia0_fld_s; 4578} ii_ibia0_u_t; 4579 4580#else 4581 4582typedef union ii_ibia0_u { 4583 bdrkreg_t ii_ibia0_regval; 4584 struct { 4585 bdrkreg_t i_rsvd : 41; 4586 bdrkreg_t i_level : 7; 4587 bdrkreg_t i_rsvd_1 : 7; 4588 bdrkreg_t i_node_id : 8; 4589 bdrkreg_t i_pi_id : 1; 4590 } ii_ibia0_fld_s; 4591} ii_ibia0_u_t; 4592 4593#endif 4594 4595 4596 4597 4598/************************************************************************ 4599 * * 4600 * Description: This register is used to set up the length for a * 4601 * transfer and then to monitor the progress of that transfer. This * 4602 * register needs to be initialized before a transfer is started. A * 4603 * legitimate write to this register will set the Busy bit, clear the * 4604 * Error bit, and initialize the length to the value desired. * 4605 * While the transfer is in progress, hardware will decrement the * 4606 * length field with each successful block that is copied. Once the * 4607 * transfer completes, hardware will clear the Busy bit. The length * 4608 * field will also contain the number of cache lines left to be * 4609 * transferred. * 4610 * * 4611 ************************************************************************/ 4612 4613 4614 4615 4616#ifdef LITTLE_ENDIAN 4617 4618typedef union ii_ibls1_u { 4619 bdrkreg_t ii_ibls1_regval; 4620 struct { 4621 bdrkreg_t i_length : 16; 4622 bdrkreg_t i_error : 1; 4623 bdrkreg_t i_rsvd_1 : 3; 4624 bdrkreg_t i_busy : 1; 4625 bdrkreg_t i_rsvd : 43; 4626 } ii_ibls1_fld_s; 4627} ii_ibls1_u_t; 4628 4629#else 4630 4631typedef union ii_ibls1_u { 4632 bdrkreg_t ii_ibls1_regval; 4633 struct { 4634 bdrkreg_t i_rsvd : 43; 4635 bdrkreg_t i_busy : 1; 4636 bdrkreg_t i_rsvd_1 : 3; 4637 bdrkreg_t i_error : 1; 4638 bdrkreg_t i_length : 16; 4639 } ii_ibls1_fld_s; 4640} ii_ibls1_u_t; 4641 4642#endif 4643 4644 4645 4646 4647/************************************************************************ 4648 * * 4649 * This register should be loaded before a transfer is started. The * 4650 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 4651 * address as described in Section 1.3, Figure2 and Figure3. Since * 4652 * the bottom 7 bits of the address are always taken to be zero, BTE * 4653 * transfers are always cacheline-aligned. * 4654 * * 4655 ************************************************************************/ 4656 4657 4658 4659 4660#ifdef LITTLE_ENDIAN 4661 4662typedef union ii_ibsa1_u { 4663 bdrkreg_t ii_ibsa1_regval; 4664 struct { 4665 bdrkreg_t i_rsvd_1 : 7; 4666 bdrkreg_t i_addr : 33; 4667 bdrkreg_t i_rsvd : 24; 4668 } ii_ibsa1_fld_s; 4669} ii_ibsa1_u_t; 4670 4671#else 4672 4673typedef union ii_ibsa1_u { 4674 bdrkreg_t ii_ibsa1_regval; 4675 struct { 4676 bdrkreg_t i_rsvd : 24; 4677 bdrkreg_t i_addr : 33; 4678 bdrkreg_t i_rsvd_1 : 7; 4679 } ii_ibsa1_fld_s; 4680} ii_ibsa1_u_t; 4681 4682#endif 4683 4684 4685 4686 4687/************************************************************************ 4688 * * 4689 * This register should be loaded before a transfer is started. The * 4690 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 4691 * address as described in Section 1.3, Figure2 and Figure3. Since * 4692 * the bottom 7 bits of the address are always taken to be zero, BTE * 4693 * transfers are always cacheline-aligned. * 4694 * * 4695 ************************************************************************/ 4696 4697 4698 4699 4700#ifdef LITTLE_ENDIAN 4701 4702typedef union ii_ibda1_u { 4703 bdrkreg_t ii_ibda1_regval; 4704 struct { 4705 bdrkreg_t i_rsvd_1 : 7; 4706 bdrkreg_t i_addr : 33; 4707 bdrkreg_t i_rsvd : 24; 4708 } ii_ibda1_fld_s; 4709} ii_ibda1_u_t; 4710 4711#else 4712 4713typedef union ii_ibda1_u { 4714 bdrkreg_t ii_ibda1_regval; 4715 struct { 4716 bdrkreg_t i_rsvd : 24; 4717 bdrkreg_t i_addr : 33; 4718 bdrkreg_t i_rsvd_1 : 7; 4719 } ii_ibda1_fld_s; 4720} ii_ibda1_u_t; 4721 4722#endif 4723 4724 4725 4726 4727/************************************************************************ 4728 * * 4729 * Writing to this register sets up the attributes of the transfer * 4730 * and initiates the transfer operation. Reading this register has * 4731 * the side effect of terminating any transfer in progress. Note: * 4732 * stopping a transfer midstream could have an adverse impact on the * 4733 * other BTE. If a BTE stream has to be stopped (due to error * 4734 * handling for example), both BTE streams should be stopped and * 4735 * their transfers discarded. * 4736 * * 4737 ************************************************************************/ 4738 4739 4740 4741 4742#ifdef LITTLE_ENDIAN 4743 4744typedef union ii_ibct1_u { 4745 bdrkreg_t ii_ibct1_regval; 4746 struct { 4747 bdrkreg_t i_zerofill : 1; 4748 bdrkreg_t i_rsvd_2 : 3; 4749 bdrkreg_t i_notify : 1; 4750 bdrkreg_t i_rsvd_1 : 3; 4751 bdrkreg_t i_poison : 1; 4752 bdrkreg_t i_rsvd : 55; 4753 } ii_ibct1_fld_s; 4754} ii_ibct1_u_t; 4755 4756#else 4757 4758typedef union ii_ibct1_u { 4759 bdrkreg_t ii_ibct1_regval; 4760 struct { 4761 bdrkreg_t i_rsvd : 55; 4762 bdrkreg_t i_poison : 1; 4763 bdrkreg_t i_rsvd_1 : 3; 4764 bdrkreg_t i_notify : 1; 4765 bdrkreg_t i_rsvd_2 : 3; 4766 bdrkreg_t i_zerofill : 1; 4767 } ii_ibct1_fld_s; 4768} ii_ibct1_u_t; 4769 4770#endif 4771 4772 4773 4774 4775/************************************************************************ 4776 * * 4777 * This register contains the address to which the WINV is sent. * 4778 * This address has to be cache line aligned. * 4779 * * 4780 ************************************************************************/ 4781 4782 4783 4784 4785#ifdef LITTLE_ENDIAN 4786 4787typedef union ii_ibna1_u { 4788 bdrkreg_t ii_ibna1_regval; 4789 struct { 4790 bdrkreg_t i_rsvd_1 : 7; 4791 bdrkreg_t i_addr : 33; 4792 bdrkreg_t i_rsvd : 24; 4793 } ii_ibna1_fld_s; 4794} ii_ibna1_u_t; 4795 4796#else 4797 4798typedef union ii_ibna1_u { 4799 bdrkreg_t ii_ibna1_regval; 4800 struct { 4801 bdrkreg_t i_rsvd : 24; 4802 bdrkreg_t i_addr : 33; 4803 bdrkreg_t i_rsvd_1 : 7; 4804 } ii_ibna1_fld_s; 4805} ii_ibna1_u_t; 4806 4807#endif 4808 4809 4810 4811 4812/************************************************************************ 4813 * * 4814 * This register contains the programmable level as well as the node * 4815 * ID and PI unit of the processor to which the interrupt will be * 4816 * sent. * 4817 * * 4818 ************************************************************************/ 4819 4820 4821 4822 4823#ifdef LITTLE_ENDIAN 4824 4825typedef union ii_ibia1_u { 4826 bdrkreg_t ii_ibia1_regval; 4827 struct { 4828 bdrkreg_t i_pi_id : 1; 4829 bdrkreg_t i_node_id : 8; 4830 bdrkreg_t i_rsvd_1 : 7; 4831 bdrkreg_t i_level : 7; 4832 bdrkreg_t i_rsvd : 41; 4833 } ii_ibia1_fld_s; 4834} ii_ibia1_u_t; 4835 4836#else 4837 4838typedef union ii_ibia1_u { 4839 bdrkreg_t ii_ibia1_regval; 4840 struct { 4841 bdrkreg_t i_rsvd : 41; 4842 bdrkreg_t i_level : 7; 4843 bdrkreg_t i_rsvd_1 : 7; 4844 bdrkreg_t i_node_id : 8; 4845 bdrkreg_t i_pi_id : 1; 4846 } ii_ibia1_fld_s; 4847} ii_ibia1_u_t; 4848 4849#endif 4850 4851 4852 4853 4854/************************************************************************ 4855 * * 4856 * This register defines the resources that feed information into * 4857 * the two performance counters located in the IO Performance * 4858 * Profiling Register. There are 17 different quantities that can be * 4859 * measured. Given these 17 different options, the two performance * 4860 * counters have 15 of them in common; menu selections 0 through 0xE * 4861 * are identical for each performance counter. As for the other two * 4862 * options, one is available from one performance counter and the * 4863 * other is available from the other performance counter. Hence, the * 4864 * II supports all 17*16=272 possible combinations of quantities to * 4865 * measure. * 4866 * * 4867 ************************************************************************/ 4868 4869 4870 4871 4872#ifdef LITTLE_ENDIAN 4873 4874typedef union ii_ipcr_u { 4875 bdrkreg_t ii_ipcr_regval; 4876 struct { 4877 bdrkreg_t i_ippr0_c : 4; 4878 bdrkreg_t i_ippr1_c : 4; 4879 bdrkreg_t i_icct : 8; 4880 bdrkreg_t i_rsvd : 48; 4881 } ii_ipcr_fld_s; 4882} ii_ipcr_u_t; 4883 4884#else 4885 4886typedef union ii_ipcr_u { 4887 bdrkreg_t ii_ipcr_regval; 4888 struct { 4889 bdrkreg_t i_rsvd : 48; 4890 bdrkreg_t i_icct : 8; 4891 bdrkreg_t i_ippr1_c : 4; 4892 bdrkreg_t i_ippr0_c : 4; 4893 } ii_ipcr_fld_s; 4894} ii_ipcr_u_t; 4895 4896#endif 4897 4898 4899 4900 4901/************************************************************************ 4902 * * 4903 * * 4904 * * 4905 ************************************************************************/ 4906 4907 4908 4909 4910#ifdef LITTLE_ENDIAN 4911 4912typedef union ii_ippr_u { 4913 bdrkreg_t ii_ippr_regval; 4914 struct { 4915 bdrkreg_t i_ippr0 : 32; 4916 bdrkreg_t i_ippr1 : 32; 4917 } ii_ippr_fld_s; 4918} ii_ippr_u_t; 4919 4920#else 4921 4922typedef union ii_ippr_u { 4923 bdrkreg_t ii_ippr_regval; 4924 struct { 4925 bdrkreg_t i_ippr1 : 32; 4926 bdrkreg_t i_ippr0 : 32; 4927 } ii_ippr_fld_s; 4928} ii_ippr_u_t; 4929 4930#endif 4931 4932 4933 4934 4935 4936 4937#endif /* __ASSEMBLY__ */ 4938 4939/************************************************************************ 4940 * * 4941 * The following defines which were not formed into structures are * 4942 * probably indentical to another register, and the name of the * 4943 * register is provided against each of these registers. This * 4944 * information needs to be checked carefully * 4945 * * 4946 * IIO_ICRB1_A IIO_ICRB0_A * 4947 * IIO_ICRB1_B IIO_ICRB0_B * 4948 * IIO_ICRB1_C IIO_ICRB0_C * 4949 * IIO_ICRB1_D IIO_ICRB0_D * 4950 * IIO_ICRB2_A IIO_ICRB0_A * 4951 * IIO_ICRB2_B IIO_ICRB0_B * 4952 * IIO_ICRB2_C IIO_ICRB0_C * 4953 * IIO_ICRB2_D IIO_ICRB0_D * 4954 * IIO_ICRB3_A IIO_ICRB0_A * 4955 * IIO_ICRB3_B IIO_ICRB0_B * 4956 * IIO_ICRB3_C IIO_ICRB0_C * 4957 * IIO_ICRB3_D IIO_ICRB0_D * 4958 * IIO_ICRB4_A IIO_ICRB0_A * 4959 * IIO_ICRB4_B IIO_ICRB0_B * 4960 * IIO_ICRB4_C IIO_ICRB0_C * 4961 * IIO_ICRB4_D IIO_ICRB0_D * 4962 * IIO_ICRB5_A IIO_ICRB0_A * 4963 * IIO_ICRB5_B IIO_ICRB0_B * 4964 * IIO_ICRB5_C IIO_ICRB0_C * 4965 * IIO_ICRB5_D IIO_ICRB0_D * 4966 * IIO_ICRB6_A IIO_ICRB0_A * 4967 * IIO_ICRB6_B IIO_ICRB0_B * 4968 * IIO_ICRB6_C IIO_ICRB0_C * 4969 * IIO_ICRB6_D IIO_ICRB0_D * 4970 * IIO_ICRB7_A IIO_ICRB0_A * 4971 * IIO_ICRB7_B IIO_ICRB0_B * 4972 * IIO_ICRB7_C IIO_ICRB0_C * 4973 * IIO_ICRB7_D IIO_ICRB0_D * 4974 * IIO_ICRB8_A IIO_ICRB0_A * 4975 * IIO_ICRB8_B IIO_ICRB0_B * 4976 * IIO_ICRB8_C IIO_ICRB0_C * 4977 * IIO_ICRB8_D IIO_ICRB0_D * 4978 * IIO_ICRB9_A IIO_ICRB0_A * 4979 * IIO_ICRB9_B IIO_ICRB0_B * 4980 * IIO_ICRB9_C IIO_ICRB0_C * 4981 * IIO_ICRB9_D IIO_ICRB0_D * 4982 * IIO_ICRBA_A IIO_ICRB0_A * 4983 * IIO_ICRBA_B IIO_ICRB0_B * 4984 * IIO_ICRBA_C IIO_ICRB0_C * 4985 * IIO_ICRBA_D IIO_ICRB0_D * 4986 * IIO_ICRBB_A IIO_ICRB0_A * 4987 * IIO_ICRBB_B IIO_ICRB0_B * 4988 * IIO_ICRBB_C IIO_ICRB0_C * 4989 * IIO_ICRBB_D IIO_ICRB0_D * 4990 * IIO_ICRBC_A IIO_ICRB0_A * 4991 * IIO_ICRBC_B IIO_ICRB0_B * 4992 * IIO_ICRBC_C IIO_ICRB0_C * 4993 * IIO_ICRBC_D IIO_ICRB0_D * 4994 * IIO_ICRBD_A IIO_ICRB0_A * 4995 * IIO_ICRBD_B IIO_ICRB0_B * 4996 * IIO_ICRBD_C IIO_ICRB0_C * 4997 * IIO_ICRBD_D IIO_ICRB0_D * 4998 * IIO_ICRBE_A IIO_ICRB0_A * 4999 * IIO_ICRBE_B IIO_ICRB0_B * 5000 * IIO_ICRBE_C IIO_ICRB0_C * 5001 * IIO_ICRBE_D IIO_ICRB0_D * 5002 * * 5003 ************************************************************************/ 5004 5005 5006/************************************************************************ 5007 * * 5008 * MAKE ALL ADDITIONS AFTER THIS LINE * 5009 * * 5010 ************************************************************************/ 5011 5012 5013 5014 5015 5016#endif /* _ASM_IA64_SN_SN1_HUBIO_H */ 5017