1/* $Id: pciio.h,v 1.1.1.1 2008/10/15 03:29:03 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. 8 */ 9#ifndef _ASM_SN_PCI_PCIIO_H 10#define _ASM_SN_PCI_PCIIO_H 11 12/* 13 * pciio.h -- platform-independent PCI interface 14 */ 15 16#include <asm/sn/ioerror.h> 17#include <asm/sn/driver.h> 18#include <asm/sn/hcl.h> 19 20 21#ifndef __ASSEMBLY__ 22 23#include <asm/sn/dmamap.h> 24#include <asm/sn/alenlist.h> 25 26typedef int pciio_vendor_id_t; 27 28#define PCIIO_VENDOR_ID_NONE (-1) 29 30typedef int pciio_device_id_t; 31 32#define PCIIO_DEVICE_ID_NONE (-1) 33 34typedef uint8_t pciio_bus_t; /* PCI bus number (0..255) */ 35typedef uint8_t pciio_slot_t; /* PCI slot number (0..31, 255) */ 36typedef uint8_t pciio_function_t; /* PCI func number (0..7, 255) */ 37 38#define PCIIO_SLOTS ((pciio_slot_t)32) 39#define PCIIO_FUNCS ((pciio_function_t)8) 40 41#define PCIIO_SLOT_NONE ((pciio_slot_t)255) 42#define PCIIO_FUNC_NONE ((pciio_function_t)255) 43 44typedef int pciio_intr_line_t; /* PCI interrupt line(s) */ 45 46#define PCIIO_INTR_LINE(n) (0x1 << (n)) 47#define PCIIO_INTR_LINE_A (0x1) 48#define PCIIO_INTR_LINE_B (0x2) 49#define PCIIO_INTR_LINE_C (0x4) 50#define PCIIO_INTR_LINE_D (0x8) 51 52typedef int pciio_space_t; /* PCI address space designation */ 53 54#define PCIIO_SPACE_NONE (0) 55#define PCIIO_SPACE_ROM (1) 56#define PCIIO_SPACE_IO (2) 57/* PCIIO_SPACE_ (3) */ 58#define PCIIO_SPACE_MEM (4) 59#define PCIIO_SPACE_MEM32 (5) 60#define PCIIO_SPACE_MEM64 (6) 61#define PCIIO_SPACE_CFG (7) 62#define PCIIO_SPACE_WIN0 (8) 63#define PCIIO_SPACE_WIN(n) (PCIIO_SPACE_WIN0+(n)) /* 8..13 */ 64/* PCIIO_SPACE_ (14) */ 65#define PCIIO_SPACE_BAD (15) 66 67#define PCIIO_SPACE_USER0 (20) 68#define PCIIO_SPACE_USER(n) (PCIIO_SPACE_USER0+(n)) /* 20 .. ? */ 69 70/* 71 * PCI_NOWHERE is the error value returned in 72 * place of a PCI address when there is no 73 * corresponding address. 74 */ 75#define PCI_NOWHERE (0) 76 77/* 78 * Acceptable flag bits for pciio service calls 79 * 80 * PCIIO_FIXED: require that mappings be established 81 * using fixed sharable resources; address 82 * translation results will be permanently 83 * available. (PIOMAP_FIXED and DMAMAP_FIXED are 84 * the same numeric value and are acceptable). 85 * PCIIO_NOSLEEP: if any part of the operation would 86 * sleep waiting for resoruces, return an error 87 * instead. (PIOMAP_NOSLEEP and DMAMAP_NOSLEEP are 88 * the same numeric value and are acceptable). 89 * PCIIO_INPLACE: when operating on alenlist structures, 90 * reuse the source alenlist rather than creating a 91 * new one. (PIOMAP_INPLACE and DMAMAP_INPLACE are 92 * the same numeric value and are acceptable). 93 * 94 * PCIIO_DMA_CMD: configure this stream as a 95 * generic "command" stream. Generally this 96 * means turn off prefetchers and write 97 * gatherers, and whatever else might be 98 * necessary to make command ring DMAs 99 * work as expected. 100 * PCIIO_DMA_DATA: configure this stream as a 101 * generic "data" stream. Generally, this 102 * means turning on prefetchers and write 103 * gatherers, and anything else that might 104 * increase the DMA throughput (short of 105 * using "high priority" or "real time" 106 * resources that may lower overall system 107 * performance). 108 * PCIIO_DMA_A64: this device is capable of 109 * using 64-bit DMA addresses. Unless this 110 * flag is specified, it is assumed that 111 * the DMA address must be in the low 4G 112 * of PCI space. 113 * PCIIO_PREFETCH: if there are prefetchers 114 * available, they can be turned on. 115 * PCIIO_NOPREFETCH: any prefetchers along 116 * the dma path should be turned off. 117 * PCIIO_WRITE_GATHER: if there are write gatherers 118 * available, they can be turned on. 119 * PCIIO_NOWRITE_GATHER: any write gatherers along 120 * the dma path should be turned off. 121 * 122 * PCIIO_BYTE_STREAM: the DMA stream represents a group 123 * of ordered bytes. Arrange all byte swapping 124 * hardware so that the bytes land in the correct 125 * order. This is a common setting for data 126 * channels, but is NOT implied by PCIIO_DMA_DATA. 127 * PCIIO_WORD_VALUES: the DMA stream is used to 128 * communicate quantities stored in multiple bytes, 129 * and the device doing the DMA is little-endian; 130 * arrange any swapping hardware so that 131 * 32-bit-wide values are maintained. This is a 132 * common setting for command rings that contain 133 * DMA addresses and counts, but is NOT implied by 134 * PCIIO_DMA_CMD. CPU Accesses to 16-bit fields 135 * must have their address xor-ed with 2, and 136 * accesses to individual bytes must have their 137 * addresses xor-ed with 3 relative to what the 138 * device expects. 139 * 140 * NOTE: any "provider specific" flags that 141 * conflict with the generic flags will 142 * override the generic flags, locally 143 * at that provider. 144 * 145 * Also, note that PCI-generic flags (PCIIO_) are 146 * in bits 0-14. The upper bits, 15-31, are reserved 147 * for PCI implementation-specific flags. 148 */ 149 150#define PCIIO_FIXED DMAMAP_FIXED 151#define PCIIO_NOSLEEP DMAMAP_NOSLEEP 152#define PCIIO_INPLACE DMAMAP_INPLACE 153 154#define PCIIO_DMA_CMD 0x0010 155#define PCIIO_DMA_DATA 0x0020 156#define PCIIO_DMA_A64 0x0040 157 158#define PCIIO_WRITE_GATHER 0x0100 159#define PCIIO_NOWRITE_GATHER 0x0200 160#define PCIIO_PREFETCH 0x0400 161#define PCIIO_NOPREFETCH 0x0800 162 163/* Requesting an endianness setting that the 164 * underlieing hardware can not support 165 * WILL result in a failure to allocate 166 * dmamaps or complete a dmatrans. 167 */ 168#define PCIIO_BYTE_STREAM 0x1000 /* set BYTE SWAP for "byte stream" */ 169#define PCIIO_WORD_VALUES 0x2000 /* set BYTE SWAP for "word values" */ 170 171/* 172 * Interface to deal with PCI endianness. 173 * The driver calls pciio_endian_set once, supplying the actual endianness of 174 * the device and the desired endianness. On SGI systems, only use LITTLE if 175 * dealing with a driver that does software swizzling. Most of the time, 176 * it's preferable to request BIG. The return value indicates the endianness 177 * that is actually achieved. On systems that support hardware swizzling, 178 * the achieved endianness will be the desired endianness. On systems without 179 * swizzle hardware, the achieved endianness will be the device's endianness. 180 */ 181typedef enum pciio_endian_e { 182 PCIDMA_ENDIAN_BIG, 183 PCIDMA_ENDIAN_LITTLE 184} pciio_endian_t; 185 186/* 187 * Interface to set PCI arbitration priority for devices that require 188 * realtime characteristics. pciio_priority_set is used to switch a 189 * device between the PCI high-priority arbitration ring and the low 190 * priority arbitration ring. 191 * 192 * (Note: this is strictly for the PCI arbitrary priority. It has 193 * no direct relationship to GBR.) 194 */ 195typedef enum pciio_priority_e { 196 PCI_PRIO_LOW, 197 PCI_PRIO_HIGH 198} pciio_priority_t; 199 200/* 201 * handles of various sorts 202 */ 203typedef struct pciio_piomap_s *pciio_piomap_t; 204typedef struct pciio_dmamap_s *pciio_dmamap_t; 205typedef struct pciio_intr_s *pciio_intr_t; 206typedef struct pciio_info_s *pciio_info_t; 207typedef struct pciio_piospace_s *pciio_piospace_t; 208 209/* PIO MANAGEMENT */ 210 211/* 212 * A NOTE ON PCI PIO ADDRESSES 213 * 214 * PCI supports three different address spaces: CFG 215 * space, MEM space and I/O space. Further, each 216 * card always accepts CFG accesses at an address 217 * based on which slot it is attached to, but can 218 * decode up to six address ranges. 219 * 220 * Assignment of the base address registers for all 221 * PCI devices is handled centrally; most commonly, 222 * device drivers will want to talk to offsets 223 * within one or another of the address ranges. In 224 * order to do this, which of these "address 225 * spaces" the PIO is directed into must be encoded 226 * in the flag word. 227 * 228 * We reserve the right to defer allocation of PCI 229 * address space for a device window until the 230 * driver makes a piomap_alloc or piotrans_addr 231 * request. 232 * 233 * If a device driver mucks with its device's base 234 * registers through a PIO mapping to CFG space, 235 * results of further PIO through the corresponding 236 * window are UNDEFINED. 237 * 238 * Windows are named by the index in the base 239 * address register set for the device of the 240 * desired register; IN THE CASE OF 64 BIT base 241 * registers, the index should be to the word of 242 * the register that contains the mapping type 243 * bits; since the PCI CFG space is natively 244 * organized little-endian fashion, this is the 245 * first of the two words. 246 * 247 * AT THE MOMENT, any required corrections for 248 * endianness are the responsibility of the device 249 * driver; not all platforms support control in 250 * hardware of byteswapping hardware. We anticipate 251 * providing flag bits to the PIO and DMA 252 * management interfaces to request different 253 * configurations of byteswapping hardware. 254 * 255 * PIO Accesses to CFG space via the "Bridge" ASIC 256 * used in IP30 platforms preserve the native byte 257 * significance within the 32-bit word; byte 258 * addresses for single byte accesses need to be 259 * XORed with 3, and addresses for 16-bit accesses 260 * need to be XORed with 2. 261 * 262 * The IOC3 used on IP30, and other SGI PCI devices 263 * as well, require use of 32-bit accesses to their 264 * configuration space registers. Any potential PCI 265 * bus providers need to be aware of this requirement. 266 */ 267 268#define PCIIO_PIOMAP_CFG (0x1) 269#define PCIIO_PIOMAP_MEM (0x2) 270#define PCIIO_PIOMAP_IO (0x4) 271#define PCIIO_PIOMAP_WIN(n) (0x8+(n)) 272 273typedef pciio_piomap_t 274pciio_piomap_alloc_f (devfs_handle_t dev, /* set up mapping for this device */ 275 device_desc_t dev_desc, /* device descriptor */ 276 pciio_space_t space, /* which address space */ 277 iopaddr_t pcipio_addr, /* starting address */ 278 size_t byte_count, 279 size_t byte_count_max, /* maximum size of a mapping */ 280 unsigned flags); /* defined in sys/pio.h */ 281 282typedef void 283pciio_piomap_free_f (pciio_piomap_t pciio_piomap); 284 285typedef caddr_t 286pciio_piomap_addr_f (pciio_piomap_t pciio_piomap, /* mapping resources */ 287 iopaddr_t pciio_addr, /* map for this pcipio address */ 288 size_t byte_count); /* map this many bytes */ 289 290typedef void 291pciio_piomap_done_f (pciio_piomap_t pciio_piomap); 292 293typedef caddr_t 294pciio_piotrans_addr_f (devfs_handle_t dev, /* translate for this device */ 295 device_desc_t dev_desc, /* device descriptor */ 296 pciio_space_t space, /* which address space */ 297 iopaddr_t pciio_addr, /* starting address */ 298 size_t byte_count, /* map this many bytes */ 299 unsigned flags); 300 301typedef caddr_t 302pciio_pio_addr_f (devfs_handle_t dev, /* translate for this device */ 303 device_desc_t dev_desc, /* device descriptor */ 304 pciio_space_t space, /* which address space */ 305 iopaddr_t pciio_addr, /* starting address */ 306 size_t byte_count, /* map this many bytes */ 307 pciio_piomap_t *mapp, /* in case a piomap was needed */ 308 unsigned flags); 309 310typedef iopaddr_t 311pciio_piospace_alloc_f (devfs_handle_t dev, /* PIO space for this device */ 312 device_desc_t dev_desc, /* Device descriptor */ 313 pciio_space_t space, /* which address space */ 314 size_t byte_count, /* Number of bytes of space */ 315 size_t alignment); /* Alignment of allocation */ 316 317typedef void 318pciio_piospace_free_f (devfs_handle_t dev, /* Device freeing space */ 319 pciio_space_t space, /* Which space is freed */ 320 iopaddr_t pci_addr, /* Address being freed */ 321 size_t size); /* Size freed */ 322 323/* DMA MANAGEMENT */ 324 325typedef pciio_dmamap_t 326pciio_dmamap_alloc_f (devfs_handle_t dev, /* set up mappings for this device */ 327 device_desc_t dev_desc, /* device descriptor */ 328 size_t byte_count_max, /* max size of a mapping */ 329 unsigned flags); /* defined in dma.h */ 330 331typedef void 332pciio_dmamap_free_f (pciio_dmamap_t dmamap); 333 334typedef iopaddr_t 335pciio_dmamap_addr_f (pciio_dmamap_t dmamap, /* use these mapping resources */ 336 paddr_t paddr, /* map for this address */ 337 size_t byte_count); /* map this many bytes */ 338 339typedef alenlist_t 340pciio_dmamap_list_f (pciio_dmamap_t dmamap, /* use these mapping resources */ 341 alenlist_t alenlist, /* map this address/length list */ 342 unsigned flags); 343 344typedef void 345pciio_dmamap_done_f (pciio_dmamap_t dmamap); 346 347typedef iopaddr_t 348pciio_dmatrans_addr_f (devfs_handle_t dev, /* translate for this device */ 349 device_desc_t dev_desc, /* device descriptor */ 350 paddr_t paddr, /* system physical address */ 351 size_t byte_count, /* length */ 352 unsigned flags); /* defined in dma.h */ 353 354typedef alenlist_t 355pciio_dmatrans_list_f (devfs_handle_t dev, /* translate for this device */ 356 device_desc_t dev_desc, /* device descriptor */ 357 alenlist_t palenlist, /* system address/length list */ 358 unsigned flags); /* defined in dma.h */ 359 360typedef void 361pciio_dmamap_drain_f (pciio_dmamap_t map); 362 363typedef void 364pciio_dmaaddr_drain_f (devfs_handle_t vhdl, 365 paddr_t addr, 366 size_t bytes); 367 368typedef void 369pciio_dmalist_drain_f (devfs_handle_t vhdl, 370 alenlist_t list); 371 372/* INTERRUPT MANAGEMENT */ 373 374typedef pciio_intr_t 375pciio_intr_alloc_f (devfs_handle_t dev, /* which PCI device */ 376 device_desc_t dev_desc, /* device descriptor */ 377 pciio_intr_line_t lines, /* which line(s) will be used */ 378 devfs_handle_t owner_dev); /* owner of this intr */ 379 380typedef void 381pciio_intr_free_f (pciio_intr_t intr_hdl); 382 383typedef int 384pciio_intr_connect_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ 385 386typedef void 387pciio_intr_disconnect_f (pciio_intr_t intr_hdl); 388 389typedef devfs_handle_t 390pciio_intr_cpu_get_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ 391 392/* CONFIGURATION MANAGEMENT */ 393 394typedef void 395pciio_provider_startup_f (devfs_handle_t pciio_provider); 396 397typedef void 398pciio_provider_shutdown_f (devfs_handle_t pciio_provider); 399 400typedef int 401pciio_reset_f (devfs_handle_t conn); /* pci connection point */ 402 403typedef int 404pciio_write_gather_flush_f (devfs_handle_t dev); /* Device flushing buffers */ 405 406typedef pciio_endian_t /* actual endianness */ 407pciio_endian_set_f (devfs_handle_t dev, /* specify endianness for this device */ 408 pciio_endian_t device_end, /* endianness of device */ 409 pciio_endian_t desired_end); /* desired endianness */ 410 411typedef pciio_priority_t 412pciio_priority_set_f (devfs_handle_t pcicard, 413 pciio_priority_t device_prio); 414 415typedef uint64_t 416pciio_config_get_f (devfs_handle_t conn, /* pci connection point */ 417 unsigned reg, /* register byte offset */ 418 unsigned size); /* width in bytes (1..4) */ 419 420typedef void 421pciio_config_set_f (devfs_handle_t conn, /* pci connection point */ 422 unsigned reg, /* register byte offset */ 423 unsigned size, /* width in bytes (1..4) */ 424 uint64_t value); /* value to store */ 425 426typedef int 427pciio_error_devenable_f (devfs_handle_t pconn_vhdl, int error_code); 428 429typedef pciio_slot_t 430pciio_error_extract_f (devfs_handle_t vhdl, 431 pciio_space_t *spacep, 432 iopaddr_t *addrp); 433 434typedef void 435pciio_driver_reg_callback_f (devfs_handle_t conn, 436 int key1, 437 int key2, 438 int error); 439 440typedef void 441pciio_driver_unreg_callback_f (devfs_handle_t conn, /* pci connection point */ 442 int key1, 443 int key2, 444 int error); 445 446typedef int 447pciio_device_unregister_f (devfs_handle_t conn); 448 449typedef int 450pciio_dma_enabled_f (devfs_handle_t conn); 451 452/* 453 * Adapters that provide a PCI interface adhere to this software interface. 454 */ 455typedef struct pciio_provider_s { 456 /* PIO MANAGEMENT */ 457 pciio_piomap_alloc_f *piomap_alloc; 458 pciio_piomap_free_f *piomap_free; 459 pciio_piomap_addr_f *piomap_addr; 460 pciio_piomap_done_f *piomap_done; 461 pciio_piotrans_addr_f *piotrans_addr; 462 pciio_piospace_alloc_f *piospace_alloc; 463 pciio_piospace_free_f *piospace_free; 464 465 /* DMA MANAGEMENT */ 466 pciio_dmamap_alloc_f *dmamap_alloc; 467 pciio_dmamap_free_f *dmamap_free; 468 pciio_dmamap_addr_f *dmamap_addr; 469 pciio_dmamap_list_f *dmamap_list; 470 pciio_dmamap_done_f *dmamap_done; 471 pciio_dmatrans_addr_f *dmatrans_addr; 472 pciio_dmatrans_list_f *dmatrans_list; 473 pciio_dmamap_drain_f *dmamap_drain; 474 pciio_dmaaddr_drain_f *dmaaddr_drain; 475 pciio_dmalist_drain_f *dmalist_drain; 476 477 /* INTERRUPT MANAGEMENT */ 478 pciio_intr_alloc_f *intr_alloc; 479 pciio_intr_free_f *intr_free; 480 pciio_intr_connect_f *intr_connect; 481 pciio_intr_disconnect_f *intr_disconnect; 482 pciio_intr_cpu_get_f *intr_cpu_get; 483 484 /* CONFIGURATION MANAGEMENT */ 485 pciio_provider_startup_f *provider_startup; 486 pciio_provider_shutdown_f *provider_shutdown; 487 pciio_reset_f *reset; 488 pciio_write_gather_flush_f *write_gather_flush; 489 pciio_endian_set_f *endian_set; 490 pciio_priority_set_f *priority_set; 491 pciio_config_get_f *config_get; 492 pciio_config_set_f *config_set; 493 494 /* Error handling interface */ 495 pciio_error_devenable_f *error_devenable; 496 pciio_error_extract_f *error_extract; 497 498 /* Callback support */ 499 pciio_driver_reg_callback_f *driver_reg_callback; 500 pciio_driver_unreg_callback_f *driver_unreg_callback; 501 pciio_device_unregister_f *device_unregister; 502 pciio_dma_enabled_f *dma_enabled; 503} pciio_provider_t; 504 505/* PCI devices use these standard PCI provider interfaces */ 506extern pciio_piomap_alloc_f pciio_piomap_alloc; 507extern pciio_piomap_free_f pciio_piomap_free; 508extern pciio_piomap_addr_f pciio_piomap_addr; 509extern pciio_piomap_done_f pciio_piomap_done; 510extern pciio_piotrans_addr_f pciio_piotrans_addr; 511extern pciio_pio_addr_f pciio_pio_addr; 512extern pciio_piospace_alloc_f pciio_piospace_alloc; 513extern pciio_piospace_free_f pciio_piospace_free; 514extern pciio_dmamap_alloc_f pciio_dmamap_alloc; 515extern pciio_dmamap_free_f pciio_dmamap_free; 516extern pciio_dmamap_addr_f pciio_dmamap_addr; 517extern pciio_dmamap_list_f pciio_dmamap_list; 518extern pciio_dmamap_done_f pciio_dmamap_done; 519extern pciio_dmatrans_addr_f pciio_dmatrans_addr; 520extern pciio_dmatrans_list_f pciio_dmatrans_list; 521extern pciio_dmamap_drain_f pciio_dmamap_drain; 522extern pciio_dmaaddr_drain_f pciio_dmaaddr_drain; 523extern pciio_dmalist_drain_f pciio_dmalist_drain; 524extern pciio_intr_alloc_f pciio_intr_alloc; 525extern pciio_intr_free_f pciio_intr_free; 526extern pciio_intr_connect_f pciio_intr_connect; 527extern pciio_intr_disconnect_f pciio_intr_disconnect; 528extern pciio_intr_cpu_get_f pciio_intr_cpu_get; 529extern pciio_provider_startup_f pciio_provider_startup; 530extern pciio_provider_shutdown_f pciio_provider_shutdown; 531extern pciio_reset_f pciio_reset; 532extern pciio_write_gather_flush_f pciio_write_gather_flush; 533extern pciio_endian_set_f pciio_endian_set; 534extern pciio_priority_set_f pciio_priority_set; 535extern pciio_config_get_f pciio_config_get; 536extern pciio_config_set_f pciio_config_set; 537extern pciio_error_devenable_f pciio_error_devenable; 538extern pciio_error_extract_f pciio_error_extract; 539 540/* Widgetdev in the IOERROR structure is encoded as follows. 541 * +---------------------------+ 542 * | slot (7:3) | function(2:0)| 543 * +---------------------------+ 544 * Following are the convenience interfaces to get at form 545 * a widgetdev or to break it into its constituents. 546 */ 547 548#define PCIIO_WIDGETDEV_SLOT_SHFT 3 549#define PCIIO_WIDGETDEV_SLOT_MASK 0x1f 550#define PCIIO_WIDGETDEV_FUNC_MASK 0x7 551 552#define pciio_widgetdev_create(slot,func) \ 553 (((slot) << PCIIO_WIDGETDEV_SLOT_SHFT) + (func)) 554 555#define pciio_widgetdev_slot_get(wdev) \ 556 (((wdev) >> PCIIO_WIDGETDEV_SLOT_SHFT) & PCIIO_WIDGETDEV_SLOT_MASK) 557 558#define pciio_widgetdev_func_get(wdev) \ 559 ((wdev) & PCIIO_WIDGETDEV_FUNC_MASK) 560 561 562/* Generic PCI card initialization interface 563 */ 564 565extern int 566pciio_driver_register (pciio_vendor_id_t vendor_id, /* card's vendor number */ 567 pciio_device_id_t device_id, /* card's device number */ 568 char *driver_prefix, /* driver prefix */ 569 unsigned flags); 570 571extern void 572pciio_error_register (devfs_handle_t pconn, /* which slot */ 573 error_handler_f *efunc, /* function to call */ 574 error_handler_arg_t einfo); /* first parameter */ 575 576extern void pciio_driver_unregister(char *driver_prefix); 577 578typedef void pciio_iter_f(devfs_handle_t pconn); /* a connect point */ 579 580extern void pciio_iterate(char *driver_prefix, 581 pciio_iter_f *func); 582 583/* Interfaces used by PCI Bus Providers to talk to 584 * the Generic PCI layer. 585 */ 586extern devfs_handle_t 587pciio_device_register (devfs_handle_t connectpt, /* vertex at center of bus */ 588 devfs_handle_t master, /* card's master ASIC (pci provider) */ 589 pciio_slot_t slot, /* card's slot (0..?) */ 590 pciio_function_t func, /* card's func (0..?) */ 591 pciio_vendor_id_t vendor, /* card's vendor number */ 592 pciio_device_id_t device); /* card's device number */ 593 594extern void 595pciio_device_unregister(devfs_handle_t connectpt); 596 597extern pciio_info_t 598pciio_device_info_new (pciio_info_t pciio_info, /* preallocated info struct */ 599 devfs_handle_t master, /* card's master ASIC (pci provider) */ 600 pciio_slot_t slot, /* card's slot (0..?) */ 601 pciio_function_t func, /* card's func (0..?) */ 602 pciio_vendor_id_t vendor, /* card's vendor number */ 603 pciio_device_id_t device); /* card's device number */ 604 605extern void 606pciio_device_info_free(pciio_info_t pciio_info); 607 608extern devfs_handle_t 609pciio_device_info_register( 610 devfs_handle_t connectpt, /* vertex at center of bus */ 611 pciio_info_t pciio_info); /* details about conn point */ 612 613extern void 614pciio_device_info_unregister( 615 devfs_handle_t connectpt, /* vertex at center of bus */ 616 pciio_info_t pciio_info); /* details about conn point */ 617 618 619extern int 620pciio_device_attach( 621 devfs_handle_t pcicard, /* vertex created by pciio_device_register */ 622 int drv_flags); 623extern int 624pciio_device_detach( 625 devfs_handle_t pcicard, /* vertex created by pciio_device_register */ 626 int drv_flags); 627 628/* 629 * Generic PCI interface, for use with all PCI providers 630 * and all PCI devices. 631 */ 632 633/* Generic PCI interrupt interfaces */ 634extern devfs_handle_t pciio_intr_dev_get(pciio_intr_t pciio_intr); 635extern devfs_handle_t pciio_intr_cpu_get(pciio_intr_t pciio_intr); 636 637/* Generic PCI pio interfaces */ 638extern devfs_handle_t pciio_pio_dev_get(pciio_piomap_t pciio_piomap); 639extern pciio_slot_t pciio_pio_slot_get(pciio_piomap_t pciio_piomap); 640extern pciio_space_t pciio_pio_space_get(pciio_piomap_t pciio_piomap); 641extern iopaddr_t pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap); 642extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap); 643extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap); 644 645#ifdef LATER 646#ifdef USE_PCI_PIO 647extern uint8_t pciio_pio_read8(volatile uint8_t *addr); 648extern uint16_t pciio_pio_read16(volatile uint16_t *addr); 649extern uint32_t pciio_pio_read32(volatile uint32_t *addr); 650extern uint64_t pciio_pio_read64(volatile uint64_t *addr); 651extern void pciio_pio_write8(uint8_t val, volatile uint8_t *addr); 652extern void pciio_pio_write16(uint16_t val, volatile uint16_t *addr); 653extern void pciio_pio_write32(uint32_t val, volatile uint32_t *addr); 654extern void pciio_pio_write64(uint64_t val, volatile uint64_t *addr); 655#else /* !USE_PCI_PIO */ 656__inline uint8_t pciio_pio_read8(volatile uint8_t *addr) 657{ 658 return *addr; 659} 660__inline uint16_t pciio_pio_read16(volatile uint16_t *addr) 661{ 662 return *addr; 663} 664__inline uint32_t pciio_pio_read32(volatile uint32_t *addr) 665{ 666 return *addr; 667} 668__inline uint64_t pciio_pio_read64(volatile uint64_t *addr) 669{ 670 return *addr; 671} 672__inline void pciio_pio_write8(uint8_t val, volatile uint8_t *addr) 673{ 674 *addr = val; 675} 676__inline void pciio_pio_write16(uint16_t val, volatile uint16_t *addr) 677{ 678 *addr = val; 679} 680__inline void pciio_pio_write32(uint32_t val, volatile uint32_t *addr) 681{ 682 *addr = val; 683} 684__inline void pciio_pio_write64(uint64_t val, volatile uint64_t *addr) 685{ 686 *addr = val; 687} 688#endif /* USE_PCI_PIO */ 689#endif /* LATER */ 690 691/* Generic PCI dma interfaces */ 692extern devfs_handle_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); 693 694/* Register/unregister PCI providers and get implementation handle */ 695extern void pciio_provider_register(devfs_handle_t provider, pciio_provider_t *pciio_fns); 696extern void pciio_provider_unregister(devfs_handle_t provider); 697extern pciio_provider_t *pciio_provider_fns_get(devfs_handle_t provider); 698 699/* Generic pci slot information access interface */ 700extern pciio_info_t pciio_info_chk(devfs_handle_t vhdl); 701extern pciio_info_t pciio_info_get(devfs_handle_t vhdl); 702extern void pciio_info_set(devfs_handle_t vhdl, pciio_info_t widget_info); 703extern devfs_handle_t pciio_info_dev_get(pciio_info_t pciio_info); 704extern pciio_bus_t pciio_info_bus_get(pciio_info_t pciio_info); 705extern pciio_slot_t pciio_info_slot_get(pciio_info_t pciio_info); 706extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info); 707extern pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t pciio_info); 708extern pciio_device_id_t pciio_info_device_id_get(pciio_info_t pciio_info); 709extern devfs_handle_t pciio_info_master_get(pciio_info_t pciio_info); 710extern arbitrary_info_t pciio_info_mfast_get(pciio_info_t pciio_info); 711extern pciio_provider_t *pciio_info_pops_get(pciio_info_t pciio_info); 712extern error_handler_f *pciio_info_efunc_get(pciio_info_t); 713extern error_handler_arg_t *pciio_info_einfo_get(pciio_info_t); 714extern pciio_space_t pciio_info_bar_space_get(pciio_info_t, int); 715extern iopaddr_t pciio_info_bar_base_get(pciio_info_t, int); 716extern size_t pciio_info_bar_size_get(pciio_info_t, int); 717extern iopaddr_t pciio_info_rom_base_get(pciio_info_t); 718extern size_t pciio_info_rom_size_get(pciio_info_t); 719 720extern int pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *); 721extern int pciio_dma_enabled(devfs_handle_t); 722 723#endif /* C or C++ */ 724#endif /* _ASM_SN_PCI_PCIIO_H */ 725