1/* $Id: bridge.h,v 1.1.1.1 2008/10/15 03:29:03 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. 8 */ 9#ifndef _ASM_SN_PCI_BRIDGE_H 10#define _ASM_SN_PCI_BRIDGE_H 11 12 13/* 14 * bridge.h - header file for bridge chip and bridge portion of xbridge chip 15 */ 16 17#include <asm/sn/xtalk/xwidget.h> 18 19/* I/O page size */ 20 21#if _PAGESZ == 4096 22#define IOPFNSHIFT 12 /* 4K per mapped page */ 23#else 24#define IOPFNSHIFT 14 /* 16K per mapped page */ 25#endif /* _PAGESZ */ 26 27#define IOPGSIZE (1 << IOPFNSHIFT) 28#define IOPG(x) ((x) >> IOPFNSHIFT) 29#define IOPGOFF(x) ((x) & (IOPGSIZE-1)) 30 31/* Bridge RAM sizes */ 32 33#define BRIDGE_INTERNAL_ATES 128 34#define XBRIDGE_INTERNAL_ATES 1024 35 36#define BRIDGE_ATE_RAM_SIZE (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */ 37#define XBRIDGE_ATE_RAM_SIZE (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */ 38 39#define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */ 40 /* map to each device's */ 41 /* config space */ 42#define BRIDGE_CONFIG1_BASE 0x28000 /* type 1 device config space */ 43#define BRIDGE_CONFIG_END 0x30000 44#define BRIDGE_CONFIG_SLOT_SIZE 0x1000 /* each map == 4k */ 45 46#define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */ 47#define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */ 48#define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */ 49#define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */ 50 51/* ======================================================================== 52 * Bridge address map 53 */ 54 55#ifndef __ASSEMBLY__ 56 57#ifdef __cplusplus 58extern "C" { 59#endif 60 61/* 62 * All accesses to bridge hardware registers must be done 63 * using 32-bit loads and stores. 64 */ 65typedef uint32_t bridgereg_t; 66 67typedef uint64_t bridge_ate_t; 68 69/* pointers to bridge ATEs 70 * are always "pointer to volatile" 71 */ 72typedef volatile bridge_ate_t *bridge_ate_p; 73 74/* 75 * It is generally preferred that hardware registers on the bridge 76 * are located from C code via this structure. 77 * 78 * Generated from Bridge spec dated 04oct95 79 */ 80 81#ifdef LITTLE_ENDIAN 82 83typedef volatile struct bridge_s { 84 85 /* Local Registers 0x000000-0x00FFFF */ 86 87 /* standard widget configuration 0x000000-0x000057 */ 88 widget_cfg_t b_widget; /* 0x000000 */ 89 90 /* helper fieldnames for accessing bridge widget */ 91 92#define b_wid_id b_widget.w_id 93#define b_wid_stat b_widget.w_status 94#define b_wid_err_upper b_widget.w_err_upper_addr 95#define b_wid_err_lower b_widget.w_err_lower_addr 96#define b_wid_control b_widget.w_control 97#define b_wid_req_timeout b_widget.w_req_timeout 98#define b_wid_int_upper b_widget.w_intdest_upper_addr 99#define b_wid_int_lower b_widget.w_intdest_lower_addr 100#define b_wid_err_cmdword b_widget.w_err_cmd_word 101#define b_wid_llp b_widget.w_llp_cfg 102#define b_wid_tflush b_widget.w_tflush 103 104 /* 105 * we access these through synergy unswizzled space, so the address 106 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) 107 * That's why we put the register first and filler second. 108 */ 109 /* bridge-specific widget configuration 0x000058-0x00007F */ 110 bridgereg_t b_wid_aux_err; /* 0x00005C */ 111 bridgereg_t _pad_000058; 112 113 bridgereg_t b_wid_resp_upper; /* 0x000064 */ 114 bridgereg_t _pad_000060; 115 116 bridgereg_t b_wid_resp_lower; /* 0x00006C */ 117 bridgereg_t _pad_000068; 118 119 bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ 120 bridgereg_t _pad_000070; 121 122 bridgereg_t _pad_000078[2]; 123 124 /* PMU & Map 0x000080-0x00008F */ 125 bridgereg_t b_dir_map; /* 0x000084 */ 126 bridgereg_t _pad_000080; 127 bridgereg_t _pad_000088[2]; 128 129 /* SSRAM 0x000090-0x00009F */ 130 bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ 131 bridgereg_t _pad_000090; 132#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ 133#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */ 134 bridgereg_t _pad_000098[2]; 135 136 /* Arbitration 0x0000A0-0x0000AF */ 137 bridgereg_t b_arb; /* 0x0000A4 */ 138 bridgereg_t _pad_0000A0; 139 bridgereg_t _pad_0000A8[2]; 140 141 /* Number In A Can 0x0000B0-0x0000BF */ 142 bridgereg_t b_nic; /* 0x0000B4 */ 143 bridgereg_t _pad_0000B0; 144 bridgereg_t _pad_0000B8[2]; 145 146 /* PCI/GIO 0x0000C0-0x0000FF */ 147 bridgereg_t b_bus_timeout; /* 0x0000C4 */ 148 bridgereg_t _pad_0000C0; 149#define b_pci_bus_timeout b_bus_timeout 150 151 bridgereg_t b_pci_cfg; /* 0x0000CC */ 152 bridgereg_t _pad_0000C8; 153 154 bridgereg_t b_pci_err_upper; /* 0x0000D4 */ 155 bridgereg_t _pad_0000D0; 156 157 bridgereg_t b_pci_err_lower; /* 0x0000DC */ 158 bridgereg_t _pad_0000D8; 159 bridgereg_t _pad_0000E0[8]; 160#define b_gio_err_lower b_pci_err_lower 161#define b_gio_err_upper b_pci_err_upper 162 163 /* Interrupt 0x000100-0x0001FF */ 164 bridgereg_t b_int_status; /* 0x000104 */ 165 bridgereg_t _pad_000100; 166 167 bridgereg_t b_int_enable; /* 0x00010C */ 168 bridgereg_t _pad_000108; 169 170 bridgereg_t b_int_rst_stat; /* 0x000114 */ 171 bridgereg_t _pad_000110; 172 173 bridgereg_t b_int_mode; /* 0x00011C */ 174 bridgereg_t _pad_000118; 175 176 bridgereg_t b_int_device; /* 0x000124 */ 177 bridgereg_t _pad_000120; 178 179 bridgereg_t b_int_host_err; /* 0x00012C */ 180 bridgereg_t _pad_000128; 181 182 struct { 183 bridgereg_t addr; /* 0x0001{34,,,6C} */ 184 bridgereg_t __pad; /* 0x0001{30,,,68} */ 185 } b_int_addr[8]; /* 0x000130 */ 186 187 bridgereg_t b_err_int_view; /* 0x000174 */ 188 bridgereg_t _pad_000170; 189 190 bridgereg_t b_mult_int; /* 0x00017c */ 191 bridgereg_t _pad_000178; 192 193 struct { 194 bridgereg_t intr; /* 0x0001{84,,,BC} */ 195 bridgereg_t __pad; /* 0x0001{80,,,B8} */ 196 } b_force_always[8]; /* 0x000180 */ 197 198 struct { 199 bridgereg_t intr; /* 0x0001{C4,,,FC} */ 200 bridgereg_t __pad; /* 0x0001{C0,,,F8} */ 201 } b_force_pin[8]; /* 0x0001C0 */ 202 203 /* Device 0x000200-0x0003FF */ 204 struct { 205 bridgereg_t reg; /* 0x0002{04,,,3C} */ 206 bridgereg_t __pad; /* 0x0002{00,,,38} */ 207 } b_device[8]; /* 0x000200 */ 208 209 struct { 210 bridgereg_t reg; /* 0x0002{44,,,7C} */ 211 bridgereg_t __pad; /* 0x0002{40,,,78} */ 212 } b_wr_req_buf[8]; /* 0x000240 */ 213 214 struct { 215 bridgereg_t reg; /* 0x0002{84,,,8C} */ 216 bridgereg_t __pad; /* 0x0002{80,,,88} */ 217 } b_rrb_map[2]; /* 0x000280 */ 218#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ 219#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ 220 221 bridgereg_t b_resp_status; /* 0x000294 */ 222 bridgereg_t _pad_000290; 223 224 bridgereg_t b_resp_clear; /* 0x00029C */ 225 bridgereg_t _pad_000298; 226 227 bridgereg_t _pad_0002A0[24]; 228 229 /* Xbridge only */ 230 struct { 231 bridgereg_t upper; /* 0x0003{04,,,F4} */ 232 bridgereg_t __pad1; /* 0x0003{00,,,F0} */ 233 bridgereg_t lower; /* 0x0003{0C,,,FC} */ 234 bridgereg_t __pad2; /* 0x0003{08,,,F8} */ 235 } b_buf_addr_match[16]; 236 237 /* Performance Monitor Registers (even only) */ 238 struct { 239 bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */ 240 bridgereg_t __pad1; /* 0x000400,,,5C0 */ 241 242 bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */ 243 bridgereg_t __pad2; /* 0x000408,,,5C8 */ 244 245 bridgereg_t inflight; /* 0x000414,,,5D4 */ 246 bridgereg_t __pad3; /* 0x000410,,,5D0 */ 247 248 bridgereg_t prefetch; /* 0x00041C,,,5DC */ 249 bridgereg_t __pad4; /* 0x000418,,,5D8 */ 250 251 bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */ 252 bridgereg_t __pad5; /* 0x000420,,,5E0 */ 253 254 bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */ 255 bridgereg_t __pad6; /* 0x000428,,,5E8 */ 256 257 bridgereg_t max_latency; /* 0x000434,,,5F4 */ 258 bridgereg_t __pad7; /* 0x000430,,,5F0 */ 259 260 bridgereg_t clear_all; /* 0x00043C,,,5FC */ 261 bridgereg_t __pad8; /* 0x000438,,,5F8 */ 262 } b_buf_count[8]; 263 264 char _pad_000600[0x010000 - 0x000600]; 265 266 /* 267 * The Xbridge has 1024 internal ATE's and the Bridge has 128. 268 * Make enough room for the Xbridge ATE's and depend on runtime 269 * checks to limit access to bridge ATE's. 270 */ 271 272 /* Internal Address Translation Entry RAM 0x010000-0x011fff */ 273 union { 274 bridge_ate_t wr; /* write-only */ 275 struct { 276 bridgereg_t rd; /* read-only */ 277 bridgereg_t _p_pad; 278 } hi; 279 } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; 280 281#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd 282 283 /* the xbridge read path for internal ates starts at 0x12000. 284 * I don't believe we ever try to read the ates. 285 */ 286 /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */ 287 struct { 288 bridgereg_t rd; 289 bridgereg_t _p_pad; 290 } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; 291 292 char _pad_014000[0x20000 - 0x014000]; 293 294 /* PCI Device Configuration Spaces 0x020000-0x027FFF */ 295 union { /* make all access sizes available. */ 296 uchar_t c[0x1000 / 1]; 297 uint16_t s[0x1000 / 2]; 298 uint32_t l[0x1000 / 4]; 299 uint64_t d[0x1000 / 8]; 300 union { 301 uchar_t c[0x100 / 1]; 302 uint16_t s[0x100 / 2]; 303 uint32_t l[0x100 / 4]; 304 uint64_t d[0x100 / 8]; 305 } f[8]; 306 } b_type0_cfg_dev[8]; /* 0x020000 */ 307 308 /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ 309 union { /* make all access sizes available. */ 310 uchar_t c[0x1000 / 1]; 311 uint16_t s[0x1000 / 2]; 312 uint32_t l[0x1000 / 4]; 313 uint64_t d[0x1000 / 8]; 314 } b_type1_cfg; /* 0x028000-0x029000 */ 315 316 char _pad_029000[0x007000]; /* 0x029000-0x030000 */ 317 318 /* PCI Interrupt Acknowledge Cycle 0x030000 */ 319 union { 320 uchar_t c[8 / 1]; 321 uint16_t s[8 / 2]; 322 uint32_t l[8 / 4]; 323 uint64_t d[8 / 8]; 324 } b_pci_iack; /* 0x030000 */ 325 326 uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ 327 328 /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ 329 bridge_ate_t b_ext_ate_ram[0x10000]; 330 331 /* Reserved 0x100000-0x1FFFFF */ 332 char _pad_100000[0x200000-0x100000]; 333 334 /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ 335 union { /* make all access sizes available. */ 336 uchar_t c[0x100000 / 1]; 337 uint16_t s[0x100000 / 2]; 338 uint32_t l[0x100000 / 4]; 339 uint64_t d[0x100000 / 8]; 340 } b_devio_raw[10]; /* 0x200000 */ 341 342 /* b_devio macro is a bit strange; it reflects the 343 * fact that the Bridge ASIC provides 2M for the 344 * first two DevIO windows and 1M for the other six. 345 */ 346#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] 347 348 /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ 349 union { /* make all access sizes available. */ 350 uchar_t c[0x400000 / 1]; /* read-only */ 351 uint16_t s[0x400000 / 2]; /* read-write */ 352 uint32_t l[0x400000 / 4]; /* read-only */ 353 uint64_t d[0x400000 / 8]; /* read-only */ 354 } b_external_flash; /* 0xC00000 */ 355} bridge_t; 356 357#else 358 359/* 360 * Field formats for Error Command Word and Auxillary Error Command Word 361 * of bridge. 362 */ 363typedef struct bridge_err_cmdword_s { 364 union { 365 uint32_t cmd_word; 366 struct { 367 uint32_t didn:4, /* Destination ID */ 368 sidn:4, /* SOurce ID */ 369 pactyp:4, /* Packet type */ 370 tnum:5, /* Trans Number */ 371 coh:1, /* Coh Transacti */ 372 ds:2, /* Data size */ 373 gbr:1, /* GBR enable */ 374 vbpm:1, /* VBPM message */ 375 error:1, /* Error occurred */ 376 barr:1, /* Barrier op */ 377 rsvd:8; 378 } berr_st; 379 } berr_un; 380} bridge_err_cmdword_t; 381 382typedef volatile struct bridge_s { 383 384 /* Local Registers 0x000000-0x00FFFF */ 385 386 /* standard widget configuration 0x000000-0x000057 */ 387 widget_cfg_t b_widget; /* 0x000000 */ 388 389 /* helper fieldnames for accessing bridge widget */ 390 391#define b_wid_id b_widget.w_id 392#define b_wid_stat b_widget.w_status 393#define b_wid_err_upper b_widget.w_err_upper_addr 394#define b_wid_err_lower b_widget.w_err_lower_addr 395#define b_wid_control b_widget.w_control 396#define b_wid_req_timeout b_widget.w_req_timeout 397#define b_wid_int_upper b_widget.w_intdest_upper_addr 398#define b_wid_int_lower b_widget.w_intdest_lower_addr 399#define b_wid_err_cmdword b_widget.w_err_cmd_word 400#define b_wid_llp b_widget.w_llp_cfg 401#define b_wid_tflush b_widget.w_tflush 402 403 /* bridge-specific widget configuration 0x000058-0x00007F */ 404 bridgereg_t _pad_000058; 405 bridgereg_t b_wid_aux_err; /* 0x00005C */ 406 bridgereg_t _pad_000060; 407 bridgereg_t b_wid_resp_upper; /* 0x000064 */ 408 bridgereg_t _pad_000068; 409 bridgereg_t b_wid_resp_lower; /* 0x00006C */ 410 bridgereg_t _pad_000070; 411 bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ 412 bridgereg_t _pad_000078[2]; 413 414 /* PMU & Map 0x000080-0x00008F */ 415 bridgereg_t _pad_000080; 416 bridgereg_t b_dir_map; /* 0x000084 */ 417 bridgereg_t _pad_000088[2]; 418 419 /* SSRAM 0x000090-0x00009F */ 420 bridgereg_t _pad_000090; 421 bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ 422#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ 423#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */ 424 bridgereg_t _pad_000098[2]; 425 426 /* Arbitration 0x0000A0-0x0000AF */ 427 bridgereg_t _pad_0000A0; 428 bridgereg_t b_arb; /* 0x0000A4 */ 429 bridgereg_t _pad_0000A8[2]; 430 431 /* Number In A Can 0x0000B0-0x0000BF */ 432 bridgereg_t _pad_0000B0; 433 bridgereg_t b_nic; /* 0x0000B4 */ 434 bridgereg_t _pad_0000B8[2]; 435 436 /* PCI/GIO 0x0000C0-0x0000FF */ 437 bridgereg_t _pad_0000C0; 438 bridgereg_t b_bus_timeout; /* 0x0000C4 */ 439#define b_pci_bus_timeout b_bus_timeout 440 441 bridgereg_t _pad_0000C8; 442 bridgereg_t b_pci_cfg; /* 0x0000CC */ 443 bridgereg_t _pad_0000D0; 444 bridgereg_t b_pci_err_upper; /* 0x0000D4 */ 445 bridgereg_t _pad_0000D8; 446 bridgereg_t b_pci_err_lower; /* 0x0000DC */ 447 bridgereg_t _pad_0000E0[8]; 448#define b_gio_err_lower b_pci_err_lower 449#define b_gio_err_upper b_pci_err_upper 450 451 /* Interrupt 0x000100-0x0001FF */ 452 bridgereg_t _pad_000100; 453 bridgereg_t b_int_status; /* 0x000104 */ 454 bridgereg_t _pad_000108; 455 bridgereg_t b_int_enable; /* 0x00010C */ 456 bridgereg_t _pad_000110; 457 bridgereg_t b_int_rst_stat; /* 0x000114 */ 458 bridgereg_t _pad_000118; 459 bridgereg_t b_int_mode; /* 0x00011C */ 460 bridgereg_t _pad_000120; 461 bridgereg_t b_int_device; /* 0x000124 */ 462 bridgereg_t _pad_000128; 463 bridgereg_t b_int_host_err; /* 0x00012C */ 464 465 struct { 466 bridgereg_t __pad; /* 0x0001{30,,,68} */ 467 bridgereg_t addr; /* 0x0001{34,,,6C} */ 468 } b_int_addr[8]; /* 0x000130 */ 469 470 bridgereg_t _pad_000170; 471 bridgereg_t b_err_int_view; /* 0x000174 */ 472 bridgereg_t _pad_000178; 473 bridgereg_t b_mult_int; /* 0x00017c */ 474 475 struct { 476 bridgereg_t __pad; /* 0x0001{80,,,B8} */ 477 bridgereg_t intr; /* 0x0001{84,,,BC} */ 478 } b_force_always[8]; /* 0x000180 */ 479 480 struct { 481 bridgereg_t __pad; /* 0x0001{C0,,,F8} */ 482 bridgereg_t intr; /* 0x0001{C4,,,FC} */ 483 } b_force_pin[8]; /* 0x0001C0 */ 484 485 /* Device 0x000200-0x0003FF */ 486 struct { 487 bridgereg_t __pad; /* 0x0002{00,,,38} */ 488 bridgereg_t reg; /* 0x0002{04,,,3C} */ 489 } b_device[8]; /* 0x000200 */ 490 491 struct { 492 bridgereg_t __pad; /* 0x0002{40,,,78} */ 493 bridgereg_t reg; /* 0x0002{44,,,7C} */ 494 } b_wr_req_buf[8]; /* 0x000240 */ 495 496 struct { 497 bridgereg_t __pad; /* 0x0002{80,,,88} */ 498 bridgereg_t reg; /* 0x0002{84,,,8C} */ 499 } b_rrb_map[2]; /* 0x000280 */ 500#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ 501#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ 502 503 bridgereg_t _pad_000290; 504 bridgereg_t b_resp_status; /* 0x000294 */ 505 bridgereg_t _pad_000298; 506 bridgereg_t b_resp_clear; /* 0x00029C */ 507 508 bridgereg_t _pad_0002A0[24]; 509 510 /* Xbridge only */ 511 struct { 512 bridgereg_t __pad1; /* 0x0003{00,,,F0} */ 513 bridgereg_t upper; /* 0x0003{04,,,F4} */ 514 bridgereg_t __pad2; /* 0x0003{08,,,F8} */ 515 bridgereg_t lower; /* 0x0003{0C,,,FC} */ 516 } b_buf_addr_match[16]; 517 518 /* Performance Monitor Registers (even only) */ 519 struct { 520 bridgereg_t __pad1; /* 0x000400,,,5C0 */ 521 bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */ 522 bridgereg_t __pad2; /* 0x000408,,,5C8 */ 523 bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */ 524 bridgereg_t __pad3; /* 0x000410,,,5D0 */ 525 bridgereg_t inflight; /* 0x000414,,,5D4 */ 526 bridgereg_t __pad4; /* 0x000418,,,5D8 */ 527 bridgereg_t prefetch; /* 0x00041C,,,5DC */ 528 bridgereg_t __pad5; /* 0x000420,,,5E0 */ 529 bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */ 530 bridgereg_t __pad6; /* 0x000428,,,5E8 */ 531 bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */ 532 bridgereg_t __pad7; /* 0x000430,,,5F0 */ 533 bridgereg_t max_latency; /* 0x000434,,,5F4 */ 534 bridgereg_t __pad8; /* 0x000438,,,5F8 */ 535 bridgereg_t clear_all; /* 0x00043C,,,5FC */ 536 } b_buf_count[8]; 537 538 char _pad_000600[0x010000 - 0x000600]; 539 540 /* 541 * The Xbridge has 1024 internal ATE's and the Bridge has 128. 542 * Make enough room for the Xbridge ATE's and depend on runtime 543 * checks to limit access to bridge ATE's. 544 */ 545 546 /* Internal Address Translation Entry RAM 0x010000-0x011fff */ 547 union { 548 bridge_ate_t wr; /* write-only */ 549 struct { 550 bridgereg_t _p_pad; 551 bridgereg_t rd; /* read-only */ 552 } hi; 553 } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; 554 555#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd 556 557 /* the xbridge read path for internal ates starts at 0x12000. 558 * I don't believe we ever try to read the ates. 559 */ 560 /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */ 561 struct { 562 bridgereg_t _p_pad; 563 bridgereg_t rd; /* read-only */ 564 } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; 565 566 char _pad_014000[0x20000 - 0x014000]; 567 568 /* PCI Device Configuration Spaces 0x020000-0x027FFF */ 569 union { /* make all access sizes available. */ 570 uchar_t c[0x1000 / 1]; 571 uint16_t s[0x1000 / 2]; 572 uint32_t l[0x1000 / 4]; 573 uint64_t d[0x1000 / 8]; 574 union { 575 uchar_t c[0x100 / 1]; 576 uint16_t s[0x100 / 2]; 577 uint32_t l[0x100 / 4]; 578 uint64_t d[0x100 / 8]; 579 } f[8]; 580 } b_type0_cfg_dev[8]; /* 0x020000 */ 581 582 583 /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ 584 union { /* make all access sizes available. */ 585 uchar_t c[0x1000 / 1]; 586 uint16_t s[0x1000 / 2]; 587 uint32_t l[0x1000 / 4]; 588 uint64_t d[0x1000 / 8]; 589 } b_type1_cfg; /* 0x028000-0x029000 */ 590 591 char _pad_029000[0x007000]; /* 0x029000-0x030000 */ 592 593 /* PCI Interrupt Acknowledge Cycle 0x030000 */ 594 union { 595 uchar_t c[8 / 1]; 596 uint16_t s[8 / 2]; 597 uint32_t l[8 / 4]; 598 uint64_t d[8 / 8]; 599 } b_pci_iack; /* 0x030000 */ 600 601 uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ 602 603 /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ 604 bridge_ate_t b_ext_ate_ram[0x10000]; 605 606 /* Reserved 0x100000-0x1FFFFF */ 607 char _pad_100000[0x200000-0x100000]; 608 609 /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ 610 union { /* make all access sizes available. */ 611 uchar_t c[0x100000 / 1]; 612 uint16_t s[0x100000 / 2]; 613 uint32_t l[0x100000 / 4]; 614 uint64_t d[0x100000 / 8]; 615 } b_devio_raw[10]; /* 0x200000 */ 616 617 /* b_devio macro is a bit strange; it reflects the 618 * fact that the Bridge ASIC provides 2M for the 619 * first two DevIO windows and 1M for the other six. 620 */ 621#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] 622 623 /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ 624 union { /* make all access sizes available. */ 625 uchar_t c[0x400000 / 1]; /* read-only */ 626 uint16_t s[0x400000 / 2]; /* read-write */ 627 uint32_t l[0x400000 / 4]; /* read-only */ 628 uint64_t d[0x400000 / 8]; /* read-only */ 629 } b_external_flash; /* 0xC00000 */ 630} bridge_t; 631 632#endif 633 634 635 636 637 638 639#define berr_field berr_un.berr_st 640#endif /* __ASSEMBLY__ */ 641 642/* 643 * The values of these macros can and should be crosschecked 644 * regularly against the offsets of the like-named fields 645 * within the "bridge_t" structure above. 646 */ 647 648/* Byte offset macros for Bridge internal registers */ 649 650#define BRIDGE_WID_ID WIDGET_ID 651#define BRIDGE_WID_STAT WIDGET_STATUS 652#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR 653#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR 654#define BRIDGE_WID_CONTROL WIDGET_CONTROL 655#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT 656#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR 657#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR 658#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD 659#define BRIDGE_WID_LLP WIDGET_LLP_CFG 660#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH 661 662#define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */ 663#define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */ 664#define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */ 665#define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */ 666 667#define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */ 668 669/* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */ 670#define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */ 671#define BRIDGE_MAP_FAULT 0x000094 /* Map Fault */ 672 673#define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */ 674 675#define BRIDGE_NIC 0x0000B4 /* Number In A Can */ 676 677#define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */ 678#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT 679#define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */ 680#define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */ 681#define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */ 682 683#define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */ 684#define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */ 685#define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */ 686#define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */ 687#define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */ 688#define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */ 689 690#define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */ 691#define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */ 692#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF) 693 694#define BRIDGE_INT_VIEW 0x000174 /* Interrupt view */ 695#define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occurred */ 696 697#define BRIDGE_FORCE_ALWAYS0 0x000184 /* Force an interrupt (always)*/ 698#define BRIDGE_FORCE_ALWAYS_OFF 0x000008 /* Force Always offset */ 699#define BRIDGE_FORCE_ALWAYS(x) (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF) 700 701#define BRIDGE_FORCE_PIN0 0x0001c4 /* Force an interrupt */ 702#define BRIDGE_FORCE_PIN_OFF 0x000008 /* Force Pin offset */ 703#define BRIDGE_FORCE_PIN(x) (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF) 704 705#define BRIDGE_DEVICE0 0x000204 /* Device 0 */ 706#define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */ 707#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF) 708 709#define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */ 710#define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */ 711#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF) 712 713#define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */ 714#define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */ 715 716#define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */ 717#define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */ 718 719#define BRIDGE_BUF_ADDR_UPPER0 0x000304 720#define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010 /* PCI Buffer Upper Offset */ 721#define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF) 722 723#define BRIDGE_BUF_ADDR_LOWER0 0x00030c 724#define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010 /* PCI Buffer Upper Offset */ 725#define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF) 726 727/* 728 * Performance Monitor Registers. 729 * 730 * The Performance registers are those registers which are associated with 731 * monitoring the performance of PCI generated reads to the host environ 732 * ment. Because of the size of the register file only the even registers 733 * were instrumented. 734 */ 735 736#define BRIDGE_BUF_OFF 0x40 737#define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF)) 738 739/* 740 * Buffer (x) Flush Count with Data Touch Register. 741 * 742 * This counter is incremented each time the corresponding response buffer 743 * is flushed after at least a single data element in the buffer is used. 744 * A word write to this address clears the count. 745 */ 746 747#define BRIDGE_BUF_0_FLUSH_TOUCH 0x000404 748#define BRIDGE_BUF_2_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1) 749#define BRIDGE_BUF_4_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2) 750#define BRIDGE_BUF_6_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3) 751#define BRIDGE_BUF_8_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4) 752#define BRIDGE_BUF_10_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5) 753#define BRIDGE_BUF_12_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6) 754#define BRIDGE_BUF_14_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7) 755 756/* 757 * Buffer (x) Flush Count w/o Data Touch Register 758 * 759 * This counter is incremented each time the corresponding response buffer 760 * is flushed without any data element in the buffer being used. A word 761 * write to this address clears the count. 762 */ 763 764 765#define BRIDGE_BUF_0_FLUSH_NOTOUCH 0x00040c 766#define BRIDGE_BUF_2_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1) 767#define BRIDGE_BUF_4_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2) 768#define BRIDGE_BUF_6_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3) 769#define BRIDGE_BUF_8_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4) 770#define BRIDGE_BUF_10_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5) 771#define BRIDGE_BUF_12_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6) 772#define BRIDGE_BUF_14_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7) 773 774/* 775 * Buffer (x) Request in Flight Count Register 776 * 777 * This counter is incremented on each bus clock while the request is in 778 * flight. A word write to this address clears the count. 779 */ 780 781#define BRIDGE_BUF_0_INFLIGHT 0x000414 782#define BRIDGE_BUF_2_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1) 783#define BRIDGE_BUF_4_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2) 784#define BRIDGE_BUF_6_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3) 785#define BRIDGE_BUF_8_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4) 786#define BRIDGE_BUF_10_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5) 787#define BRIDGE_BUF_12_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6) 788#define BRIDGE_BUF_14_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7) 789 790/* 791 * Buffer (x) Prefetch Request Count Register 792 * 793 * This counter is incremented each time the request using this buffer was 794 * generated from the prefetcher. A word write to this address clears the 795 * count. 796 */ 797 798#define BRIDGE_BUF_0_PREFETCH 0x00041C 799#define BRIDGE_BUF_2_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1) 800#define BRIDGE_BUF_4_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2) 801#define BRIDGE_BUF_6_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3) 802#define BRIDGE_BUF_8_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4) 803#define BRIDGE_BUF_10_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5) 804#define BRIDGE_BUF_12_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6) 805#define BRIDGE_BUF_14_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7) 806 807/* 808 * Buffer (x) Total PCI Retry Count Register 809 * 810 * This counter is incremented each time a PCI bus retry occurs and the ad 811 * dress matches the tag for the selected buffer. The buffer must also has 812 * this request in-flight. A word write to this address clears the count. 813 */ 814 815#define BRIDGE_BUF_0_PCI_RETRY 0x000424 816#define BRIDGE_BUF_2_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1) 817#define BRIDGE_BUF_4_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2) 818#define BRIDGE_BUF_6_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3) 819#define BRIDGE_BUF_8_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4) 820#define BRIDGE_BUF_10_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5) 821#define BRIDGE_BUF_12_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6) 822#define BRIDGE_BUF_14_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7) 823 824/* 825 * Buffer (x) Max PCI Retry Count Register 826 * 827 * This counter is contains the maximum retry count for a single request 828 * which was in-flight for this buffer. A word write to this address 829 * clears the count. 830 */ 831 832#define BRIDGE_BUF_0_MAX_PCI_RETRY 0x00042C 833#define BRIDGE_BUF_2_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1) 834#define BRIDGE_BUF_4_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2) 835#define BRIDGE_BUF_6_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3) 836#define BRIDGE_BUF_8_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4) 837#define BRIDGE_BUF_10_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5) 838#define BRIDGE_BUF_12_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6) 839#define BRIDGE_BUF_14_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7) 840 841/* 842 * Buffer (x) Max Latency Count Register 843 * 844 * This counter is contains the maximum count (in bus clocks) for a single 845 * request which was in-flight for this buffer. A word write to this 846 * address clears the count. 847 */ 848 849#define BRIDGE_BUF_0_MAX_LATENCY 0x000434 850#define BRIDGE_BUF_2_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1) 851#define BRIDGE_BUF_4_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2) 852#define BRIDGE_BUF_6_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3) 853#define BRIDGE_BUF_8_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4) 854#define BRIDGE_BUF_10_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5) 855#define BRIDGE_BUF_12_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6) 856#define BRIDGE_BUF_14_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7) 857 858/* 859 * Buffer (x) Clear All Register 860 * 861 * Any access to this register clears all the count values for the (x) 862 * registers. 863 */ 864 865#define BRIDGE_BUF_0_CLEAR_ALL 0x00043C 866#define BRIDGE_BUF_2_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1) 867#define BRIDGE_BUF_4_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2) 868#define BRIDGE_BUF_6_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3) 869#define BRIDGE_BUF_8_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4) 870#define BRIDGE_BUF_10_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5) 871#define BRIDGE_BUF_12_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6) 872#define BRIDGE_BUF_14_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7) 873 874/* end of Performance Monitor Registers */ 875 876/* Byte offset macros for Bridge I/O space */ 877 878#define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */ 879 880#define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */ 881#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */ 882#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ 883#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ 884 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) 885#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ 886 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ 887 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) 888 889#define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */ 890 891#define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */ 892#define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */ 893 894/* Byte offset macros for Bridge device IO spaces */ 895 896#define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */ 897#define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */ 898#define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */ 899#define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */ 900#define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */ 901 902#define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */ 903#define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */ 904 905#ifndef __ASSEMBLY__ 906 907#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) 908#endif /* __ASSEMBLY__ */ 909 910#define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ 911 912/* ======================================================================== 913 * Bridge register bit field definitions 914 */ 915 916/* Widget part number of bridge */ 917#define BRIDGE_WIDGET_PART_NUM 0xc002 918#define XBRIDGE_WIDGET_PART_NUM 0xd002 919 920/* Manufacturer of bridge */ 921#define BRIDGE_WIDGET_MFGR_NUM 0x036 922#define XBRIDGE_WIDGET_MFGR_NUM 0x024 923 924/* Revision numbers for known [X]Bridge revisions */ 925#define BRIDGE_REV_A 0x1 926#define BRIDGE_REV_B 0x2 927#define BRIDGE_REV_C 0x3 928#define BRIDGE_REV_D 0x4 929#define XBRIDGE_REV_A 0x1 930#define XBRIDGE_REV_B 0x2 931 932/* Part + Rev numbers allows distinction and acscending sequence */ 933#define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A) 934#define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B) 935#define BRIDGE_PART_REV_C (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C) 936#define BRIDGE_PART_REV_D (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D) 937#define XBRIDGE_PART_REV_A (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A) 938#define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B) 939 940/* Bridge widget status register bits definition */ 941 942#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24) 943#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16) 944#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6) 945#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5) 946#define BRIDGE_STAT_PENDING (0x1F << 0) 947 948/* Bridge widget control register bits definition */ 949#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) 950#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30) 951#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29) 952#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28) 953#define BRIDGE_CTRL_RST(n) ((n) << 24) 954#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF)) 955#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x))) 956#define BRIDGE_CTRL_IO_SWAP (0x1 << 23) 957#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22) 958#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21) 959#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20) 960#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19) 961#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17) 962#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3)) 963#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3)) 964#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2)) 965#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1)) 966#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0)) 967#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16) 968#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12) 969#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf)) 970#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) 971#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) 972#define BRIDGE_CTRL_SYS_END (0x1 << 9) 973#define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4) 974#define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3)) 975#define BRIDGE_CTRL_BUS_SPEED_33 0x00 976#define BRIDGE_CTRL_BUS_SPEED_66 0x10 977#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4) 978#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f)) 979#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0) 980#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf)) 981 982/* Bridge Response buffer Error Upper Register bit fields definition */ 983#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20) 984#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) 985#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16) 986#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) 987#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF) 988 989#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \ 990 (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \ 991 BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) 992 993#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \ 994 (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \ 995 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) 996 997/* Bridge direct mapping register bits definition */ 998#define BRIDGE_DIRMAP_W_ID_SHFT 20 999#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT) 1000#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18) 1001#define BRIDGE_DIRMAP_ADD512 (0x1 << 17) 1002#define BRIDGE_DIRMAP_OFF (0x1ffff << 0) 1003#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */ 1004 1005/* Bridge Arbitration register bits definition */ 1006#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16) 1007#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3) 1008#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8) 1009#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff) 1010#define BRIDGE_ARB_FREEZE_GNT (1 << 6) 1011#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5) 1012#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4) 1013#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3) 1014#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2) 1015#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1) 1016#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0) 1017 1018/* Bridge Bus time-out register bits definition */ 1019#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16) 1020#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f) 1021#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12) 1022#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0) 1023#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) 1024 1025/* Bridge interrupt status register bits definition */ 1026#define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */ 1027#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */ 1028#define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */ 1029#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29) 1030#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28) 1031#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27) 1032#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26) 1033#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25) 1034#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24) 1035#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23) 1036#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22) 1037#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21) 1038#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20) 1039#define BRIDGE_ISR_LLP_RCTY (0x1 << 19) 1040#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18) 1041#define BRIDGE_ISR_LLP_TCTY (0x1 << 17) 1042#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16) 1043#define BRIDGE_ISR_PCI_ABORT (0x1 << 15) 1044#define BRIDGE_ISR_PCI_PARITY (0x1 << 14) 1045#define BRIDGE_ISR_PCI_SERR (0x1 << 13) 1046#define BRIDGE_ISR_PCI_PERR (0x1 << 12) 1047#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11) 1048#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT 1049#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10) 1050#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9) 1051#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8) 1052#define BRIDGE_ISR_INT_MSK (0xff << 0) 1053#define BRIDGE_ISR_INT(x) (0x1 << (x)) 1054 1055#define BRIDGE_ISR_LINK_ERROR \ 1056 (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \ 1057 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \ 1058 BRIDGE_ISR_LLP_TCTY) 1059 1060#define BRIDGE_ISR_PCIBUS_PIOERR \ 1061 (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT) 1062 1063#define BRIDGE_ISR_PCIBUS_ERROR \ 1064 (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \ 1065 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \ 1066 BRIDGE_ISR_PCI_PARITY) 1067 1068#define BRIDGE_ISR_XTALK_ERROR \ 1069 (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\ 1070 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \ 1071 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \ 1072 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \ 1073 BRIDGE_ISR_UNEXP_RESP) 1074 1075#define BRIDGE_ISR_ERRORS \ 1076 (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ 1077 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ 1078 BRIDGE_ISR_PMU_ESIZE_FAULT) 1079 1080/* 1081 * List of Errors which are fatal and kill the sytem 1082 */ 1083#define BRIDGE_ISR_ERROR_FATAL \ 1084 ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\ 1085 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY ) 1086 1087#define BRIDGE_ISR_ERROR_DUMP \ 1088 (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \ 1089 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR) 1090 1091/* Bridge interrupt enable register bits definition */ 1092#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP 1093#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT 1094#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT 1095#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT 1096#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR 1097#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR 1098#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR 1099#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP 1100#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW 1101#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR 1102#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR 1103#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY 1104#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY 1105#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY 1106#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR 1107#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT 1108#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY 1109#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR 1110#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR 1111#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT 1112#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT 1113#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT 1114#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT 1115#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR 1116#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK 1117#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x) 1118 1119/* Bridge interrupt reset register bits definition */ 1120#define BRIDGE_IRR_MULTI_CLR (0x1 << 6) 1121#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5) 1122#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4) 1123#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3) 1124#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2) 1125#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1) 1126#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0) 1127#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0) 1128#define BRIDGE_IRR_ALL_CLR 0x7f 1129 1130#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \ 1131 BRIDGE_ISR_XREQ_FIFO_OFLOW) 1132#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \ 1133 BRIDGE_ISR_RESP_XTLK_ERR | \ 1134 BRIDGE_ISR_XREAD_REQ_TIMEOUT) 1135#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \ 1136 BRIDGE_ISR_BAD_XREQ_PKT | \ 1137 BRIDGE_ISR_REQ_XTLK_ERR | \ 1138 BRIDGE_ISR_INVLD_ADDR) 1139#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \ 1140 BRIDGE_ISR_LLP_REC_CBERR | \ 1141 BRIDGE_ISR_LLP_RCTY | \ 1142 BRIDGE_ISR_LLP_TX_RETRY | \ 1143 BRIDGE_ISR_LLP_TCTY) 1144#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \ 1145 BRIDGE_ISR_PMU_ESIZE_FAULT) 1146#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \ 1147 BRIDGE_ISR_PCI_PARITY | \ 1148 BRIDGE_ISR_PCI_SERR | \ 1149 BRIDGE_ISR_PCI_PERR | \ 1150 BRIDGE_ISR_PCI_MST_TIMEOUT | \ 1151 BRIDGE_ISR_PCI_RETRY_CNT) 1152 1153#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \ 1154 BRIDGE_ISR_GIO_MST_TIMEOUT) 1155 1156/* Bridge INT_DEV register bits definition */ 1157#define BRIDGE_INT_DEV_SHFT(n) ((n)*3) 1158#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n)) 1159#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line)) 1160 1161/* Bridge interrupt(x) register bits definition */ 1162#define BRIDGE_INT_ADDR_HOST 0x0003FF00 1163#define BRIDGE_INT_ADDR_FLD 0x000000FF 1164 1165#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000 1166#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000 1167#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff 1168 1169#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff 1170 1171#ifdef SN0 1172/* 1173 * The NASID should be shifted by this amount and stored into the 1174 * interrupt(x) register. 1175 */ 1176#define BRIDGE_INT_ADDR_NASID_SHFT 8 1177 1178/* 1179 * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to 1180 * memory. 1181 */ 1182#define BRIDGE_INT_ADDR_DEST_IO (1 << 17) 1183#define BRIDGE_INT_ADDR_DEST_MEM 0 1184#define BRIDGE_INT_ADDR_MASK (1 << 17) 1185#endif 1186 1187/* Bridge device(x) register bits definition */ 1188#define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28) 1189#define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27) 1190#define BRIDGE_DEV_FORCE_PCI_PAR (1ull << 26) 1191#define BRIDGE_DEV_VIRTUAL_EN (1ull << 25) 1192#define BRIDGE_DEV_PMU_WRGA_EN (1ull << 24) 1193#define BRIDGE_DEV_DIR_WRGA_EN (1ull << 23) 1194#define BRIDGE_DEV_DEV_SIZE (1ull << 22) 1195#define BRIDGE_DEV_RT (1ull << 21) 1196#define BRIDGE_DEV_SWAP_PMU (1ull << 20) 1197#define BRIDGE_DEV_SWAP_DIR (1ull << 19) 1198#define BRIDGE_DEV_PREF (1ull << 18) 1199#define BRIDGE_DEV_PRECISE (1ull << 17) 1200#define BRIDGE_DEV_COH (1ull << 16) 1201#define BRIDGE_DEV_BARRIER (1ull << 15) 1202#define BRIDGE_DEV_GBR (1ull << 14) 1203#define BRIDGE_DEV_DEV_SWAP (1ull << 13) 1204#define BRIDGE_DEV_DEV_IO_MEM (1ull << 12) 1205#define BRIDGE_DEV_OFF_MASK 0x00000fff 1206#define BRIDGE_DEV_OFF_ADDR_SHFT 20 1207 1208#define XBRIDGE_DEV_PMU_BITS BRIDGE_DEV_PMU_WRGA_EN 1209#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \ 1210 BRIDGE_DEV_SWAP_PMU) 1211#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ 1212 BRIDGE_DEV_SWAP_DIR | \ 1213 BRIDGE_DEV_PREF | \ 1214 BRIDGE_DEV_PRECISE | \ 1215 BRIDGE_DEV_COH | \ 1216 BRIDGE_DEV_BARRIER) 1217#define XBRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ 1218 BRIDGE_DEV_COH | \ 1219 BRIDGE_DEV_BARRIER) 1220#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ 1221 BRIDGE_DEV_SWAP_DIR | \ 1222 BRIDGE_DEV_COH | \ 1223 BRIDGE_DEV_BARRIER) 1224 1225/* Bridge Error Upper register bit field definition */ 1226#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */ 1227#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */ 1228#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16) 1229#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT) 1230#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7) 1231#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF) 1232 1233/* Bridge interrupt mode register bits definition */ 1234#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x)) 1235 1236/* this should be written to the xbow's link_control(x) register */ 1237#define BRIDGE_CREDIT 3 1238 1239/* RRB assignment register */ 1240#define BRIDGE_RRB_EN 0x8 /* after shifting down */ 1241#define BRIDGE_RRB_DEV 0x7 /* after shifting down */ 1242#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */ 1243#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */ 1244 1245/* RRB status register */ 1246#define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) 1247#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r)) 1248 1249/* RRB clear register */ 1250#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) 1251 1252/* xbox system controller declarations */ 1253#define XBOX_BRIDGE_WID 8 1254#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ 1255#define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */ 1256#define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */ 1257 1258/* ======================================================================== 1259 */ 1260/* 1261 * Macros for Xtalk to Bridge bus (PCI/GIO) PIO 1262 * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings 1263 */ 1264/* XTALK addresses that map into Bridge Bus addr space */ 1265#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L 1266#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL 1267#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L 1268#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL 1269#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L 1270#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL 1271 1272/* Ranges of PCI bus space that can be accessed via PIO from xtalk */ 1273#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */ 1274#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff 1275#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */ 1276#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff 1277 1278/* XTALK addresses that map into PCI addresses */ 1279#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE 1280#define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT 1281#define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE 1282#define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT 1283#define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE 1284#define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 1285 1286/* 1287 * Macros for Bridge bus (PCI/GIO) to Xtalk DMA 1288 */ 1289/* Bridge Bus DMA addresses */ 1290#define BRIDGE_LOCAL_BASE 0 1291#define BRIDGE_DMA_MAPPED_BASE 0x40000000 1292#define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */ 1293#define BRIDGE_DMA_DIRECT_BASE 0x80000000 1294#define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */ 1295 1296#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE 1297 1298/* PCI addresses of regions decoded by Bridge for DMA */ 1299#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE 1300#define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE 1301 1302#ifndef __ASSEMBLY__ 1303 1304#define IS_PCI32_LOCAL(x) ((uint64_t)(x) < PCI32_MAPPED_BASE) 1305#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ 1306 (uint64_t)(x) >= PCI32_MAPPED_BASE) 1307#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) 1308#define IS_PCI64(x) ((uint64_t)(x) >= PCI64_BASE) 1309#endif /* __ASSEMBLY__ */ 1310 1311/* 1312 * The GIO address space. 1313 */ 1314/* Xtalk to GIO PIO */ 1315#define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE 1316#define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT 1317 1318#define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE 1319 1320/* GIO addresses of regions decoded by Bridge for DMA */ 1321#define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE 1322#define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE 1323 1324#ifndef __ASSEMBLY__ 1325 1326#define IS_GIO_LOCAL(x) ((uint64_t)(x) < GIO_MAPPED_BASE) 1327#define IS_GIO_MAPPED(x) ((uint64_t)(x) < GIO_DIRECT_BASE && \ 1328 (uint64_t)(x) >= GIO_MAPPED_BASE) 1329#define IS_GIO_DIRECT(x) ((uint64_t)(x) >= GIO_MAPPED_BASE) 1330#endif /* __ASSEMBLY__ */ 1331 1332/* PCI to xtalk mapping */ 1333 1334/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine 1335 * which xtalk address is accessed 1336 */ 1337#define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE 1338#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \ 1339 ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \ 1340 ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE) 1341 1342/* 64-bit address attribute masks */ 1343#define PCI64_ATTR_TARG_MASK 0xf000000000000000 1344#define PCI64_ATTR_TARG_SHFT 60 1345#define PCI64_ATTR_PREF (1ull << 59) 1346#define PCI64_ATTR_PREC (1ull << 58) 1347#define PCI64_ATTR_VIRTUAL (1ull << 57) 1348#define PCI64_ATTR_BAR (1ull << 56) 1349#define PCI64_ATTR_SWAP (1ull << 55) 1350#define PCI64_ATTR_RMF_MASK 0x00ff000000000000 1351#define PCI64_ATTR_RMF_SHFT 48 1352 1353#ifndef __ASSEMBLY__ 1354/* Address translation entry for mapped pci32 accesses */ 1355typedef union ate_u { 1356 uint64_t ent; 1357 struct xb_ate_s { /* xbridge */ 1358 uint64_t :16; 1359 uint64_t addr:36; 1360 uint64_t targ:4; 1361 uint64_t reserved:2; 1362 uint64_t swap:1; 1363 uint64_t barrier:1; 1364 uint64_t prefetch:1; 1365 uint64_t precise:1; 1366 uint64_t coherent:1; 1367 uint64_t valid:1; 1368 } xb_field; 1369 struct ate_s { /* bridge */ 1370 uint64_t rmf:16; 1371 uint64_t addr:36; 1372 uint64_t targ:4; 1373 uint64_t reserved:3; 1374 uint64_t barrier:1; 1375 uint64_t prefetch:1; 1376 uint64_t precise:1; 1377 uint64_t coherent:1; 1378 uint64_t valid:1; 1379 } field; 1380} ate_t; 1381#endif /* __ASSEMBLY__ */ 1382 1383#define ATE_V (1 << 0) 1384#define ATE_CO (1 << 1) 1385#define ATE_PREC (1 << 2) 1386#define ATE_PREF (1 << 3) 1387#define ATE_BAR (1 << 4) 1388#define ATE_SWAP (1 << 5) 1389 1390#define ATE_PFNSHIFT 12 1391#define ATE_TIDSHIFT 8 1392#define ATE_RMFSHIFT 48 1393 1394#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \ 1395 ((xid)<<ATE_TIDSHIFT) | \ 1396 (attr) 1397 1398/* 1399 * for xbridge, bit 29 of the pci address is the swap bit */ 1400#define ATE_SWAPSHIFT 29 1401#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) 1402#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) 1403 1404#define is_xbridge(bridge) \ 1405 (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM) 1406 1407#ifndef __ASSEMBLY__ 1408 1409/* ======================================================================== 1410 */ 1411 1412#ifdef MACROFIELD_LINE 1413/* 1414 * This table forms a relation between the byte offset macros normally 1415 * used for ASM coding and the calculated byte offsets of the fields 1416 * in the C structure. 1417 * 1418 * See bridge_check.c and bridge_html.c for further details. 1419 */ 1420#ifndef MACROFIELD_LINE_BITFIELD 1421#define MACROFIELD_LINE_BITFIELD(m) /* ignored */ 1422#endif 1423 1424struct macrofield_s bridge_macrofield[] = 1425{ 1426 1427 MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id) 1428 MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM) 1429 MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM) 1430 MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM) 1431 MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat) 1432 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT) 1433 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT) 1434 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT) 1435 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N) 1436 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING) 1437 MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper) 1438 MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower) 1439 MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control) 1440 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN) 1441 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50) 1442 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40) 1443 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33) 1444 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK) 1445 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP) 1446 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP) 1447 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE) 1448 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD) 1449 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN) 1450 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK) 1451 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT) 1452 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK) 1453 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT) 1454 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT) 1455 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END) 1456 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK) 1457 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK) 1458 MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout) 1459 MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper) 1460 MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR) 1461 MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID) 1462 MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR) 1463 MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower) 1464 MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword) 1465 MACROFIELD_LINE_BITFIELD(WIDGET_DIDN) 1466 MACROFIELD_LINE_BITFIELD(WIDGET_SIDN) 1467 MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP) 1468 MACROFIELD_LINE_BITFIELD(WIDGET_TNUM) 1469 MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT) 1470 MACROFIELD_LINE_BITFIELD(WIDGET_DS) 1471 MACROFIELD_LINE_BITFIELD(WIDGET_GBR) 1472 MACROFIELD_LINE_BITFIELD(WIDGET_VBPM) 1473 MACROFIELD_LINE_BITFIELD(WIDGET_ERROR) 1474 MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER) 1475 MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp) 1476 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY) 1477 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT) 1478 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST) 1479 MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush) 1480 MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err) 1481 MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper) 1482 MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower) 1483 MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl) 1484 MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map) 1485 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID) 1486 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64) 1487 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512) 1488 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF) 1489 MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr) 1490 MACROFIELD_LINE(BRIDGE_ARB, b_arb) 1491 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK) 1492 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK) 1493 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT) 1494 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2) 1495 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B1) 1496 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B0) 1497 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B2) 1498 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B1) 1499 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B0) 1500 MACROFIELD_LINE(BRIDGE_NIC, b_nic) 1501 MACROFIELD_LINE(BRIDGE_PCI_BUS_TIMEOUT, b_pci_bus_timeout) 1502 MACROFIELD_LINE(BRIDGE_PCI_CFG, b_pci_cfg) 1503 MACROFIELD_LINE(BRIDGE_PCI_ERR_UPPER, b_pci_err_upper) 1504 MACROFIELD_LINE(BRIDGE_PCI_ERR_LOWER, b_pci_err_lower) 1505 MACROFIELD_LINE(BRIDGE_INT_STATUS, b_int_status) 1506 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_MULTI_ERR) 1507 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PMU_ESIZE_FAULT) 1508 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNEXP_RESP) 1509 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XRESP_PKT) 1510 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XREQ_PKT) 1511 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_RESP_XTLK_ERR) 1512 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_REQ_XTLK_ERR) 1513 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INVLD_ADDR) 1514 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNSUPPORTED_XOP) 1515 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREQ_FIFO_OFLOW) 1516 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_SNERR) 1517 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_CBERR) 1518 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_RCTY) 1519 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TX_RETRY) 1520 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TCTY) 1521 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_SSRAM_PERR) 1522 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_ABORT) 1523 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PARITY) 1524 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_SERR) 1525 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PERR) 1526 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_MST_TIMEOUT) 1527 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_RETRY_CNT) 1528 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREAD_REQ_TIMEOUT) 1529 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_GIO_B_ENBL_ERR) 1530 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INT_MSK) 1531 MACROFIELD_LINE(BRIDGE_INT_ENABLE, b_int_enable) 1532 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNEXP_RESP) 1533 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PMU_ESIZE_FAULT) 1534 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XRESP_PKT) 1535 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XREQ_PKT) 1536 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_RESP_XTLK_ERR) 1537 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_REQ_XTLK_ERR) 1538 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INVLD_ADDR) 1539 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNSUPPORTED_XOP) 1540 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREQ_FIFO_OFLOW) 1541 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_SNERR) 1542 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_CBERR) 1543 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_RCTY) 1544 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TX_RETRY) 1545 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TCTY) 1546 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_SSRAM_PERR) 1547 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_ABORT) 1548 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PARITY) 1549 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_SERR) 1550 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PERR) 1551 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_MST_TIMEOUT) 1552 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_RETRY_CNT) 1553 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREAD_REQ_TIMEOUT) 1554 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_GIO_B_ENBL_ERR) 1555 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INT_MSK) 1556 MACROFIELD_LINE(BRIDGE_INT_RST_STAT, b_int_rst_stat) 1557 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_ALL_CLR) 1558 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_MULTI_CLR) 1559 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_CRP_GRP_CLR) 1560 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_RESP_BUF_GRP_CLR) 1561 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_REQ_DSP_GRP_CLR) 1562 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_LLP_GRP_CLR) 1563 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_SSRAM_GRP_CLR) 1564 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_PCI_GRP_CLR) 1565 MACROFIELD_LINE(BRIDGE_INT_MODE, b_int_mode) 1566 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(7)) 1567 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(6)) 1568 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(5)) 1569 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(4)) 1570 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(3)) 1571 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(2)) 1572 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(1)) 1573 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(0)) 1574 MACROFIELD_LINE(BRIDGE_INT_DEVICE, b_int_device) 1575 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(7)) 1576 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(6)) 1577 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(5)) 1578 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(4)) 1579 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(3)) 1580 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(2)) 1581 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(1)) 1582 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(0)) 1583 MACROFIELD_LINE(BRIDGE_INT_HOST_ERR, b_int_host_err) 1584 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_HOST) 1585 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_FLD) 1586 MACROFIELD_LINE(BRIDGE_INT_ADDR0, b_int_addr[0].addr) 1587 MACROFIELD_LINE(BRIDGE_INT_ADDR(0), b_int_addr[0].addr) 1588 MACROFIELD_LINE(BRIDGE_INT_ADDR(1), b_int_addr[1].addr) 1589 MACROFIELD_LINE(BRIDGE_INT_ADDR(2), b_int_addr[2].addr) 1590 MACROFIELD_LINE(BRIDGE_INT_ADDR(3), b_int_addr[3].addr) 1591 MACROFIELD_LINE(BRIDGE_INT_ADDR(4), b_int_addr[4].addr) 1592 MACROFIELD_LINE(BRIDGE_INT_ADDR(5), b_int_addr[5].addr) 1593 MACROFIELD_LINE(BRIDGE_INT_ADDR(6), b_int_addr[6].addr) 1594 MACROFIELD_LINE(BRIDGE_INT_ADDR(7), b_int_addr[7].addr) 1595 MACROFIELD_LINE(BRIDGE_DEVICE0, b_device[0].reg) 1596 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_ERR_LOCK_EN) 1597 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PAGE_CHK_DIS) 1598 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_FORCE_PCI_PAR) 1599 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_VIRTUAL_EN) 1600 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PMU_WRGA_EN) 1601 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DIR_WRGA_EN) 1602 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SIZE) 1603 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_RT) 1604 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_PMU) 1605 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_DIR) 1606 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PREF) 1607 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PRECISE) 1608 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_COH) 1609 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_BARRIER) 1610 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_GBR) 1611 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SWAP) 1612 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_IO_MEM) 1613 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_OFF_MASK) 1614 MACROFIELD_LINE(BRIDGE_DEVICE(0), b_device[0].reg) 1615 MACROFIELD_LINE(BRIDGE_DEVICE(1), b_device[1].reg) 1616 MACROFIELD_LINE(BRIDGE_DEVICE(2), b_device[2].reg) 1617 MACROFIELD_LINE(BRIDGE_DEVICE(3), b_device[3].reg) 1618 MACROFIELD_LINE(BRIDGE_DEVICE(4), b_device[4].reg) 1619 MACROFIELD_LINE(BRIDGE_DEVICE(5), b_device[5].reg) 1620 MACROFIELD_LINE(BRIDGE_DEVICE(6), b_device[6].reg) 1621 MACROFIELD_LINE(BRIDGE_DEVICE(7), b_device[7].reg) 1622 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF0, b_wr_req_buf[0].reg) 1623 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(0), b_wr_req_buf[0].reg) 1624 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(1), b_wr_req_buf[1].reg) 1625 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(2), b_wr_req_buf[2].reg) 1626 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(3), b_wr_req_buf[3].reg) 1627 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(4), b_wr_req_buf[4].reg) 1628 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(5), b_wr_req_buf[5].reg) 1629 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(6), b_wr_req_buf[6].reg) 1630 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(7), b_wr_req_buf[7].reg) 1631 MACROFIELD_LINE(BRIDGE_EVEN_RESP, b_even_resp) 1632 MACROFIELD_LINE(BRIDGE_ODD_RESP, b_odd_resp) 1633 MACROFIELD_LINE(BRIDGE_RESP_STATUS, b_resp_status) 1634 MACROFIELD_LINE(BRIDGE_RESP_CLEAR, b_resp_clear) 1635 MACROFIELD_LINE(BRIDGE_ATE_RAM, b_int_ate_ram) 1636 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV0, b_type0_cfg_dev[0]) 1637 1638 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(0), b_type0_cfg_dev[0]) 1639 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,0), b_type0_cfg_dev[0].f[0]) 1640 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,1), b_type0_cfg_dev[0].f[1]) 1641 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,2), b_type0_cfg_dev[0].f[2]) 1642 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,3), b_type0_cfg_dev[0].f[3]) 1643 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,4), b_type0_cfg_dev[0].f[4]) 1644 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,5), b_type0_cfg_dev[0].f[5]) 1645 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,6), b_type0_cfg_dev[0].f[6]) 1646 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,7), b_type0_cfg_dev[0].f[7]) 1647 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(1), b_type0_cfg_dev[1]) 1648 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,0), b_type0_cfg_dev[1].f[0]) 1649 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,1), b_type0_cfg_dev[1].f[1]) 1650 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,2), b_type0_cfg_dev[1].f[2]) 1651 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,3), b_type0_cfg_dev[1].f[3]) 1652 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,4), b_type0_cfg_dev[1].f[4]) 1653 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,5), b_type0_cfg_dev[1].f[5]) 1654 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,6), b_type0_cfg_dev[1].f[6]) 1655 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,7), b_type0_cfg_dev[1].f[7]) 1656 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(2), b_type0_cfg_dev[2]) 1657 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,0), b_type0_cfg_dev[2].f[0]) 1658 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,1), b_type0_cfg_dev[2].f[1]) 1659 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,2), b_type0_cfg_dev[2].f[2]) 1660 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,3), b_type0_cfg_dev[2].f[3]) 1661 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,4), b_type0_cfg_dev[2].f[4]) 1662 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,5), b_type0_cfg_dev[2].f[5]) 1663 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,6), b_type0_cfg_dev[2].f[6]) 1664 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,7), b_type0_cfg_dev[2].f[7]) 1665 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(3), b_type0_cfg_dev[3]) 1666 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,0), b_type0_cfg_dev[3].f[0]) 1667 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,1), b_type0_cfg_dev[3].f[1]) 1668 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,2), b_type0_cfg_dev[3].f[2]) 1669 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,3), b_type0_cfg_dev[3].f[3]) 1670 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,4), b_type0_cfg_dev[3].f[4]) 1671 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,5), b_type0_cfg_dev[3].f[5]) 1672 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,6), b_type0_cfg_dev[3].f[6]) 1673 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,7), b_type0_cfg_dev[3].f[7]) 1674 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(4), b_type0_cfg_dev[4]) 1675 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,0), b_type0_cfg_dev[4].f[0]) 1676 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,1), b_type0_cfg_dev[4].f[1]) 1677 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,2), b_type0_cfg_dev[4].f[2]) 1678 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,3), b_type0_cfg_dev[4].f[3]) 1679 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,4), b_type0_cfg_dev[4].f[4]) 1680 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,5), b_type0_cfg_dev[4].f[5]) 1681 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,6), b_type0_cfg_dev[4].f[6]) 1682 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,7), b_type0_cfg_dev[4].f[7]) 1683 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(5), b_type0_cfg_dev[5]) 1684 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,0), b_type0_cfg_dev[5].f[0]) 1685 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,1), b_type0_cfg_dev[5].f[1]) 1686 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,2), b_type0_cfg_dev[5].f[2]) 1687 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,3), b_type0_cfg_dev[5].f[3]) 1688 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,4), b_type0_cfg_dev[5].f[4]) 1689 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,5), b_type0_cfg_dev[5].f[5]) 1690 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,6), b_type0_cfg_dev[5].f[6]) 1691 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,7), b_type0_cfg_dev[5].f[7]) 1692 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(6), b_type0_cfg_dev[6]) 1693 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,0), b_type0_cfg_dev[6].f[0]) 1694 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,1), b_type0_cfg_dev[6].f[1]) 1695 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,2), b_type0_cfg_dev[6].f[2]) 1696 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,3), b_type0_cfg_dev[6].f[3]) 1697 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,4), b_type0_cfg_dev[6].f[4]) 1698 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,5), b_type0_cfg_dev[6].f[5]) 1699 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,6), b_type0_cfg_dev[6].f[6]) 1700 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,7), b_type0_cfg_dev[6].f[7]) 1701 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(7), b_type0_cfg_dev[7]) 1702 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,0), b_type0_cfg_dev[7].f[0]) 1703 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,1), b_type0_cfg_dev[7].f[1]) 1704 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,2), b_type0_cfg_dev[7].f[2]) 1705 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,3), b_type0_cfg_dev[7].f[3]) 1706 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,4), b_type0_cfg_dev[7].f[4]) 1707 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,5), b_type0_cfg_dev[7].f[5]) 1708 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,6), b_type0_cfg_dev[7].f[6]) 1709 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,7), b_type0_cfg_dev[7].f[7]) 1710 1711 MACROFIELD_LINE(BRIDGE_TYPE1_CFG, b_type1_cfg) 1712 MACROFIELD_LINE(BRIDGE_PCI_IACK, b_pci_iack) 1713 MACROFIELD_LINE(BRIDGE_EXT_SSRAM, b_ext_ate_ram) 1714 MACROFIELD_LINE(BRIDGE_DEVIO0, b_devio(0)) 1715 MACROFIELD_LINE(BRIDGE_DEVIO(0), b_devio(0)) 1716 MACROFIELD_LINE(BRIDGE_DEVIO(1), b_devio(1)) 1717 MACROFIELD_LINE(BRIDGE_DEVIO(2), b_devio(2)) 1718 MACROFIELD_LINE(BRIDGE_DEVIO(3), b_devio(3)) 1719 MACROFIELD_LINE(BRIDGE_DEVIO(4), b_devio(4)) 1720 MACROFIELD_LINE(BRIDGE_DEVIO(5), b_devio(5)) 1721 MACROFIELD_LINE(BRIDGE_DEVIO(6), b_devio(6)) 1722 MACROFIELD_LINE(BRIDGE_DEVIO(7), b_devio(7)) 1723 MACROFIELD_LINE(BRIDGE_EXTERNAL_FLASH, b_external_flash) 1724}; 1725#endif 1726 1727#ifdef __cplusplus 1728}; 1729#endif 1730#endif /* C or C++ */ 1731 1732#endif /* _ASM_SN_PCI_BRIDGE_H */ 1733