1/* $Id: l1.h,v 1.1.1.1 2008/10/15 03:29:03 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. All Rights Reserved. 8 */ 9 10#ifndef _ASM_SN_KSYS_L1_H 11#define _ASM_SN_KSYS_L1_H 12 13#include <asm/sn/vector.h> 14#include <asm/sn/addrs.h> 15#include <asm/atomic.h> 16#include <asm/sn/sv.h> 17 18#define BRL1_QSIZE 128 /* power of 2 is more efficient */ 19#define BRL1_BUFSZ 264 /* needs to be large enough 20 * to hold 2 flags, escaped 21 * CRC, type/subchannel byte, 22 * and escaped payload 23 */ 24 25#define BRL1_IQS 32 26#define BRL1_OQS 4 27 28 29typedef struct sc_cq_s { 30 u_char buf[BRL1_QSIZE]; 31 int ipos, opos, tent_next; 32} sc_cq_t; 33 34/* An l1sc_t struct can be associated with the local (C-brick) L1 or an L1 35 * on an R-brick. In the R-brick case, the l1sc_t records a vector path 36 * to the R-brick's junk bus UART. In the C-brick case, we just use the 37 * following flag to denote the local uart. 38 * 39 * This value can't be confused with a network vector because the least- 40 * significant nibble of a network vector cannot be greater than 8. 41 */ 42#define BRL1_LOCALHUB_UART ((net_vec_t)0xf) 43 44/* L1<->Bedrock reserved subchannels */ 45 46/* console channels */ 47#define SC_CONS_CPU0 0x00 48#define SC_CONS_CPU1 0x01 49#define SC_CONS_CPU2 0x02 50#define SC_CONS_CPU3 0x03 51 52#define L1_ELSCUART_SUBCH(p) (p) 53#define L1_ELSCUART_CPU(ch) (ch) 54 55#define SC_CONS_SYSTEM CPUS_PER_NODE 56 57/* mapping subchannels to queues */ 58#define MAP_IQ(s) (s) 59#define MAP_OQ(s) (s) 60 61#define BRL1_NUM_SUBCHANS 32 62#define BRL1_CMD_SUBCH 16 63#define BRL1_EVENT_SUBCH (BRL1_NUM_SUBCHANS - 1) 64#define BRL1_SUBCH_RSVD 0 65#define BRL1_SUBCH_FREE (-1) 66 67/* constants for L1 hwgraph vertex info */ 68#define CBRICK_L1 (__psint_t)1 69#define IOBRICK_L1 (__psint_t)2 70#define RBRICK_L1 (__psint_t)3 71 72 73struct l1sc_s; 74/* Saved off interrupt frame */ 75typedef struct brl1_intr_frame { 76 int bf_irq; /* irq received */ 77 void *bf_dev_id; /* device information */ 78 struct pt_regs *bf_regs; /* register frame */ 79} brl1_intr_frame_t; 80 81typedef void (*brl1_notif_t)(int, void *, struct pt_regs *, struct l1sc_s *, int); 82typedef int (*brl1_uartf_t)(struct l1sc_s *); 83 84/* structure for controlling a subchannel */ 85typedef struct brl1_sch_s { 86 int use; /* if this subchannel is free, 87 * use == BRL1_SUBCH_FREE */ 88 uint target; /* type, rack and slot of component to 89 * which this subchannel is directed */ 90 atomic_t packet_arrived; /* true if packet arrived on 91 * this subchannel */ 92 sc_cq_t * iqp; /* input queue for this subchannel */ 93 sv_t arrive_sv; /* used to wait for a packet */ 94 spinlock_t data_lock; /* synchronize access to input queues and 95 * other fields of the brl1_sch_s struct */ 96 brl1_notif_t tx_notify; /* notify higher layer that transmission may 97 * continue */ 98 brl1_notif_t rx_notify; /* notify higher layer that a packet has been 99 * received */ 100 brl1_intr_frame_t irq_frame; /* saved off irq information */ 101} brl1_sch_t; 102 103/* br<->l1 protocol states */ 104#define BRL1_IDLE 0 105#define BRL1_FLAG 1 106#define BRL1_HDR 2 107#define BRL1_BODY 3 108#define BRL1_ESC 4 109#define BRL1_RESET 7 110 111 112#ifndef __ASSEMBLY__ 113 114/* 115 * l1sc_t structure-- tracks protocol state, open subchannels, etc. 116 */ 117typedef struct l1sc_s { 118 nasid_t nasid; /* nasid with which this instance 119 * of the structure is associated */ 120 moduleid_t modid; /* module id of this brick */ 121 u_char verbose; /* non-zero if elscuart routines should 122 * prefix output */ 123 net_vec_t uart; /* vector path to UART, or BRL1_LOCALUART */ 124 int sent; /* number of characters sent */ 125 int send_len; /* number of characters in send buf */ 126 brl1_uartf_t putc_f; /* pointer to UART putc function */ 127 brl1_uartf_t getc_f; /* pointer to UART getc function */ 128 129 spinlock_t send_lock; /* arbitrates send synchronization */ 130 spinlock_t recv_lock; /* arbitrates uart receive access */ 131 spinlock_t subch_lock; /* arbitrates subchannel allocation */ 132 cpuid_t intr_cpu; /* cpu that receives L1 interrupts */ 133 134 u_char send_in_use; /* non-zero if send buffer contains an 135 * unsent or partially-sent packet */ 136 u_char fifo_space; /* current depth of UART send FIFO */ 137 138 u_char brl1_state; /* current state of the receive side */ 139 u_char brl1_last_hdr; /* last header byte received */ 140 141 char send[BRL1_BUFSZ]; /* send buffer */ 142 143 int sol; /* "start of line" (see elscuart routines) */ 144 int cons_listen; /* non-zero if the elscuart interface should 145 * also check the system console subchannel */ 146 brl1_sch_t subch[BRL1_NUM_SUBCHANS]; 147 /* subchannels provided by link */ 148 149 sc_cq_t garbage_q; /* a place to put unsolicited packets */ 150 sc_cq_t oq[BRL1_OQS]; /* elscuart output queues */ 151 152} l1sc_t; 153 154 155/* error codes */ 156#define BRL1_VALID 0 157#define BRL1_FULL_Q (-1) 158#define BRL1_CRC (-2) 159#define BRL1_PROTOCOL (-3) 160#define BRL1_NO_MESSAGE (-4) 161#define BRL1_LINK (-5) 162#define BRL1_BUSY (-6) 163 164#define SC_SUCCESS BRL1_VALID 165#define SC_NMSG BRL1_NO_MESSAGE 166#define SC_BUSY BRL1_BUSY 167#define SC_NOPEN (-7) 168#define SC_BADSUBCH (-8) 169#define SC_TIMEDOUT (-9) 170#define SC_NSUBCH (-10) 171 172 173/* L1 Target Addresses */ 174/* 175 * L1 commands and responses use source/target addresses that are 176 * 32 bits long. These are broken up into multiple bitfields that 177 * specify the type of the target controller (could actually be L2 178 * L3, not just L1), the rack and bay of the target, and the task 179 * id (L1 functionality is divided into several independent "tasks" 180 * that can each receive command requests and transmit responses) 181 */ 182#define L1_ADDR_TYPE_SHFT 28 183#define L1_ADDR_TYPE_MASK 0xF0000000 184#define L1_ADDR_TYPE_L1 0x00 /* L1 system controller */ 185#define L1_ADDR_TYPE_L2 0x01 /* L2 system controller */ 186#define L1_ADDR_TYPE_L3 0x02 /* L3 system controller */ 187#define L1_ADDR_TYPE_CBRICK 0x03 /* attached C brick */ 188#define L1_ADDR_TYPE_IOBRICK 0x04 /* attached I/O brick */ 189 190#define L1_ADDR_RACK_SHFT 18 191#define L1_ADDR_RACK_MASK 0x0FFC0000 192#define L1_ADDR_RACK_LOCAL 0x3ff /* local brick's rack */ 193 194#define L1_ADDR_BAY_SHFT 12 195#define L1_ADDR_BAY_MASK 0x0003F000 196#define L1_ADDR_BAY_LOCAL 0x3f /* local brick's bay */ 197 198#define L1_ADDR_TASK_SHFT 0 199#define L1_ADDR_TASK_MASK 0x0000001F 200#define L1_ADDR_TASK_INVALID 0x00 /* invalid task */ 201#define L1_ADDR_TASK_IROUTER 0x01 /* iRouter */ 202#define L1_ADDR_TASK_SYS_MGMT 0x02 /* system management port */ 203#define L1_ADDR_TASK_CMD 0x03 /* command interpreter */ 204#define L1_ADDR_TASK_ENV 0x04 /* environmental monitor */ 205#define L1_ADDR_TASK_BEDROCK 0x05 /* bedrock */ 206#define L1_ADDR_TASK_GENERAL 0x06 /* general requests */ 207 208#define L1_ADDR_LOCAL \ 209 (L1_ADDR_TYPE_L1 << L1_ADDR_TYPE_SHFT) | \ 210 (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \ 211 (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT) 212 213#define L1_ADDR_LOCALIO \ 214 (L1_ADDR_TYPE_IOBRICK << L1_ADDR_TYPE_SHFT) | \ 215 (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \ 216 (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT) 217 218#define L1_ADDR_LOCAL_SHFT L1_ADDR_BAY_SHFT 219 220/* response argument types */ 221#define L1_ARG_INT 0x00 /* 4-byte integer (big-endian) */ 222#define L1_ARG_ASCII 0x01 /* null-terminated ASCII string */ 223#define L1_ARG_UNKNOWN 0x80 /* unknown data type. The low 224 * 7 bits will contain the data 225 * length. */ 226 227/* response codes */ 228#define L1_RESP_OK 0 /* no problems encountered */ 229#define L1_RESP_IROUTER (- 1) /* iRouter error */ 230#define L1_RESP_ARGC (-100) /* arg count mismatch */ 231#define L1_RESP_REQC (-101) /* bad request code */ 232#define L1_RESP_NAVAIL (-104) /* requested data not available */ 233#define L1_RESP_ARGVAL (-105) /* arg value out of range */ 234#define L1_RESP_INVAL (-107) /* requested data invalid */ 235 236/* L1 general requests */ 237 238/* request codes */ 239#define L1_REQ_RDBG 0x0001 /* read debug switches */ 240#define L1_REQ_RRACK 0x0002 /* read brick rack & bay */ 241#define L1_REQ_RRBT 0x0003 /* read brick rack, bay & type */ 242#define L1_REQ_SER_NUM 0x0004 /* read brick serial number */ 243#define L1_REQ_FW_REV 0x0005 /* read L1 firmware revision */ 244#define L1_REQ_EEPROM 0x0006 /* read EEPROM info */ 245#define L1_REQ_EEPROM_FMT 0x0007 /* get EEPROM data format & size */ 246#define L1_REQ_SYS_SERIAL 0x0008 /* read system serial number */ 247#define L1_REQ_PARTITION_GET 0x0009 /* read partition id */ 248#define L1_REQ_PORTSPEED 0x000a /* get ioport speed */ 249 250#define L1_REQ_CONS_SUBCH 0x1002 /* select this node's console 251 subchannel */ 252#define L1_REQ_CONS_NODE 0x1003 /* volunteer to be the master 253 (console-hosting) node */ 254#define L1_REQ_DISP1 0x1004 /* write line 1 of L1 display */ 255#define L1_REQ_DISP2 0x1005 /* write line 2 of L1 display */ 256#define L1_REQ_PARTITION_SET 0x1006 /* set partition id */ 257#define L1_REQ_EVENT_SUBCH 0x1007 /* set the subchannel for system 258 controller event transmission */ 259 260#define L1_REQ_RESET 0x2000 /* request a full system reset */ 261#define L1_REQ_PCI_UP 0x2001 /* power up pci slot or bus */ 262#define L1_REQ_PCI_DOWN 0x2002 /* power down pci slot or bus */ 263#define L1_REQ_PCI_RESET 0x2003 /* reset pci bus or slot */ 264 265/* L1 command interpreter requests */ 266 267/* request codes */ 268#define L1_REQ_EXEC_CMD 0x0000 /* interpret and execute an ASCII 269 command string */ 270 271 272/* brick type response codes */ 273#define L1_BRICKTYPE_C 0x43 274#define L1_BRICKTYPE_I 0x49 275#define L1_BRICKTYPE_P 0x50 276#define L1_BRICKTYPE_R 0x52 277#define L1_BRICKTYPE_X 0x58 278 279/* EEPROM codes (for the "read EEPROM" request) */ 280/* c brick */ 281#define L1_EEP_NODE 0x00 /* node board */ 282#define L1_EEP_PIMM0 0x01 283#define L1_EEP_PIMM(x) (L1_EEP_PIMM0+(x)) 284#define L1_EEP_DIMM0 0x03 285#define L1_EEP_DIMM(x) (L1_EEP_DIMM0+(x)) 286 287/* other brick types */ 288#define L1_EEP_POWER 0x00 /* power board */ 289#define L1_EEP_LOGIC 0x01 /* logic board */ 290 291/* info area types */ 292#define L1_EEP_CHASSIS 1 /* chassis info area */ 293#define L1_EEP_BOARD 2 /* board info area */ 294#define L1_EEP_IUSE 3 /* internal use area */ 295#define L1_EEP_SPD 4 /* serial presence detect record */ 296 297typedef uint32_t l1addr_t; 298 299#define L1_BUILD_ADDR(addr,at,r,s,t) \ 300 (*(l1addr_t *)(addr) = ((l1addr_t)(at) << L1_ADDR_TYPE_SHFT) | \ 301 ((l1addr_t)(r) << L1_ADDR_RACK_SHFT) | \ 302 ((l1addr_t)(s) << L1_ADDR_BAY_SHFT) | \ 303 ((l1addr_t)(t) << L1_ADDR_TASK_SHFT)) 304 305#define L1_ADDRESS_TO_TASK(addr,trb,tsk) \ 306 (*(l1addr_t *)(addr) = (l1addr_t)(trb) | \ 307 ((l1addr_t)(tsk) << L1_ADDR_TASK_SHFT)) 308 309 310#define L1_DISPLAY_LINE_LENGTH 12 /* L1 display characters/line */ 311 312#ifdef L1_DISP_2LINES 313#define L1_DISPLAY_LINES 2 /* number of L1 display lines */ 314#else 315#define L1_DISPLAY_LINES 1 /* number of L1 display lines available 316 * to system software */ 317#endif 318 319#define SC_EVENT_CLASS_MASK ((unsigned short)0xff00) 320 321#define bzero(d, n) memset((d), 0, (n)) 322 323/* public interfaces to L1 system controller */ 324 325int sc_open( l1sc_t *sc, uint target ); 326int sc_close( l1sc_t *sc, int ch ); 327int sc_construct_msg( l1sc_t *sc, int ch, 328 char *msg, int msg_len, 329 uint addr_task, short req_code, 330 int req_nargs, ... ); 331int sc_interpret_resp( char *resp, int resp_nargs, ... ); 332int sc_send( l1sc_t *sc, int ch, char *msg, int len, int wait ); 333int sc_recv( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block ); 334int sc_command( l1sc_t *sc, int ch, char *cmd, char *resp, int *len ); 335int sc_command_kern( l1sc_t *sc, int ch, char *cmd, char *resp, int *len ); 336int sc_poll( l1sc_t *sc, int ch ); 337void sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart ); 338void sc_intr_enable( l1sc_t *sc ); 339 340int elsc_rack_bay_get(l1sc_t *e, uint *rack, uint *bay); 341int elsc_rack_bay_type_get(l1sc_t *e, uint *rack, 342 uint *bay, uint *brick_type); 343int elsc_cons_subch(l1sc_t *e, uint ch); 344int elsc_cons_node(l1sc_t *e); 345int elsc_display_line(l1sc_t *e, char *line, int lnum); 346 347extern l1sc_t *get_elsc( void ); 348#define get_l1sc get_elsc 349#define get_master_l1sc get_l1sc 350 351int router_module_get( nasid_t nasid, net_vec_t path ); 352 353int iobrick_rack_bay_type_get( l1sc_t *sc, uint *rack, 354 uint *bay, uint *brick_type ); 355int iobrick_module_get( l1sc_t *sc ); 356int iobrick_pci_slot_pwr( l1sc_t *sc, int bus, int slot, int up ); 357int iobrick_pci_bus_pwr( l1sc_t *sc, int bus, int up ); 358int iobrick_sc_version( l1sc_t *sc, char *result ); 359 360 361#endif /* !__ASSEMBLY__ */ 362#endif /* _ASM_SN_KSYS_L1_H */ 363