1#ifndef _ASM_IA64_PAL_H 2#define _ASM_IA64_PAL_H 3 4/* 5 * Processor Abstraction Layer definitions. 6 * 7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0 8 * chapter 11 IA-64 Processor Abstraction Layer 9 * 10 * Copyright (C) 1998-2001 Hewlett-Packard Co 11 * David Mosberger-Tang <davidm@hpl.hp.com> 12 * Stephane Eranian <eranian@hpl.hp.com> 13 * Copyright (C) 1999 VA Linux Systems 14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> 16 * 17 * 99/10/01 davidm Make sure we pass zero for reserved parameters. 18 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6. 19 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info 20 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added 21 * 00/05/25 eranian Support for stack calls, and static physical calls 22 * 00/06/18 eranian Support for stacked physical calls 23 */ 24 25/* 26 * Note that some of these calls use a static-register only calling 27 * convention which has nothing to do with the regular calling 28 * convention. 29 */ 30#define PAL_CACHE_FLUSH 1 /* flush i/d cache */ 31#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */ 32#define PAL_CACHE_INIT 3 /* initialize i/d cache */ 33#define PAL_CACHE_SUMMARY 4 /* get summary of cache heirarchy */ 34#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */ 35#define PAL_PTCE_INFO 6 /* purge TLB info */ 36#define PAL_VM_INFO 7 /* return supported virtual memory features */ 37#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */ 38#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */ 39#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */ 40#define PAL_DEBUG_INFO 11 /* get number of debug registers */ 41#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */ 42#define PAL_FREQ_BASE 13 /* base frequency of the platform */ 43#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */ 44#define PAL_PERF_MON_INFO 15 /* return performance monitor info */ 45#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */ 46#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */ 47#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */ 48#define PAL_RSE_INFO 19 /* return rse information */ 49#define PAL_VERSION 20 /* return version of PAL code */ 50#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */ 51#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */ 52#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */ 53#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */ 54#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */ 55#define PAL_MC_RESUME 26 /* Return to interrupted process */ 56#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */ 57#define PAL_HALT 28 /* enter the low power HALT state */ 58#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/ 59#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */ 60#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */ 61#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */ 62#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */ 63#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */ 64 65#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */ 66#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */ 67#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/ 68#define PAL_SHUTDOWN 40 /* enter processor shutdown state */ 69#define PAL_PREFETCH_VISIBILITY 41 70 71#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ 72#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */ 73#define PAL_TEST_PROC 258 /* perform late processor self-test */ 74#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ 75#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ 76#define PAL_VM_TR_READ 261 /* read contents of translation register */ 77 78#ifndef __ASSEMBLY__ 79 80#include <linux/types.h> 81 82/* 83 * Data types needed to pass information into PAL procedures and 84 * interpret information returned by them. 85 */ 86 87/* Return status from the PAL procedure */ 88typedef s64 pal_status_t; 89 90#define PAL_STATUS_SUCCESS 0 /* No error */ 91#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */ 92#define PAL_STATUS_EINVAL (-2) /* Invalid argument */ 93#define PAL_STATUS_ERROR (-3) /* Error */ 94#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the 95 * specified level and type of 96 * cache without sideeffects 97 * and "restrict" was 1 98 */ 99 100/* Processor cache level in the heirarchy */ 101typedef u64 pal_cache_level_t; 102#define PAL_CACHE_LEVEL_L0 0 /* L0 */ 103#define PAL_CACHE_LEVEL_L1 1 /* L1 */ 104#define PAL_CACHE_LEVEL_L2 2 /* L2 */ 105 106 107/* Processor cache type at a particular level in the heirarchy */ 108 109typedef u64 pal_cache_type_t; 110#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */ 111#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */ 112#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */ 113 114 115#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */ 116#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */ 117 118/* Processor cache line size in bytes */ 119typedef int pal_cache_line_size_t; 120 121/* Processor cache line state */ 122typedef u64 pal_cache_line_state_t; 123#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */ 124#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */ 125#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */ 126#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */ 127 128typedef struct pal_freq_ratio { 129 u64 den : 32, num : 32; /* numerator & denominator */ 130} itc_ratio, proc_ratio; 131 132typedef union pal_cache_config_info_1_s { 133 struct { 134 u64 u : 1, /* 0 Unified cache ? */ 135 at : 2, /* 2-1 Cache mem attr*/ 136 reserved : 5, /* 7-3 Reserved */ 137 associativity : 8, /* 16-8 Associativity*/ 138 line_size : 8, /* 23-17 Line size */ 139 stride : 8, /* 31-24 Stride */ 140 store_latency : 8, /*39-32 Store latency*/ 141 load_latency : 8, /* 47-40 Load latency*/ 142 store_hints : 8, /* 55-48 Store hints*/ 143 load_hints : 8; /* 63-56 Load hints */ 144 } pcci1_bits; 145 u64 pcci1_data; 146} pal_cache_config_info_1_t; 147 148typedef union pal_cache_config_info_2_s { 149 struct { 150 u64 cache_size : 32, /*cache size in bytes*/ 151 152 153 alias_boundary : 8, /* 39-32 aliased addr 154 * separation for max 155 * performance. 156 */ 157 tag_ls_bit : 8, /* 47-40 LSb of addr*/ 158 tag_ms_bit : 8, /* 55-48 MSb of addr*/ 159 reserved : 8; /* 63-56 Reserved */ 160 } pcci2_bits; 161 u64 pcci2_data; 162} pal_cache_config_info_2_t; 163 164 165typedef struct pal_cache_config_info_s { 166 pal_status_t pcci_status; 167 pal_cache_config_info_1_t pcci_info_1; 168 pal_cache_config_info_2_t pcci_info_2; 169 u64 pcci_reserved; 170} pal_cache_config_info_t; 171 172#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints 173#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints 174#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency 175#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency 176#define pcci_stride pcci_info_1.pcci1_bits.stride 177#define pcci_line_size pcci_info_1.pcci1_bits.line_size 178#define pcci_assoc pcci_info_1.pcci1_bits.associativity 179#define pcci_cache_attr pcci_info_1.pcci1_bits.at 180#define pcci_unified pcci_info_1.pcci1_bits.u 181#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit 182#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit 183#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary 184#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size 185 186 187 188/* Possible values for cache attributes */ 189 190#define PAL_CACHE_ATTR_WT 0 /* Write through cache */ 191#define PAL_CACHE_ATTR_WB 1 /* Write back cache */ 192#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write 193 * back depending on TLB 194 * memory attributes 195 */ 196 197 198/* Possible values for cache hints */ 199 200#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */ 201#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */ 202#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */ 203 204/* Processor cache protection information */ 205typedef union pal_cache_protection_element_u { 206 u32 pcpi_data; 207 struct { 208 u32 data_bits : 8, /* # data bits covered by 209 * each unit of protection 210 */ 211 212 tagprot_lsb : 6, /* Least -do- */ 213 tagprot_msb : 6, /* Most Sig. tag address 214 * bit that this 215 * protection covers. 216 */ 217 prot_bits : 6, /* # of protection bits */ 218 method : 4, /* Protection method */ 219 t_d : 2; /* Indicates which part 220 * of the cache this 221 * protection encoding 222 * applies. 223 */ 224 } pcp_info; 225} pal_cache_protection_element_t; 226 227#define pcpi_cache_prot_part pcp_info.t_d 228#define pcpi_prot_method pcp_info.method 229#define pcpi_prot_bits pcp_info.prot_bits 230#define pcpi_tagprot_msb pcp_info.tagprot_msb 231#define pcpi_tagprot_lsb pcp_info.tagprot_lsb 232#define pcpi_data_bits pcp_info.data_bits 233 234/* Processor cache part encodings */ 235#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */ 236#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */ 237#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is 238 * more significant ) 239 */ 240#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is 241 * more significant ) 242 */ 243#define PAL_CACHE_PROT_PART_MAX 6 244 245 246typedef struct pal_cache_protection_info_s { 247 pal_status_t pcpi_status; 248 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX]; 249} pal_cache_protection_info_t; 250 251 252/* Processor cache protection method encodings */ 253#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */ 254#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */ 255#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */ 256#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */ 257 258 259/* Processor cache line identification in the heirarchy */ 260typedef union pal_cache_line_id_u { 261 u64 pclid_data; 262 struct { 263 u64 cache_type : 8, /* 7-0 cache type */ 264 level : 8, /* 15-8 level of the 265 * cache in the 266 * heirarchy. 267 */ 268 way : 8, /* 23-16 way in the set 269 */ 270 part : 8, /* 31-24 part of the 271 * cache 272 */ 273 reserved : 32; /* 63-32 is reserved*/ 274 } pclid_info_read; 275 struct { 276 u64 cache_type : 8, /* 7-0 cache type */ 277 level : 8, /* 15-8 level of the 278 * cache in the 279 * heirarchy. 280 */ 281 way : 8, /* 23-16 way in the set 282 */ 283 part : 8, /* 31-24 part of the 284 * cache 285 */ 286 mesi : 8, /* 39-32 cache line 287 * state 288 */ 289 start : 8, /* 47-40 lsb of data to 290 * invert 291 */ 292 length : 8, /* 55-48 #bits to 293 * invert 294 */ 295 trigger : 8; /* 63-56 Trigger error 296 * by doing a load 297 * after the write 298 */ 299 300 } pclid_info_write; 301} pal_cache_line_id_u_t; 302 303#define pclid_read_part pclid_info_read.part 304#define pclid_read_way pclid_info_read.way 305#define pclid_read_level pclid_info_read.level 306#define pclid_read_cache_type pclid_info_read.cache_type 307 308#define pclid_write_trigger pclid_info_write.trigger 309#define pclid_write_length pclid_info_write.length 310#define pclid_write_start pclid_info_write.start 311#define pclid_write_mesi pclid_info_write.mesi 312#define pclid_write_part pclid_info_write.part 313#define pclid_write_way pclid_info_write.way 314#define pclid_write_level pclid_info_write.level 315#define pclid_write_cache_type pclid_info_write.cache_type 316 317/* Processor cache line part encodings */ 318#define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */ 319#define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */ 320#define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */ 321#define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */ 322#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag 323 * protection 324 */ 325typedef struct pal_cache_line_info_s { 326 pal_status_t pcli_status; /* Return status of the read cache line 327 * info call. 328 */ 329 u64 pcli_data; /* 64-bit data, tag, protection bits .. */ 330 u64 pcli_data_len; /* data length in bits */ 331 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */ 332 333} pal_cache_line_info_t; 334 335 336/* Machine Check related crap */ 337 338/* Pending event status bits */ 339typedef u64 pal_mc_pending_events_t; 340 341#define PAL_MC_PENDING_MCA (1 << 0) 342#define PAL_MC_PENDING_INIT (1 << 1) 343 344/* Error information type */ 345typedef u64 pal_mc_info_index_t; 346 347#define PAL_MC_INFO_PROCESSOR 0 /* Processor */ 348#define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */ 349#define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */ 350#define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */ 351#define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */ 352#define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */ 353#define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */ 354#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation 355 * dependent 356 */ 357 358 359typedef struct pal_process_state_info_s { 360 u64 reserved1 : 2, 361 rz : 1, /* PAL_CHECK processor 362 * rendezvous 363 * successful. 364 */ 365 366 ra : 1, /* PAL_CHECK attempted 367 * a rendezvous. 368 */ 369 me : 1, /* Distinct multiple 370 * errors occurred 371 */ 372 373 mn : 1, /* Min. state save 374 * area has been 375 * registered with PAL 376 */ 377 378 sy : 1, /* Storage integrity 379 * synched 380 */ 381 382 383 co : 1, /* Continuable */ 384 ci : 1, /* MC isolated */ 385 us : 1, /* Uncontained storage 386 * damage. 387 */ 388 389 390 hd : 1, /* Non-essential hw 391 * lost (no loss of 392 * functionality) 393 * causing the 394 * processor to run in 395 * degraded mode. 396 */ 397 398 tl : 1, /* 1 => MC occurred 399 * after an instr was 400 * executed but before 401 * the trap that 402 * resulted from instr 403 * execution was 404 * generated. 405 * (Trap Lost ) 406 */ 407 op : 3, /* Operation that 408 * caused the machine 409 * check 410 */ 411 412 dy : 1, /* Processor dynamic 413 * state valid 414 */ 415 416 417 in : 1, /* 0 = MC, 1 = INIT */ 418 rs : 1, /* RSE valid */ 419 cm : 1, /* MC corrected */ 420 ex : 1, /* MC is expected */ 421 cr : 1, /* Control regs valid*/ 422 pc : 1, /* Perf cntrs valid */ 423 dr : 1, /* Debug regs valid */ 424 tr : 1, /* Translation regs 425 * valid 426 */ 427 rr : 1, /* Region regs valid */ 428 ar : 1, /* App regs valid */ 429 br : 1, /* Branch regs valid */ 430 pr : 1, /* Predicate registers 431 * valid 432 */ 433 434 fp : 1, /* fp registers valid*/ 435 b1 : 1, /* Preserved bank one 436 * general registers 437 * are valid 438 */ 439 b0 : 1, /* Preserved bank zero 440 * general registers 441 * are valid 442 */ 443 gr : 1, /* General registers 444 * are valid 445 * (excl. banked regs) 446 */ 447 dsize : 16, /* size of dynamic 448 * state returned 449 * by the processor 450 */ 451 452 reserved2 : 12, 453 cc : 1, /* Cache check */ 454 tc : 1, /* TLB check */ 455 bc : 1, /* Bus check */ 456 uc : 1; /* Unknown check */ 457 458} pal_processor_state_info_t; 459 460typedef struct pal_cache_check_info_s { 461 u64 reserved1 : 16, 462 way : 5, /* Way in which the 463 * error occurred 464 */ 465 reserved2 : 1, 466 mc : 1, /* Machine check corrected */ 467 tv : 1, /* Target address 468 * structure is valid 469 */ 470 471 wv : 1, /* Way field valid */ 472 op : 3, /* Type of cache 473 * operation that 474 * caused the machine 475 * check. 476 */ 477 478 dl : 1, /* Failure in data part 479 * of cache line 480 */ 481 tl : 1, /* Failure in tag part 482 * of cache line 483 */ 484 dc : 1, /* Failure in dcache */ 485 ic : 1, /* Failure in icache */ 486 index : 24, /* Cache line index */ 487 mv : 1, /* mesi valid */ 488 mesi : 3, /* Cache line state */ 489 level : 4; /* Cache level */ 490 491} pal_cache_check_info_t; 492 493typedef struct pal_tlb_check_info_s { 494 495 u64 tr_slot : 8, /* Slot# of TR where 496 * error occurred 497 */ 498 reserved2 : 8, 499 dtr : 1, /* Fail in data TR */ 500 itr : 1, /* Fail in inst TR */ 501 dtc : 1, /* Fail in data TC */ 502 itc : 1, /* Fail in inst. TC */ 503 mc : 1, /* Machine check corrected */ 504 reserved1 : 43; 505 506} pal_tlb_check_info_t; 507 508typedef struct pal_bus_check_info_s { 509 u64 size : 5, /* Xaction size*/ 510 ib : 1, /* Internal bus error */ 511 eb : 1, /* External bus error */ 512 cc : 1, /* Error occurred 513 * during cache-cache 514 * transfer. 515 */ 516 type : 8, /* Bus xaction type*/ 517 sev : 5, /* Bus error severity*/ 518 tv : 1, /* Targ addr valid */ 519 rp : 1, /* Resp addr valid */ 520 rq : 1, /* Req addr valid */ 521 bsi : 8, /* Bus error status 522 * info 523 */ 524 mc : 1, /* Machine check corrected */ 525 reserved1 : 31; 526} pal_bus_check_info_t; 527 528typedef union pal_mc_error_info_u { 529 u64 pmei_data; 530 pal_processor_state_info_t pme_processor; 531 pal_cache_check_info_t pme_cache; 532 pal_tlb_check_info_t pme_tlb; 533 pal_bus_check_info_t pme_bus; 534} pal_mc_error_info_t; 535 536#define pmci_proc_unknown_check pme_processor.uc 537#define pmci_proc_bus_check pme_processor.bc 538#define pmci_proc_tlb_check pme_processor.tc 539#define pmci_proc_cache_check pme_processor.cc 540#define pmci_proc_dynamic_state_size pme_processor.dsize 541#define pmci_proc_gpr_valid pme_processor.gr 542#define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0 543#define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1 544#define pmci_proc_fp_valid pme_processor.fp 545#define pmci_proc_predicate_regs_valid pme_processor.pr 546#define pmci_proc_branch_regs_valid pme_processor.br 547#define pmci_proc_app_regs_valid pme_processor.ar 548#define pmci_proc_region_regs_valid pme_processor.rr 549#define pmci_proc_translation_regs_valid pme_processor.tr 550#define pmci_proc_debug_regs_valid pme_processor.dr 551#define pmci_proc_perf_counters_valid pme_processor.pc 552#define pmci_proc_control_regs_valid pme_processor.cr 553#define pmci_proc_machine_check_expected pme_processor.ex 554#define pmci_proc_machine_check_corrected pme_processor.cm 555#define pmci_proc_rse_valid pme_processor.rs 556#define pmci_proc_machine_check_or_init pme_processor.in 557#define pmci_proc_dynamic_state_valid pme_processor.dy 558#define pmci_proc_operation pme_processor.op 559#define pmci_proc_trap_lost pme_processor.tl 560#define pmci_proc_hardware_damage pme_processor.hd 561#define pmci_proc_uncontained_storage_damage pme_processor.us 562#define pmci_proc_machine_check_isolated pme_processor.ci 563#define pmci_proc_continuable pme_processor.co 564#define pmci_proc_storage_intergrity_synced pme_processor.sy 565#define pmci_proc_min_state_save_area_regd pme_processor.mn 566#define pmci_proc_distinct_multiple_errors pme_processor.me 567#define pmci_proc_pal_attempted_rendezvous pme_processor.ra 568#define pmci_proc_pal_rendezvous_complete pme_processor.rz 569 570 571#define pmci_cache_level pme_cache.level 572#define pmci_cache_line_state pme_cache.mesi 573#define pmci_cache_line_state_valid pme_cache.mv 574#define pmci_cache_line_index pme_cache.index 575#define pmci_cache_instr_cache_fail pme_cache.ic 576#define pmci_cache_data_cache_fail pme_cache.dc 577#define pmci_cache_line_tag_fail pme_cache.tl 578#define pmci_cache_line_data_fail pme_cache.dl 579#define pmci_cache_operation pme_cache.op 580#define pmci_cache_way_valid pme_cache.wv 581#define pmci_cache_target_address_valid pme_cache.tv 582#define pmci_cache_way pme_cache.way 583#define pmci_cache_mc pme_cache.mc 584 585#define pmci_tlb_instr_translation_cache_fail pme_tlb.itc 586#define pmci_tlb_data_translation_cache_fail pme_tlb.dtc 587#define pmci_tlb_instr_translation_reg_fail pme_tlb.itr 588#define pmci_tlb_data_translation_reg_fail pme_tlb.dtr 589#define pmci_tlb_translation_reg_slot pme_tlb.tr_slot 590#define pmci_tlb_mc pme_tlb.mc 591 592#define pmci_bus_status_info pme_bus.bsi 593#define pmci_bus_req_address_valid pme_bus.rq 594#define pmci_bus_resp_address_valid pme_bus.rp 595#define pmci_bus_target_address_valid pme_bus.tv 596#define pmci_bus_error_severity pme_bus.sev 597#define pmci_bus_transaction_type pme_bus.type 598#define pmci_bus_cache_cache_transfer pme_bus.cc 599#define pmci_bus_transaction_size pme_bus.size 600#define pmci_bus_internal_error pme_bus.ib 601#define pmci_bus_external_error pme_bus.eb 602#define pmci_bus_mc pme_bus.mc 603 604/* 605 * NOTE: this min_state_save area struct only includes the 1KB 606 * architectural state save area. The other 3 KB is scratch space 607 * for PAL. 608 */ 609 610typedef struct pal_min_state_area_s { 611 u64 pmsa_nat_bits; /* nat bits for saved GRs */ 612 u64 pmsa_gr[15]; /* GR1 - GR15 */ 613 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */ 614 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */ 615 u64 pmsa_pr; /* predicate registers */ 616 u64 pmsa_br0; /* branch register 0 */ 617 u64 pmsa_rsc; /* ar.rsc */ 618 u64 pmsa_iip; /* cr.iip */ 619 u64 pmsa_ipsr; /* cr.ipsr */ 620 u64 pmsa_ifs; /* cr.ifs */ 621 u64 pmsa_xip; /* previous iip */ 622 u64 pmsa_xpsr; /* previous psr */ 623 u64 pmsa_xfs; /* previous ifs */ 624 u64 pmsa_reserved[71]; /* pal_min_state_area should total to 1KB */ 625} pal_min_state_area_t; 626 627 628struct ia64_pal_retval { 629 /* 630 * A zero status value indicates call completed without error. 631 * A negative status value indicates reason of call failure. 632 * A positive status value indicates success but an 633 * informational value should be printed (e.g., "reboot for 634 * change to take effect"). 635 */ 636 s64 status; 637 u64 v0; 638 u64 v1; 639 u64 v2; 640}; 641 642/* 643 * Note: Currently unused PAL arguments are generally labeled 644 * "reserved" so the value specified in the PAL documentation 645 * (generally 0) MUST be passed. Reserved parameters are not optional 646 * parameters. 647 */ 648extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64); 649extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64); 650extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64); 651extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64); 652 653#define PAL_CALL(iprv,a0,a1,a2,a3) iprv = ia64_pal_call_static(a0, a1, a2, a3, 0) 654#define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) iprv = ia64_pal_call_static(a0, a1, a2, a3, 1) 655#define PAL_CALL_STK(iprv,a0,a1,a2,a3) iprv = ia64_pal_call_stacked(a0, a1, a2, a3) 656#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) iprv = ia64_pal_call_phys_static(a0, a1, a2, a3) 657#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3) 658 659typedef int (*ia64_pal_handler) (u64, ...); 660extern ia64_pal_handler ia64_pal; 661extern void ia64_pal_handler_init (void *); 662 663extern ia64_pal_handler ia64_pal; 664 665extern pal_cache_config_info_t l0d_cache_config_info; 666extern pal_cache_config_info_t l0i_cache_config_info; 667extern pal_cache_config_info_t l1_cache_config_info; 668extern pal_cache_config_info_t l2_cache_config_info; 669 670extern pal_cache_protection_info_t l0d_cache_protection_info; 671extern pal_cache_protection_info_t l0i_cache_protection_info; 672extern pal_cache_protection_info_t l1_cache_protection_info; 673extern pal_cache_protection_info_t l2_cache_protection_info; 674 675extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t, 676 pal_cache_type_t); 677 678extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t, 679 pal_cache_type_t); 680 681 682extern void pal_error(int); 683 684 685/* Useful wrappers for the current list of pal procedures */ 686 687typedef union pal_bus_features_u { 688 u64 pal_bus_features_val; 689 struct { 690 u64 pbf_reserved1 : 29; 691 u64 pbf_req_bus_parking : 1; 692 u64 pbf_bus_lock_mask : 1; 693 u64 pbf_enable_half_xfer_rate : 1; 694 u64 pbf_reserved2 : 22; 695 u64 pbf_disable_xaction_queueing : 1; 696 u64 pbf_disable_resp_err_check : 1; 697 u64 pbf_disable_berr_check : 1; 698 u64 pbf_disable_bus_req_internal_err_signal : 1; 699 u64 pbf_disable_bus_req_berr_signal : 1; 700 u64 pbf_disable_bus_init_event_check : 1; 701 u64 pbf_disable_bus_init_event_signal : 1; 702 u64 pbf_disable_bus_addr_err_check : 1; 703 u64 pbf_disable_bus_addr_err_signal : 1; 704 u64 pbf_disable_bus_data_err_check : 1; 705 } pal_bus_features_s; 706} pal_bus_features_u_t; 707 708extern void pal_bus_features_print (u64); 709 710/* Provide information about configurable processor bus features */ 711static inline s64 712ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail, 713 pal_bus_features_u_t *features_status, 714 pal_bus_features_u_t *features_control) 715{ 716 struct ia64_pal_retval iprv; 717 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0); 718 if (features_avail) 719 features_avail->pal_bus_features_val = iprv.v0; 720 if (features_status) 721 features_status->pal_bus_features_val = iprv.v1; 722 if (features_control) 723 features_control->pal_bus_features_val = iprv.v2; 724 return iprv.status; 725} 726 727/* Enables/disables specific processor bus features */ 728static inline s64 729ia64_pal_bus_set_features (pal_bus_features_u_t feature_select) 730{ 731 struct ia64_pal_retval iprv; 732 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0); 733 return iprv.status; 734} 735 736/* Get detailed cache information */ 737static inline s64 738ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf) 739{ 740 struct ia64_pal_retval iprv; 741 742 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0); 743 744 if (iprv.status == 0) { 745 conf->pcci_status = iprv.status; 746 conf->pcci_info_1.pcci1_data = iprv.v0; 747 conf->pcci_info_2.pcci2_data = iprv.v1; 748 conf->pcci_reserved = iprv.v2; 749 } 750 return iprv.status; 751 752} 753 754/* Get detailed cche protection information */ 755static inline s64 756ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot) 757{ 758 struct ia64_pal_retval iprv; 759 760 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0); 761 762 if (iprv.status == 0) { 763 prot->pcpi_status = iprv.status; 764 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; 765 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; 766 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; 767 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; 768 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; 769 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; 770 } 771 return iprv.status; 772} 773 774/* 775 * Flush the processor instruction or data caches. *PROGRESS must be 776 * initialized to zero before calling this for the first time.. 777 */ 778static inline s64 779ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) 780{ 781 struct ia64_pal_retval iprv; 782 PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); 783 if (vector) 784 *vector = iprv.v0; 785 *progress = iprv.v1; 786 return iprv.status; 787} 788 789 790/* Initialize the processor controlled caches */ 791static inline s64 792ia64_pal_cache_init (u64 level, u64 cache_type, u64 restrict) 793{ 794 struct ia64_pal_retval iprv; 795 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, restrict); 796 return iprv.status; 797} 798 799/* Initialize the tags and data of a data or unified cache line of 800 * processor controlled cache to known values without the availability 801 * of backing memory. 802 */ 803static inline s64 804ia64_pal_cache_line_init (u64 physical_addr, u64 data_value) 805{ 806 struct ia64_pal_retval iprv; 807 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0); 808 return iprv.status; 809} 810 811 812/* Read the data and tag of a processor controlled cache line for diags */ 813static inline s64 814ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) 815{ 816 struct ia64_pal_retval iprv; 817 PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0); 818 return iprv.status; 819} 820 821/* Return summary information about the heirarchy of caches controlled by the processor */ 822static inline s64 823ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches) 824{ 825 struct ia64_pal_retval iprv; 826 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0); 827 if (cache_levels) 828 *cache_levels = iprv.v0; 829 if (unique_caches) 830 *unique_caches = iprv.v1; 831 return iprv.status; 832} 833 834/* Write the data and tag of a processor-controlled cache line for diags */ 835static inline s64 836ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) 837{ 838 struct ia64_pal_retval iprv; 839 PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data); 840 return iprv.status; 841} 842 843 844/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */ 845static inline s64 846ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics, 847 u64 *buffer_size, u64 *buffer_align) 848{ 849 struct ia64_pal_retval iprv; 850 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics); 851 if (buffer_size) 852 *buffer_size = iprv.v0; 853 if (buffer_align) 854 *buffer_align = iprv.v1; 855 return iprv.status; 856} 857 858/* Copy relocatable PAL procedures from ROM to memory */ 859static inline s64 860ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) 861{ 862 struct ia64_pal_retval iprv; 863 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor); 864 if (pal_proc_offset) 865 *pal_proc_offset = iprv.v0; 866 return iprv.status; 867} 868 869/* Return the number of instruction and data debug register pairs */ 870static inline s64 871ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs) 872{ 873 struct ia64_pal_retval iprv; 874 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0); 875 if (inst_regs) 876 *inst_regs = iprv.v0; 877 if (data_regs) 878 *data_regs = iprv.v1; 879 880 return iprv.status; 881} 882 883#ifdef TBD 884/* Switch from IA64-system environment to IA-32 system environment */ 885static inline s64 886ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3) 887{ 888 struct ia64_pal_retval iprv; 889 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3); 890 return iprv.status; 891} 892#endif 893 894/* Get unique geographical address of this processor on its bus */ 895static inline s64 896ia64_pal_fixed_addr (u64 *global_unique_addr) 897{ 898 struct ia64_pal_retval iprv; 899 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0); 900 if (global_unique_addr) 901 *global_unique_addr = iprv.v0; 902 return iprv.status; 903} 904 905/* Get base frequency of the platform if generated by the processor */ 906static inline s64 907ia64_pal_freq_base (u64 *platform_base_freq) 908{ 909 struct ia64_pal_retval iprv; 910 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0); 911 if (platform_base_freq) 912 *platform_base_freq = iprv.v0; 913 return iprv.status; 914} 915 916/* 917 * Get the ratios for processor frequency, bus frequency and interval timer to 918 * to base frequency of the platform 919 */ 920static inline s64 921ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio, 922 struct pal_freq_ratio *itc_ratio) 923{ 924 struct ia64_pal_retval iprv; 925 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0); 926 if (proc_ratio) 927 *(u64 *)proc_ratio = iprv.v0; 928 if (bus_ratio) 929 *(u64 *)bus_ratio = iprv.v1; 930 if (itc_ratio) 931 *(u64 *)itc_ratio = iprv.v2; 932 return iprv.status; 933} 934 935/* Make the processor enter HALT or one of the implementation dependent low 936 * power states where prefetching and execution are suspended and cache and 937 * TLB coherency is not maintained. 938 */ 939static inline s64 940ia64_pal_halt (u64 halt_state) 941{ 942 struct ia64_pal_retval iprv; 943 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0); 944 return iprv.status; 945} 946 947typedef union pal_power_mgmt_info_u { 948 u64 ppmi_data; 949 struct { 950 u64 exit_latency : 16, 951 entry_latency : 16, 952 power_consumption : 28, 953 im : 1, 954 co : 1, 955 reserved : 2; 956 } pal_power_mgmt_info_s; 957} pal_power_mgmt_info_u_t; 958 959/* Return information about processor's optional power management capabilities. */ 960static inline s64 961ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) 962{ 963 struct ia64_pal_retval iprv; 964 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0); 965 return iprv.status; 966} 967 968/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are 969 * suspended, but cache and TLB coherency is maintained. 970 */ 971static inline s64 972ia64_pal_halt_light (void) 973{ 974 struct ia64_pal_retval iprv; 975 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0); 976 return iprv.status; 977} 978 979/* Clear all the processor error logging registers and reset the indicator that allows 980 * the error logging registers to be written. This procedure also checks the pending 981 * machine check bit and pending INIT bit and reports their states. 982 */ 983static inline s64 984ia64_pal_mc_clear_log (u64 *pending_vector) 985{ 986 struct ia64_pal_retval iprv; 987 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0); 988 if (pending_vector) 989 *pending_vector = iprv.v0; 990 return iprv.status; 991} 992 993/* Ensure that all outstanding transactions in a processor are completed or that any 994 * MCA due to thes outstanding transaction is taken. 995 */ 996static inline s64 997ia64_pal_mc_drain (void) 998{ 999 struct ia64_pal_retval iprv; 1000 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0); 1001 return iprv.status; 1002} 1003 1004/* Return the machine check dynamic processor state */ 1005static inline s64 1006ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds) 1007{ 1008 struct ia64_pal_retval iprv; 1009 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0); 1010 if (size) 1011 *size = iprv.v0; 1012 if (pds) 1013 *pds = iprv.v1; 1014 return iprv.status; 1015} 1016 1017/* Return processor machine check information */ 1018static inline s64 1019ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info) 1020{ 1021 struct ia64_pal_retval iprv; 1022 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0); 1023 if (size) 1024 *size = iprv.v0; 1025 if (error_info) 1026 *error_info = iprv.v1; 1027 return iprv.status; 1028} 1029 1030/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot 1031 * attempt to correct any expected machine checks. 1032 */ 1033static inline s64 1034ia64_pal_mc_expected (u64 expected, u64 *previous) 1035{ 1036 struct ia64_pal_retval iprv; 1037 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0); 1038 if (previous) 1039 *previous = iprv.v0; 1040 return iprv.status; 1041} 1042 1043/* Register a platform dependent location with PAL to which it can save 1044 * minimal processor state in the event of a machine check or initialization 1045 * event. 1046 */ 1047static inline s64 1048ia64_pal_mc_register_mem (u64 physical_addr) 1049{ 1050 struct ia64_pal_retval iprv; 1051 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0); 1052 return iprv.status; 1053} 1054 1055/* Restore minimal architectural processor state, set CMC interrupt if necessary 1056 * and resume execution 1057 */ 1058static inline s64 1059ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr) 1060{ 1061 struct ia64_pal_retval iprv; 1062 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0); 1063 return iprv.status; 1064} 1065 1066/* Return the memory attributes implemented by the processor */ 1067static inline s64 1068ia64_pal_mem_attrib (u64 *mem_attrib) 1069{ 1070 struct ia64_pal_retval iprv; 1071 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0); 1072 if (mem_attrib) 1073 *mem_attrib = iprv.v0 & 0xff; 1074 return iprv.status; 1075} 1076 1077/* Return the amount of memory needed for second phase of processor 1078 * self-test and the required alignment of memory. 1079 */ 1080static inline s64 1081ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment) 1082{ 1083 struct ia64_pal_retval iprv; 1084 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0); 1085 if (bytes_needed) 1086 *bytes_needed = iprv.v0; 1087 if (alignment) 1088 *alignment = iprv.v1; 1089 return iprv.status; 1090} 1091 1092typedef union pal_perf_mon_info_u { 1093 u64 ppmi_data; 1094 struct { 1095 u64 generic : 8, 1096 width : 8, 1097 cycles : 8, 1098 retired : 8, 1099 reserved : 32; 1100 } pal_perf_mon_info_s; 1101} pal_perf_mon_info_u_t; 1102 1103/* Return the performance monitor information about what can be counted 1104 * and how to configure the monitors to count the desired events. 1105 */ 1106static inline s64 1107ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info) 1108{ 1109 struct ia64_pal_retval iprv; 1110 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0); 1111 if (pm_info) 1112 pm_info->ppmi_data = iprv.v0; 1113 return iprv.status; 1114} 1115 1116/* Specifies the physical address of the processor interrupt block 1117 * and I/O port space. 1118 */ 1119static inline s64 1120ia64_pal_platform_addr (u64 type, u64 physical_addr) 1121{ 1122 struct ia64_pal_retval iprv; 1123 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0); 1124 return iprv.status; 1125} 1126 1127/* Set the SAL PMI entrypoint in memory */ 1128static inline s64 1129ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr) 1130{ 1131 struct ia64_pal_retval iprv; 1132 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0); 1133 return iprv.status; 1134} 1135 1136struct pal_features_s; 1137/* Provide information about configurable processor features */ 1138static inline s64 1139ia64_pal_proc_get_features (u64 *features_avail, 1140 u64 *features_status, 1141 u64 *features_control) 1142{ 1143 struct ia64_pal_retval iprv; 1144 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0); 1145 if (iprv.status == 0) { 1146 *features_avail = iprv.v0; 1147 *features_status = iprv.v1; 1148 *features_control = iprv.v2; 1149 } 1150 return iprv.status; 1151} 1152 1153/* Enable/disable processor dependent features */ 1154static inline s64 1155ia64_pal_proc_set_features (u64 feature_select) 1156{ 1157 struct ia64_pal_retval iprv; 1158 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0); 1159 return iprv.status; 1160} 1161 1162/* 1163 * Put everything in a struct so we avoid the global offset table whenever 1164 * possible. 1165 */ 1166typedef struct ia64_ptce_info_s { 1167 u64 base; 1168 u32 count[2]; 1169 u32 stride[2]; 1170} ia64_ptce_info_t; 1171 1172/* Return the information required for the architected loop used to purge 1173 * (initialize) the entire TC 1174 */ 1175static inline s64 1176ia64_get_ptce (ia64_ptce_info_t *ptce) 1177{ 1178 struct ia64_pal_retval iprv; 1179 1180 if (!ptce) 1181 return -1; 1182 1183 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0); 1184 if (iprv.status == 0) { 1185 ptce->base = iprv.v0; 1186 ptce->count[0] = iprv.v1 >> 32; 1187 ptce->count[1] = iprv.v1 & 0xffffffff; 1188 ptce->stride[0] = iprv.v2 >> 32; 1189 ptce->stride[1] = iprv.v2 & 0xffffffff; 1190 } 1191 return iprv.status; 1192} 1193 1194/* Return info about implemented application and control registers. */ 1195static inline s64 1196ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2) 1197{ 1198 struct ia64_pal_retval iprv; 1199 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0); 1200 if (reg_info_1) 1201 *reg_info_1 = iprv.v0; 1202 if (reg_info_2) 1203 *reg_info_2 = iprv.v1; 1204 return iprv.status; 1205} 1206 1207typedef union pal_hints_u { 1208 u64 ph_data; 1209 struct { 1210 u64 si : 1, 1211 li : 1, 1212 reserved : 62; 1213 } pal_hints_s; 1214} pal_hints_u_t; 1215 1216/* Return information about the register stack and RSE for this processor 1217 * implementation. 1218 */ 1219static inline s64 1220ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints) 1221{ 1222 struct ia64_pal_retval iprv; 1223 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0); 1224 if (num_phys_stacked) 1225 *num_phys_stacked = iprv.v0; 1226 if (hints) 1227 hints->ph_data = iprv.v1; 1228 return iprv.status; 1229} 1230 1231/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are 1232 * suspended, but cause cache and TLB coherency to be maintained. 1233 * This is usually called in IA-32 mode. 1234 */ 1235static inline s64 1236ia64_pal_shutdown (void) 1237{ 1238 struct ia64_pal_retval iprv; 1239 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0); 1240 return iprv.status; 1241} 1242 1243/* Perform the second phase of processor self-test. */ 1244static inline s64 1245ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state) 1246{ 1247 struct ia64_pal_retval iprv; 1248 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes); 1249 if (self_test_state) 1250 *self_test_state = iprv.v0; 1251 return iprv.status; 1252} 1253 1254typedef union pal_version_u { 1255 u64 pal_version_val; 1256 struct { 1257 u64 pv_pal_b_rev : 8; 1258 u64 pv_pal_b_model : 8; 1259 u64 pv_reserved1 : 8; 1260 u64 pv_pal_vendor : 8; 1261 u64 pv_pal_a_rev : 8; 1262 u64 pv_pal_a_model : 8; 1263 u64 pv_reserved2 : 16; 1264 } pal_version_s; 1265} pal_version_u_t; 1266 1267 1268/* Return PAL version information */ 1269static inline s64 1270ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version) 1271{ 1272 struct ia64_pal_retval iprv; 1273 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0); 1274 if (pal_min_version) 1275 pal_min_version->pal_version_val = iprv.v0; 1276 1277 if (pal_cur_version) 1278 pal_cur_version->pal_version_val = iprv.v1; 1279 1280 return iprv.status; 1281} 1282 1283typedef union pal_tc_info_u { 1284 u64 pti_val; 1285 struct { 1286 u64 num_sets : 8, 1287 associativity : 8, 1288 num_entries : 16, 1289 pf : 1, 1290 unified : 1, 1291 reduce_tr : 1, 1292 reserved : 29; 1293 } pal_tc_info_s; 1294} pal_tc_info_u_t; 1295 1296#define tc_reduce_tr pal_tc_info_s.reduce_tr 1297#define tc_unified pal_tc_info_s.unified 1298#define tc_pf pal_tc_info_s.pf 1299#define tc_num_entries pal_tc_info_s.num_entries 1300#define tc_associativity pal_tc_info_s.associativity 1301#define tc_num_sets pal_tc_info_s.num_sets 1302 1303 1304/* Return information about the virtual memory characteristics of the processor 1305 * implementation. 1306 */ 1307static inline s64 1308ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages) 1309{ 1310 struct ia64_pal_retval iprv; 1311 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0); 1312 if (tc_info) 1313 tc_info->pti_val = iprv.v0; 1314 if (tc_pages) 1315 *tc_pages = iprv.v1; 1316 return iprv.status; 1317} 1318 1319/* Get page size information about the virtual memory characteristics of the processor 1320 * implementation. 1321 */ 1322static inline s64 1323ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages) 1324{ 1325 struct ia64_pal_retval iprv; 1326 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0); 1327 if (tr_pages) 1328 *tr_pages = iprv.v0; 1329 if (vw_pages) 1330 *vw_pages = iprv.v1; 1331 return iprv.status; 1332} 1333 1334typedef union pal_vm_info_1_u { 1335 u64 pvi1_val; 1336 struct { 1337 u64 vw : 1, 1338 phys_add_size : 7, 1339 key_size : 8, 1340 max_pkr : 8, 1341 hash_tag_id : 8, 1342 max_dtr_entry : 8, 1343 max_itr_entry : 8, 1344 max_unique_tcs : 8, 1345 num_tc_levels : 8; 1346 } pal_vm_info_1_s; 1347} pal_vm_info_1_u_t; 1348 1349typedef union pal_vm_info_2_u { 1350 u64 pvi2_val; 1351 struct { 1352 u64 impl_va_msb : 8, 1353 rid_size : 8, 1354 reserved : 48; 1355 } pal_vm_info_2_s; 1356} pal_vm_info_2_u_t; 1357 1358/* Get summary information about the virtual memory characteristics of the processor 1359 * implementation. 1360 */ 1361static inline s64 1362ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2) 1363{ 1364 struct ia64_pal_retval iprv; 1365 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0); 1366 if (vm_info_1) 1367 vm_info_1->pvi1_val = iprv.v0; 1368 if (vm_info_2) 1369 vm_info_2->pvi2_val = iprv.v1; 1370 return iprv.status; 1371} 1372 1373typedef union pal_itr_valid_u { 1374 u64 piv_val; 1375 struct { 1376 u64 access_rights_valid : 1, 1377 priv_level_valid : 1, 1378 dirty_bit_valid : 1, 1379 mem_attr_valid : 1, 1380 reserved : 60; 1381 } pal_tr_valid_s; 1382} pal_tr_valid_u_t; 1383 1384/* Read a translation register */ 1385static inline s64 1386ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid) 1387{ 1388 struct ia64_pal_retval iprv; 1389 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)__pa(tr_buffer)); 1390 if (tr_valid) 1391 tr_valid->piv_val = iprv.v0; 1392 return iprv.status; 1393} 1394 1395static inline s64 1396ia64_pal_prefetch_visibility (void) 1397{ 1398 struct ia64_pal_retval iprv; 1399 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, 0, 0, 0); 1400 return iprv.status; 1401} 1402 1403#endif /* __ASSEMBLY__ */ 1404 1405#endif /* _ASM_IA64_PAL_H */ 1406