1#include <linux/config.h>
2#ifndef __I386_COBALT_H
3#define __I386_COBALT_H
4
5/*
6 * Cobalt is the system ASIC on the SGI 320 and 540 Visual Workstations
7 */
8
9#define	CO_CPU_PHYS		0xc2000000
10#define	CO_APIC_PHYS		0xc4000000
11
12/* see set_fixmap() and asm/fixmap.h */
13#define	CO_CPU_VADDR		(fix_to_virt(FIX_CO_CPU))
14#define	CO_APIC_VADDR		(fix_to_virt(FIX_CO_APIC))
15
16/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
17#define	CO_CPU_REV		0x08
18#define	CO_CPU_CTRL		0x10
19#define	CO_CPU_STAT		0x20
20#define	CO_CPU_TIMEVAL		0x30
21
22/* CO_CPU_CTRL bits */
23#define	CO_CTRL_TIMERUN		0x04	/* 0 == disabled */
24#define	CO_CTRL_TIMEMASK	0x08	/* 0 == unmasked */
25
26/* CO_CPU_STATUS bits */
27#define	CO_STAT_TIMEINTR	0x02	/* (r) 1 == int pend, (w) 0 == clear */
28
29/* CO_CPU_TIMEVAL value */
30#define	CO_TIME_HZ		100000000 /* Cobalt core rate */
31
32/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
33#define	CO_APIC_HI(n)		(((n) * 0x10) + 4)
34#define	CO_APIC_LO(n)		((n) * 0x10)
35#define	CO_APIC_ID		0x0ffc
36
37/* CO_APIC_ID bits */
38#define	CO_APIC_ENABLE		0x00000100
39
40/* CO_APIC_LO bits */
41#define	CO_APIC_LEVEL		0x08000		/* 0 = edge */
42
43/*
44 * Where things are physically wired to Cobalt
45 * #defines with no board _<type>_<rev>_ are common to all (thus far)
46 */
47#define CO_APIC_0_5_IDE0	5
48#define	CO_APIC_0_5_SERIAL	13
49#define CO_APIC_0_5_PARLL	4
50#define CO_APIC_0_5_FLOPPY	6
51
52#define	CO_APIC_0_6_IDE0	4
53#define	CO_APIC_0_6_USB	7	/* PIIX4 USB */
54
55#define	CO_APIC_1_2_IDE0	4
56
57#define CO_APIC_0_5_IDE1	2
58#define CO_APIC_0_6_IDE1	2
59
60#define	CO_APIC_IDE0	CO_APIC_0_5_IDE0
61#define	CO_APIC_IDE1	CO_APIC_0_5_IDE1
62#define	CO_APIC_SERIAL	CO_APIC_0_5_SERIAL
63
64#define CO_APIC_ENET	3	/* Lithium PCI Bridge A, Device 3 */
65#define	CO_APIC_8259	12	/* serial, floppy, par-l-l, audio */
66
67#define	CO_APIC_VIDOUT0	16
68#define	CO_APIC_VIDOUT1	17
69#define	CO_APIC_VIDIN0	18
70#define	CO_APIC_VIDIN1	19
71
72#define CO_APIC_CPU	28	/* Timer and Cache interrupt */
73
74/*
75 * This is the "irq" arg to request_irq(), just a unique cookie.
76 */
77#define	CO_IRQ_TIMER	0
78#define CO_IRQ_ENET	3
79#define CO_IRQ_SERIAL	4
80#define CO_IRQ_FLOPPY	6	/* Same as drivers/block/floppy.c:FLOPPY_IRQ */
81#define	CO_IRQ_PARLL	7
82#define	CO_IRQ_POWER	9
83#define CO_IRQ_IDE	14
84#define	CO_IRQ_8259	12
85
86#ifdef CONFIG_X86_VISWS_APIC
87static __inline void co_cpu_write(unsigned long reg, unsigned long v)
88{
89	*((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
90}
91
92static __inline unsigned long co_cpu_read(unsigned long reg)
93{
94	return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
95}
96
97static __inline void co_apic_write(unsigned long reg, unsigned long v)
98{
99	*((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
100}
101
102static __inline unsigned long co_apic_read(unsigned long reg)
103{
104	return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
105}
106#endif
107
108extern char visws_board_type;
109
110#define	VISWS_320	0
111#define	VISWS_540	1
112
113extern char visws_board_rev;
114
115#endif
116