1/* 2 * linux/include/asm-arm/arch-shark/irq.h 3 * 4 * by Alexander Schulz 5 * 6 * derived from linux/arch/ppc/kernel/i8259.c and: 7 * include/asm-arm/arch-ebsa110/irq.h 8 * Copyright (C) 1996-1998 Russell King 9 */ 10 11#include <asm/io.h> 12#define fixup_irq(x) (x) 13 14/* 15 * 8259A PIC functions to handle ISA devices: 16 */ 17 18/* 19 * This contains the irq mask for both 8259A irq controllers, 20 * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb) 21 */ 22static unsigned char cached_irq_mask[2] = { 0xfb, 0xff }; 23 24/* 25 * These have to be protected by the irq controller spinlock 26 * before being called. 27 */ 28static void shark_disable_8259A_irq(unsigned int irq) 29{ 30 unsigned int mask; 31 if (irq<8) { 32 mask = 1 << irq; 33 cached_irq_mask[0] |= mask; 34 } else { 35 mask = 1 << (irq-8); 36 cached_irq_mask[1] |= mask; 37 } 38 outb(cached_irq_mask[1],0xA1); 39 outb(cached_irq_mask[0],0x21); 40} 41 42static void shark_enable_8259A_irq(unsigned int irq) 43{ 44 unsigned int mask; 45 if (irq<8) { 46 mask = ~(1 << irq); 47 cached_irq_mask[0] &= mask; 48 } else { 49 mask = ~(1 << (irq-8)); 50 cached_irq_mask[1] &= mask; 51 } 52 outb(cached_irq_mask[1],0xA1); 53 outb(cached_irq_mask[0],0x21); 54} 55 56/* 57 * Careful! The 8259A is a fragile beast, it pretty 58 * much _has_ to be done exactly like this (mask it 59 * first, _then_ send the EOI, and the order of EOI 60 * to the two 8259s is important! 61 */ 62static void shark_mask_and_ack_8259A_irq(unsigned int irq) 63{ 64 if (irq & 8) { 65 cached_irq_mask[1] |= 1 << (irq-8); 66 inb(0xA1); /* DUMMY */ 67 outb(cached_irq_mask[1],0xA1); 68 } else { 69 cached_irq_mask[0] |= 1 << irq; 70 outb(cached_irq_mask[0],0x21); 71 } 72} 73 74static void bogus_int(int irq, void *dev_id, struct pt_regs *regs) 75{ 76 printk("Got interrupt %i!\n",irq); 77} 78 79static struct irqaction cascade; 80 81static __inline__ void irq_init_irq(void) 82{ 83 int irq; 84 85 for (irq = 0; irq < NR_IRQS; irq++) { 86 irq_desc[irq].valid = 1; 87 irq_desc[irq].probe_ok = 1; 88 irq_desc[irq].mask_ack = shark_mask_and_ack_8259A_irq; 89 irq_desc[irq].mask = shark_disable_8259A_irq; 90 irq_desc[irq].unmask = shark_enable_8259A_irq; 91 } 92 93 /* The PICs are initialized to level triggered and auto eoi! 94 * If they are set to edge triggered they lose some IRQs, 95 * if they are set to manual eoi they get locked up after 96 * a short time 97 */ 98 99 /* init master interrupt controller */ 100 outb(0x19, 0x20); /* Start init sequence, level triggered */ 101 outb(0x00, 0x21); /* Vector base */ 102 outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */ 103 outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/ 104 outb(0x0A, 0x20); 105 /* init slave interrupt controller */ 106 outb(0x19, 0xA0); /* Start init sequence, level triggered */ 107 outb(0x08, 0xA1); /* Vector base */ 108 outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */ 109 outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */ 110 outb(0x0A, 0xA0); 111 outb(cached_irq_mask[1],0xA1); 112 outb(cached_irq_mask[0],0x21); 113 //request_region(0x20,0x2,"pic1"); 114 //request_region(0xA0,0x2,"pic2"); 115 116 cascade.handler = bogus_int; 117 cascade.flags = 0; 118 cascade.mask = 0; 119 cascade.name = "cascade"; 120 cascade.next = NULL; 121 cascade.dev_id = NULL; 122 setup_arm_irq(2,&cascade); 123 124} 125