1/* 2 * BK Id: SCCS/s.8xx_immap.h 1.5 05/17/01 18:14:24 cort 3 */ 4 5/* 6 * MPC8xx Internal Memory Map 7 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 8 * 9 * The I/O on the MPC860 is comprised of blocks of special registers 10 * and the dual port ram for the Communication Processor Module. 11 * Within this space are functional units such as the SIU, memory 12 * controller, system timers, and other control functions. It is 13 * a combination that I found difficult to separate into logical 14 * functional files.....but anyone else is welcome to try. -- Dan 15 */ 16#ifdef __KERNEL__ 17#ifndef __IMMAP_8XX__ 18#define __IMMAP_8XX__ 19 20/* System configuration registers. 21*/ 22typedef struct sys_conf { 23 uint sc_siumcr; 24 uint sc_sypcr; 25 uint sc_swt; 26 char res1[2]; 27 ushort sc_swsr; 28 uint sc_sipend; 29 uint sc_simask; 30 uint sc_siel; 31 uint sc_sivec; 32 uint sc_tesr; 33 char res2[0xc]; 34 uint sc_sdcr; 35 char res3[0x4c]; 36} sysconf8xx_t; 37 38/* PCMCIA configuration registers. 39*/ 40typedef struct pcmcia_conf { 41 uint pcmc_pbr0; 42 uint pcmc_por0; 43 uint pcmc_pbr1; 44 uint pcmc_por1; 45 uint pcmc_pbr2; 46 uint pcmc_por2; 47 uint pcmc_pbr3; 48 uint pcmc_por3; 49 uint pcmc_pbr4; 50 uint pcmc_por4; 51 uint pcmc_pbr5; 52 uint pcmc_por5; 53 uint pcmc_pbr6; 54 uint pcmc_por6; 55 uint pcmc_pbr7; 56 uint pcmc_por7; 57 char res1[0x20]; 58 uint pcmc_pgcra; 59 uint pcmc_pgcrb; 60 uint pcmc_pscr; 61 char res2[4]; 62 uint pcmc_pipr; 63 char res3[4]; 64 uint pcmc_per; 65 char res4[4]; 66} pcmconf8xx_t; 67 68/* Memory controller registers. 69*/ 70typedef struct mem_ctlr { 71 uint memc_br0; 72 uint memc_or0; 73 uint memc_br1; 74 uint memc_or1; 75 uint memc_br2; 76 uint memc_or2; 77 uint memc_br3; 78 uint memc_or3; 79 uint memc_br4; 80 uint memc_or4; 81 uint memc_br5; 82 uint memc_or5; 83 uint memc_br6; 84 uint memc_or6; 85 uint memc_br7; 86 uint memc_or7; 87 char res1[0x24]; 88 uint memc_mar; 89 uint memc_mcr; 90 char res2[4]; 91 uint memc_mamr; 92 uint memc_mbmr; 93 ushort memc_mstat; 94 ushort memc_mptpr; 95 uint memc_mdr; 96 char res3[0x80]; 97} memctl8xx_t; 98 99/* System Integration Timers. 100*/ 101typedef struct sys_int_timers { 102 ushort sit_tbscr; 103 uint sit_tbreff0; 104 uint sit_tbreff1; 105 char res1[0x14]; 106 ushort sit_rtcsc; 107 uint sit_rtc; 108 uint sit_rtsec; 109 uint sit_rtcal; 110 char res2[0x10]; 111 ushort sit_piscr; 112 char res3[2]; 113 uint sit_pitc; 114 uint sit_pitr; 115 char res4[0x34]; 116} sit8xx_t; 117 118#define TBSCR_TBIRQ_MASK ((ushort)0xff00) 119#define TBSCR_REFA ((ushort)0x0080) 120#define TBSCR_REFB ((ushort)0x0040) 121#define TBSCR_REFAE ((ushort)0x0008) 122#define TBSCR_REFBE ((ushort)0x0004) 123#define TBSCR_TBF ((ushort)0x0002) 124#define TBSCR_TBE ((ushort)0x0001) 125 126#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) 127#define RTCSC_SEC ((ushort)0x0080) 128#define RTCSC_ALR ((ushort)0x0040) 129#define RTCSC_38K ((ushort)0x0010) 130#define RTCSC_SIE ((ushort)0x0008) 131#define RTCSC_ALE ((ushort)0x0004) 132#define RTCSC_RTF ((ushort)0x0002) 133#define RTCSC_RTE ((ushort)0x0001) 134 135#define PISCR_PIRQ_MASK ((ushort)0xff00) 136#define PISCR_PS ((ushort)0x0080) 137#define PISCR_PIE ((ushort)0x0004) 138#define PISCR_PTF ((ushort)0x0002) 139#define PISCR_PTE ((ushort)0x0001) 140 141/* Clocks and Reset. 142*/ 143typedef struct clk_and_reset { 144 uint car_sccr; 145 uint car_plprcr; 146 uint car_rsr; 147 char res[0x74]; /* Reserved area */ 148} car8xx_t; 149 150/* System Integration Timers keys. 151*/ 152typedef struct sitk { 153 uint sitk_tbscrk; 154 uint sitk_tbreff0k; 155 uint sitk_tbreff1k; 156 uint sitk_tbk; 157 char res1[0x10]; 158 uint sitk_rtcsck; 159 uint sitk_rtck; 160 uint sitk_rtseck; 161 uint sitk_rtcalk; 162 char res2[0x10]; 163 uint sitk_piscrk; 164 uint sitk_pitck; 165 char res3[0x38]; 166} sitk8xx_t; 167 168/* Clocks and reset keys. 169*/ 170typedef struct cark { 171 uint cark_sccrk; 172 uint cark_plprcrk; 173 uint cark_rsrk; 174 char res[0x474]; 175} cark8xx_t; 176 177/* The key to unlock registers maintained by keep-alive power. 178*/ 179#define KAPWR_KEY ((unsigned int)0x55ccaa33) 180 181/* LCD interface. MPC821 Only. 182*/ 183typedef struct lcd { 184 ushort lcd_lcolr[16]; 185 char res[0x20]; 186 uint lcd_lccr; 187 uint lcd_lchcr; 188 uint lcd_lcvcr; 189 char res2[4]; 190 uint lcd_lcfaa; 191 uint lcd_lcfba; 192 char lcd_lcsr; 193 char res3[0x7]; 194} lcd8xx_t; 195 196/* I2C 197*/ 198typedef struct i2c { 199 u_char i2c_i2mod; 200 char res1[3]; 201 u_char i2c_i2add; 202 char res2[3]; 203 u_char i2c_i2brg; 204 char res3[3]; 205 u_char i2c_i2com; 206 char res4[3]; 207 u_char i2c_i2cer; 208 char res5[3]; 209 u_char i2c_i2cmr; 210 char res6[0x8b]; 211} i2c8xx_t; 212 213/* DMA control/status registers. 214*/ 215typedef struct sdma_csr { 216 char res1[4]; 217 uint sdma_sdar; 218 u_char sdma_sdsr; 219 char res3[3]; 220 u_char sdma_sdmr; 221 char res4[3]; 222 u_char sdma_idsr1; 223 char res5[3]; 224 u_char sdma_idmr1; 225 char res6[3]; 226 u_char sdma_idsr2; 227 char res7[3]; 228 u_char sdma_idmr2; 229 char res8[0x13]; 230} sdma8xx_t; 231 232/* Communication Processor Module Interrupt Controller. 233*/ 234typedef struct cpm_ic { 235 ushort cpic_civr; 236 char res[0xe]; 237 uint cpic_cicr; 238 uint cpic_cipr; 239 uint cpic_cimr; 240 uint cpic_cisr; 241} cpic8xx_t; 242 243/* Input/Output Port control/status registers. 244*/ 245typedef struct io_port { 246 ushort iop_padir; 247 ushort iop_papar; 248 ushort iop_paodr; 249 ushort iop_padat; 250 char res1[8]; 251 ushort iop_pcdir; 252 ushort iop_pcpar; 253 ushort iop_pcso; 254 ushort iop_pcdat; 255 ushort iop_pcint; 256 char res2[6]; 257 ushort iop_pddir; 258 ushort iop_pdpar; 259 char res3[2]; 260 ushort iop_pddat; 261 char res4[8]; 262} iop8xx_t; 263 264/* Communication Processor Module Timers 265*/ 266typedef struct cpm_timers { 267 ushort cpmt_tgcr; 268 char res1[0xe]; 269 ushort cpmt_tmr1; 270 ushort cpmt_tmr2; 271 ushort cpmt_trr1; 272 ushort cpmt_trr2; 273 ushort cpmt_tcr1; 274 ushort cpmt_tcr2; 275 ushort cpmt_tcn1; 276 ushort cpmt_tcn2; 277 ushort cpmt_tmr3; 278 ushort cpmt_tmr4; 279 ushort cpmt_trr3; 280 ushort cpmt_trr4; 281 ushort cpmt_tcr3; 282 ushort cpmt_tcr4; 283 ushort cpmt_tcn3; 284 ushort cpmt_tcn4; 285 ushort cpmt_ter1; 286 ushort cpmt_ter2; 287 ushort cpmt_ter3; 288 ushort cpmt_ter4; 289 char res2[8]; 290} cpmtimer8xx_t; 291 292/* Finally, the Communication Processor stuff..... 293*/ 294typedef struct scc { /* Serial communication channels */ 295 uint scc_gsmrl; 296 uint scc_gsmrh; 297 ushort scc_pmsr; 298 char res1[2]; 299 ushort scc_todr; 300 ushort scc_dsr; 301 ushort scc_scce; 302 char res2[2]; 303 ushort scc_sccm; 304 char res3; 305 u_char scc_sccs; 306 char res4[8]; 307} scc_t; 308 309typedef struct smc { /* Serial management channels */ 310 char res1[2]; 311 ushort smc_smcmr; 312 char res2[2]; 313 u_char smc_smce; 314 char res3[3]; 315 u_char smc_smcm; 316 char res4[5]; 317} smc_t; 318 319/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but 320 * it fits within the address space. 321 */ 322typedef struct fec { 323 uint fec_addr_low; /* LS 32 bits of station address */ 324 ushort fec_addr_high; /* MS 16 bits of address */ 325 ushort res1; 326 uint fec_hash_table_high; 327 uint fec_hash_table_low; 328 uint fec_r_des_start; 329 uint fec_x_des_start; 330 uint fec_r_buff_size; 331 uint res2[9]; 332 uint fec_ecntrl; 333 uint fec_ievent; 334 uint fec_imask; 335 uint fec_ivec; 336 uint fec_r_des_active; 337 uint fec_x_des_active; 338 uint res3[10]; 339 uint fec_mii_data; 340 uint fec_mii_speed; 341 uint res4[17]; 342 uint fec_r_bound; 343 uint fec_r_fstart; 344 uint res5[6]; 345 uint fec_x_fstart; 346 uint res6[17]; 347 uint fec_fun_code; 348 uint res7[3]; 349 uint fec_r_cntrl; 350 uint fec_r_hash; 351 uint res8[14]; 352 uint fec_x_cntrl; 353 uint res9[0x1e]; 354} fec_t; 355 356typedef struct comm_proc { 357 /* General control and status registers. 358 */ 359 ushort cp_cpcr; 360 char res1[2]; 361 ushort cp_rccr; 362 char res2[6]; 363 ushort cp_cpmcr1; 364 ushort cp_cpmcr2; 365 ushort cp_cpmcr3; 366 ushort cp_cpmcr4; 367 char res3[2]; 368 ushort cp_rter; 369 char res4[2]; 370 ushort cp_rtmr; 371 char res5[0x14]; 372 373 /* Baud rate generators. 374 */ 375 uint cp_brgc1; 376 uint cp_brgc2; 377 uint cp_brgc3; 378 uint cp_brgc4; 379 380 /* Serial Communication Channels. 381 */ 382 scc_t cp_scc[4]; 383 384 /* Serial Management Channels. 385 */ 386 smc_t cp_smc[2]; 387 388 /* Serial Peripheral Interface. 389 */ 390 ushort cp_spmode; 391 char res6[4]; 392 u_char cp_spie; 393 char res7[3]; 394 u_char cp_spim; 395 char res8[2]; 396 u_char cp_spcom; 397 char res9[2]; 398 399 /* Parallel Interface Port. 400 */ 401 char res10[2]; 402 ushort cp_pipc; 403 char res11[2]; 404 ushort cp_ptpr; 405 uint cp_pbdir; 406 uint cp_pbpar; 407 char res12[2]; 408 ushort cp_pbodr; 409 uint cp_pbdat; 410 char res13[0x18]; 411 412 /* Serial Interface and Time Slot Assignment. 413 */ 414 uint cp_simode; 415 u_char cp_sigmr; 416 char res14; 417 u_char cp_sistr; 418 u_char cp_sicmr; 419 char res15[4]; 420 uint cp_sicr; 421 uint cp_sirp; 422 char res16[0x10c]; 423 u_char cp_siram[0x200]; 424 425 /* The fast ethernet controller is not really part of the CPM, 426 * but it resides in the address space. 427 */ 428 fec_t cp_fec; 429 char res18[0x1000]; 430 431 /* Dual Ported RAM follows. 432 * There are many different formats for this memory area 433 * depending upon the devices used and options chosen. 434 */ 435 u_char cp_dpmem[0x1000]; /* BD / Data / ucode */ 436 u_char res19[0xc00]; 437 u_char cp_dparam[0x400]; /* Parameter RAM */ 438} cpm8xx_t; 439 440/* Internal memory map. 441*/ 442typedef struct immap { 443 sysconf8xx_t im_siu_conf; /* SIU Configuration */ 444 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ 445 memctl8xx_t im_memctl; /* Memory Controller */ 446 sit8xx_t im_sit; /* System integration timers */ 447 car8xx_t im_clkrst; /* Clocks and reset */ 448 sitk8xx_t im_sitk; /* Sys int timer keys */ 449 cark8xx_t im_clkrstk; /* Clocks and reset keys */ 450 lcd8xx_t im_lcd; /* LCD (821 only) */ 451 i2c8xx_t im_i2c; /* I2C control/status */ 452 sdma8xx_t im_sdma; /* SDMA control/status */ 453 cpic8xx_t im_cpic; /* CPM Interrupt Controller */ 454 iop8xx_t im_ioport; /* IO Port control/status */ 455 cpmtimer8xx_t im_cpmtimer; /* CPM timers */ 456 cpm8xx_t im_cpm; /* Communication processor */ 457} immap_t; 458 459#endif /* __IMMAP_8XX__ */ 460#endif /* __KERNEL__ */ 461