1#ifndef __PARISC_SYSTEM_H 2#define __PARISC_SYSTEM_H 3 4#include <linux/config.h> 5#include <asm/psw.h> 6 7/* The program status word as bitfields. */ 8struct pa_psw { 9 unsigned int y:1; 10 unsigned int z:1; 11 unsigned int rv:2; 12 unsigned int w:1; 13 unsigned int e:1; 14 unsigned int s:1; 15 unsigned int t:1; 16 17 unsigned int h:1; 18 unsigned int l:1; 19 unsigned int n:1; 20 unsigned int x:1; 21 unsigned int b:1; 22 unsigned int c:1; 23 unsigned int v:1; 24 unsigned int m:1; 25 26 unsigned int cb:8; 27 28 unsigned int o:1; 29 unsigned int g:1; 30 unsigned int f:1; 31 unsigned int r:1; 32 unsigned int q:1; 33 unsigned int p:1; 34 unsigned int d:1; 35 unsigned int i:1; 36}; 37 38#ifdef __LP64__ 39#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4)) 40#else 41#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW)) 42#endif 43 44struct task_struct; 45 46extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *); 47 48#define prepare_to_switch() do { } while(0) 49#define switch_to(prev, next, last) do { \ 50 (last) = _switch_to(prev, next); \ 51} while(0) 52 53 54 55/* interrupt control */ 56#define __save_flags(x) __asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory") 57#define __restore_flags(x) __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory") 58#define __cli() __asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" ) 59#define __sti() __asm__ __volatile__("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory" ) 60 61#define local_irq_save(x) \ 62 __asm__ __volatile__("rsm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" ) 63#define local_irq_set(x) \ 64 __asm__ __volatile__("ssm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" ) 65#define local_irq_restore(x) \ 66 __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory" ) 67#define local_irq_disable() __cli() 68#define local_irq_enable() __sti() 69 70#ifdef CONFIG_SMP 71extern void __global_cli(void); 72extern void __global_sti(void); 73extern unsigned long __global_save_flags(void); 74extern void __global_restore_flags(unsigned long); 75 76#define cli() __global_cli() 77#define sti() __global_sti() 78#define save_flags(x) ((x)=__global_save_flags()) 79#define restore_flags(x) __global_restore_flags(x) 80 81#else 82 83#define cli() __cli() 84#define sti() __sti() 85#define save_flags(x) __save_flags(x) 86#define restore_flags(x) __restore_flags(x) 87 88#endif 89 90 91#define mfctl(reg) ({ \ 92 unsigned long cr; \ 93 __asm__ __volatile__( \ 94 "mfctl " #reg ",%0" : \ 95 "=r" (cr) \ 96 ); \ 97 cr; \ 98}) 99 100#define mtctl(gr, cr) \ 101 __asm__ __volatile__("mtctl %0,%1" \ 102 : /* no outputs */ \ 103 : "r" (gr), "i" (cr)) 104 105/* these are here to de-mystefy the calling code, and to provide hooks */ 106/* which I needed for debugging EIEM problems -PB */ 107#define get_eiem() mfctl(15) 108static inline void set_eiem(unsigned long val) 109{ 110 mtctl(val, 15); 111} 112 113#define mfsp(reg) ({ \ 114 unsigned long cr; \ 115 __asm__ __volatile__( \ 116 "mfsp " #reg ",%0" : \ 117 "=r" (cr) \ 118 ); \ 119 cr; \ 120}) 121 122#define mtsp(gr, cr) \ 123 __asm__ __volatile__("mtsp %0,%1" \ 124 : /* no outputs */ \ 125 : "r" (gr), "i" (cr)) 126 127 128/* 129** This is simply the barrier() macro from linux/kernel.h but when serial.c 130** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h 131** hasn't yet been included yet so it fails, thus repeating the macro here. 132** 133** PA-RISC architecture allows for weakly ordered memory accesses although 134** none of the processors use it. There is a strong ordered bit that is 135** set in the O-bit of the page directory entry. Operating systems that 136** can not tolerate out of order accesses should set this bit when mapping 137** pages. The O-bit of the PSW should also be set to 1 (I don't believe any 138** of the processor implemented the PSW O-bit). The PCX-W ERS states that 139** the TLB O-bit is not implemented so the page directory does not need to 140** have the O-bit set when mapping pages (section 3.1). This section also 141** states that the PSW Y, Z, G, and O bits are not implemented. 142** So it looks like nothing needs to be done for parisc-linux (yet). 143** (thanks to chada for the above comment -ggg) 144** 145** The __asm__ op below simple prevents gcc/ld from reordering 146** instructions across the mb() "call". 147*/ 148#define mb() __asm__ __volatile__("":::"memory"); /* barrier() */ 149#define rmb() mb() 150#define wmb() mb() 151#define smp_mb() mb() 152#define smp_wmb() mb() 153 154#define set_mb(var, value) do { var = value; mb(); } while (0) 155 156 157/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */ 158#define __ldcw(a) ({ \ 159 unsigned __ret; \ 160 __asm__ __volatile__("ldcw 0(%1),%0" : "=r" (__ret) : "r" (a)); \ 161 __ret; \ 162}) 163 164 165#ifdef CONFIG_SMP 166/* 167 * Your basic SMP spinlocks, allowing only a single CPU anywhere 168 */ 169 170typedef struct { 171 volatile unsigned int __attribute__((aligned(16))) lock; 172} spinlock_t; 173#endif 174 175#endif 176