1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * sgint23.h: Defines for the SGI INT2 and INT3 chipsets. 7 * 8 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 9 * Copyright (C) 1997, 98, 1999, 2000 Ralf Baechle 10 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - INT2 corrections 11 * Copyright (C) 2001 Ladislav Michl (ladis@psi.cz) 12 */ 13#ifndef _ASM_SGI_SGINT23_H 14#define _ASM_SGI_SGINT23_H 15 16/* These are the virtual IRQ numbers, we divide all IRQ's into 17 * 'spaces', the 'space' determines where and how to enable/disable 18 * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups 19 * are not supported this way. Driver is supposed to allocate HPC/MC 20 * interrupt as shareable and then look to proper status bit (see 21 * HAL2 driver). This will prevent many complications, trust me ;-) 22 * --ladis 23 */ 24#define SGINT_EISA 0 /* INDIGO 2 has 16 EISA irq levels */ 25#define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */ 26#define SGINT_LOCAL0 24 /* INDY has 8 local0 irq levels */ 27#define SGINT_LOCAL1 32 /* INDY has 8 local1 irq levels */ 28#define SGINT_LOCAL2 40 /* INDY has 8 local2 vectored irq levels */ 29#define SGINT_LOCAL3 48 /* INDY has 8 local3 vectored irq levels */ 30#define SGINT_END 56 /* End of 'spaces' */ 31 32/* 33 * Individual interrupt definitions for the INDY and Indigo2 34 */ 35 36#define SGI_SOFT_0_IRQ SGINT_CPU + 0 37#define SGI_SOFT_1_IRQ SGINT_CPU + 1 38#define SGI_LOCAL_0_IRQ SGINT_CPU + 2 39#define SGI_LOCAL_1_IRQ SGINT_CPU + 3 40#define SGI_8254_0_IRQ SGINT_CPU + 4 41#define SGI_8254_1_IRQ SGINT_CPU + 5 42#define SGI_BUSERR_IRQ SGINT_CPU + 6 43#define SGI_TIMER_IRQ SGINT_CPU + 7 44 45#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */ 46#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */ 47#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ 48#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ 49#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ 50#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */ 51#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */ 52#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */ 53#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */ 54 55#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */ 56#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ 57#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */ 58#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */ 59#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */ 60#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */ 61#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */ 62#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */ 63 64/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 65 * We map them to 0 */ 66#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */ 67#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ 68#define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ 69#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ 70 71/* INT2 occupies HPC PBUS slot 4, INT3 uses slot 6. */ 72#define SGI_INT2_BASE 0x1fbd9000 /* physical */ 73#define SGI_INT3_BASE 0x1fbd9880 /* physical */ 74 75struct sgi_ioc_ints { 76#ifdef __MIPSEB__ 77 unsigned char _unused0[3]; 78 volatile unsigned char istat0; /* Interrupt status zero */ 79#else 80 volatile unsigned char istat0; /* Interrupt status zero */ 81 unsigned char _unused0[3]; 82#endif 83#define ISTAT0_FFULL 0x01 84#define ISTAT0_SCSI0 0x02 85#define ISTAT0_SCSI1 0x04 86#define ISTAT0_ENET 0x08 87#define ISTAT0_GFXDMA 0x10 88#define ISTAT0_LPR 0x20 89#define ISTAT0_HPC2 0x40 90#define ISTAT0_LIO2 0x80 91 92#ifdef __MIPSEB__ 93 unsigned char _unused1[3]; 94 volatile unsigned char imask0; /* Interrupt mask zero */ 95 unsigned char _unused2[3]; 96 volatile unsigned char istat1; /* Interrupt status one */ 97#else 98 volatile unsigned char imask0; /* Interrupt mask zero */ 99 unsigned char _unused1[3]; 100 volatile unsigned char istat1; /* Interrupt status one */ 101 unsigned char _unused2[3]; 102#endif 103#define ISTAT1_ISDNI 0x01 104#define ISTAT1_PWR 0x02 105#define ISTAT1_ISDNH 0x04 106#define ISTAT1_LIO3 0x08 107#define ISTAT1_HPC3 0x10 108#define ISTAT1_AFAIL 0x20 109#define ISTAT1_VIDEO 0x40 110#define ISTAT1_GIO2 0x80 111 112#ifdef __MIPSEB__ 113 unsigned char _unused3[3]; 114 volatile unsigned char imask1; /* Interrupt mask one */ 115 unsigned char _unused4[3]; 116 volatile unsigned char vmeistat; /* VME interrupt status */ 117 unsigned char _unused5[3]; 118 volatile unsigned char cmeimask0; /* VME interrupt mask zero */ 119 unsigned char _unused6[3]; 120 volatile unsigned char cmeimask1; /* VME interrupt mask one */ 121 unsigned char _unused7[3]; 122 volatile unsigned char cmepol; /* VME polarity */ 123#else 124 volatile unsigned char imask1; /* Interrupt mask one */ 125 unsigned char _unused3[3]; 126 volatile unsigned char vmeistat; /* VME interrupt status */ 127 unsigned char _unused4[3]; 128 volatile unsigned char cmeimask0; /* VME interrupt mask zero */ 129 unsigned char _unused5[3]; 130 volatile unsigned char cmeimask1; /* VME interrupt mask one */ 131 unsigned char _unused6[3]; 132 volatile unsigned char cmepol; /* VME polarity */ 133 unsigned char _unused7[3]; 134#endif 135}; 136 137struct sgi_ioc_timers { 138#ifdef __MIPSEB__ 139 unsigned char _unused0[3]; 140 volatile unsigned char tcnt0; /* counter 0 */ 141 unsigned char _unused1[3]; 142 volatile unsigned char tcnt1; /* counter 1 */ 143 unsigned char _unused2[3]; 144 volatile unsigned char tcnt2; /* counter 2 */ 145 unsigned char _unused3[3]; 146 volatile unsigned char tcword; /* control word */ 147#else 148 volatile unsigned char tcnt0; /* counter 0 */ 149 unsigned char _unused0[3]; 150 volatile unsigned char tcnt1; /* counter 1 */ 151 unsigned char _unused1[3]; 152 volatile unsigned char tcnt2; /* counter 2 */ 153 unsigned char _unused2[3]; 154 volatile unsigned char tcword; /* control word */ 155 unsigned char _unused3[3]; 156#endif 157}; 158 159/* Timer control word bits. */ 160#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */ 161#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */ 162#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */ 163#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */ 164#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */ 165#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */ 166#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */ 167#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */ 168#define SGINT_TCWORD_CMASK 0x30 /* Command mask */ 169#define SGINT_TCWORD_CLAT 0x00 /* Latch command */ 170#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */ 171#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */ 172#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */ 173#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */ 174#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */ 175#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */ 176#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */ 177 178#define SGINT_TCSAMP_COUNTER 10255 179 180struct sgi_int2_regs { 181 struct sgi_ioc_ints ints; 182 183 volatile u32 ledbits; /* LED control bits */ 184#define INT2_LED_TXCLK 0x01 /* GPI to TXCLK enable */ 185#define INT2_LED_SERSLCT0 0x02 /* serial port0: 0=apple 1=pc */ 186#define INT2_LED_SERSLCT1 0x04 /* serial port1: 0=apple 1=pc */ 187#define INT2_LED_CHEAPER 0x08 /* 0=cheapernet 1=ethernet */ 188#define INT2_LED_POWEROFF 0x10 /* Power-off request, active high */ 189 190#ifdef __MIPSEB__ 191 unsigned char _unused0[3]; 192 volatile unsigned char tclear; /* Timer clear strobe address */ 193#else 194 volatile unsigned char tclear; /* Timer clear strobe address */ 195 unsigned char _unused0[3]; 196#endif 197#define INT2_TCLEAR_T0CLR 0x1 /* Clear timer0 IRQ */ 198#define INT2_TCLEAR_T1CLR 0x2 /* Clear timer1 IRQ */ 199/* I am guesing there are only two unused registers here 200 * but I could be wrong... - andrewb 201 */ 202/* u32 _unused[3]; */ 203 u32 _unused[2]; 204 struct sgi_ioc_timers timers; 205}; 206 207struct sgi_int3_regs { 208 struct sgi_ioc_ints ints; 209 210#ifdef __MIPSEB__ 211 unsigned char _unused0[3]; 212 volatile unsigned char tclear; /* Timer clear strobe address */ 213#else 214 volatile unsigned char tclear; /* Timer clear strobe address */ 215 unsigned char _unused0[3]; 216#endif 217 volatile u32 estatus; /* Error status reg */ 218 u32 _unused1[2]; 219 struct sgi_ioc_timers timers; 220}; 221 222extern struct sgi_int2_regs *sgi_i2regs; 223extern struct sgi_int3_regs *sgi_i3regs; 224extern struct sgi_ioc_ints *ioc_icontrol; 225extern struct sgi_ioc_timers *ioc_timers; 226extern volatile unsigned char *ioc_tclear; 227 228#endif /* _ASM_SGI_SGINT23_H */ 229