1/* 2 * sgihpc.h: Various HPC I/O controller defines. The HPC is basically 3 * the approximate functional equivalent of the Sun SYSIO 4 * on SGI INDY machines. 5 * 6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 7 * Copyright (C) 1998 Ralf Baechle (ralf@gnu.org) 8 */ 9#ifndef __ASM_SGI_SGIHPC_H 10#define __ASM_SGI_SGIHPC_H 11 12#include <linux/types.h> 13#include <asm/page.h> 14 15extern int sgi_has_ioc2; /* to know if we have older ioc1 or ioc2. */ 16extern int sgi_guiness; /* GUINESS or FULLHOUSE machine. */ 17extern int sgi_boardid; /* Board revision. */ 18 19/* An HPC dma descriptor. */ 20struct hpc_dma_desc { 21 u32 pbuf; /* physical address of data buffer */ 22 u32 cntinfo; /* counter and info bits */ 23#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */ 24#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */ 25#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */ 26#define HPCDMA_EORP 0x40000000 /* end of packet for rx */ 27#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */ 28#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */ 29#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */ 30#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */ 31#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */ 32#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */ 33 34 u32 pnext; /* paddr of next hpc_dma_desc if any */ 35}; 36 37typedef volatile u32 hpcreg; 38 39/* HPC1 stuff. */ 40 41/* HPC3 stuff. */ 42 43/* The set of regs for each HPC3 pbus dma channel. */ 44struct hpc3_pbus_dmacregs { 45 hpcreg pbdma_bptr; /* pbus dma channel buffer ptr */ 46 hpcreg pbdma_dptr; /* pbus dma channel desc ptr */ 47 char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */ 48 hpcreg pbdma_ctrl; /* pbus dma channel control register has 49 * copletely different meaning for read 50 * compared with write */ 51 /* read */ 52#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */ 53#define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */ 54 /* write */ 55#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */ 56#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */ 57#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */ 58#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */ 59#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */ 60#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */ 61#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */ 62#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */ 63#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */ 64 65 char _unused2[PAGE_SIZE - (sizeof(hpcreg))]; /* padding */ 66}; 67 68/* The HPC3 scsi registers, this does not include external ones. */ 69struct hpc3_scsiregs { 70 hpcreg cbptr; /* current dma buffer ptr, diagnostic use only */ 71 hpcreg ndptr; /* next dma descriptor ptr */ 72 char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */ 73 hpcreg bcd; /* byte count info */ 74#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */ 75#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */ 76#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */ 77 78 hpcreg ctrl; /* control register */ 79#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ 80#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */ 81#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */ 82#define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */ 83#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */ 84#define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */ 85#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */ 86#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */ 87 88 hpcreg gfptr; /* current GIO fifo ptr */ 89 hpcreg dfptr; /* current device fifo ptr */ 90 hpcreg dconfig; /* DMA configuration register */ 91#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */ 92#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */ 93#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */ 94#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */ 95#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */ 96#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */ 97#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */ 98#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */ 99#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */ 100#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */ 101 102 hpcreg pconfig; /* PIO configuration register */ 103#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */ 104#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */ 105#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */ 106#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */ 107#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */ 108#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */ 109#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */ 110#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */ 111 112 char _unused2[PAGE_SIZE - (6 * sizeof(hpcreg))]; /* padding */ 113}; 114 115/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */ 116struct hpc3_ethregs { 117 /* Receiver registers. */ 118 hpcreg rx_cbptr; /* current dma buffer ptr, diagnostic use only */ 119 hpcreg rx_ndptr; /* next dma descriptor ptr */ 120 char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */ 121 hpcreg rx_bcd; /* byte count info */ 122#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */ 123#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */ 124#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */ 125 126 hpcreg rx_ctrl; /* control register */ 127#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */ 128#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */ 129#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */ 130#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */ 131#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */ 132#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */ 133#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */ 134 135 hpcreg rx_gfptr; /* current GIO fifo ptr */ 136 hpcreg rx_dfptr; /* current device fifo ptr */ 137 hpcreg _unused2; /* padding */ 138 hpcreg rx_reset; /* reset register */ 139#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */ 140#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */ 141#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ 142 143 hpcreg rx_dconfig; /* DMA configuration register */ 144#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ 145#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ 146#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ 147#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ 148#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ 149#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ 150#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ 151#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */ 152 153 hpcreg rx_pconfig; /* PIO configuration register */ 154#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ 155#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ 156#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ 157#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ 158 159 char _unused3[PAGE_SIZE - (8 * sizeof(hpcreg))]; /* padding */ 160 161 /* Transmitter registers. */ 162 hpcreg tx_cbptr; /* current dma buffer ptr, diagnostic use only */ 163 hpcreg tx_ndptr; /* next dma descriptor ptr */ 164 char _unused4[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */ 165 hpcreg tx_bcd; /* byte count info */ 166#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */ 167#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */ 168#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */ 169#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */ 170#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */ 171 172 hpcreg tx_ctrl; /* control register */ 173#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */ 174#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */ 175#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */ 176#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* Dma channel endian mode, 1=little 0=big */ 177#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */ 178#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */ 179 180 hpcreg tx_gfptr; /* current GIO fifo ptr */ 181 hpcreg tx_dfptr; /* current device fifo ptr */ 182 char _unused5[PAGE_SIZE - (4 * sizeof(hpcreg))]; /* padding */ 183}; 184 185struct hpc3_regs { 186 /* First regs for the PBUS 8 dma channels. */ 187 struct hpc3_pbus_dmacregs pbdma[8]; 188 189 /* Now the HPC scsi registers, we get two scsi reg sets. */ 190 struct hpc3_scsiregs scsi_chan0, scsi_chan1; 191 192 /* The SEEQ hpc3 ethernet dma/control registers. */ 193 struct hpc3_ethregs ethregs; 194 195 /* Here are where the hpc3 fifo's can be directly accessed 196 * via PIO accesses. Under normal operation we never stick 197 * our grubby paws in here so it's just padding. 198 */ 199 char _unused1[PAGE_SIZE * 24]; 200 201 /* HPC3 irq status regs. Due to a peculiar bug you need to 202 * look at two different register addresses to get at all of 203 * the status bits. The first reg can only reliably report 204 * bits 4:0 of the status, and the second reg can only 205 * reliably report bits 9:5 of the hpc3 irq status. I told 206 * you it was a peculiar bug. ;-) 207 */ 208 hpcreg istat0; /* Irq status, only bits <4:0> reliable. */ 209 210#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */ 211#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */ 212#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */ 213 214 hpcreg gio64_misc; /* GIO64 misc control bits. */ 215#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */ 216#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */ 217 218 hpcreg eeprom_data; /* EEPROM data reg. */ 219#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */ 220#define HPC3_EEPROM_CSEL 0x02 /* Chip select */ 221#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */ 222#define HPC3_EEPROM_DATO 0x08 /* Data out */ 223#define HPC3_EEPROM_DATI 0x10 /* Data in */ 224 225 hpcreg istat1; /* Irq status, only bits <9:5> reliable. */ 226 hpcreg gio64_estat; /* GIO64 error interrupt status reg. */ 227#define HPC3_GIOESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */ 228#define HPC3_GIOESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */ 229#define HPC3_GIOESTAT_PIDMSK 0x3f700 /* DMA channel parity identifier */ 230 231 /* Now direct PIO per-HPC3 peripheral access to external regs. */ 232 char _unused2[0x13fec]; /* Trust me... */ 233 hpcreg scsi0_ext[256]; /* SCSI channel 0 external regs */ 234 char _unused3[0x07c00]; /* Trust me... */ 235 hpcreg scsi1_ext[256]; /* SCSI channel 1 external regs */ 236 char _unused4[0x07c00]; /* It'll only hurt a little... */ 237 238 /* Ethernet external registers. Noone use them so we need some 239 * padding instead. 240 */ 241 char _unused5[0x04000]; /* It'll hurt a lot if you leave this out */ 242 243 /* Per-peripheral device external registers and dma/pio control. */ 244 hpcreg pbus_extregs[16][256]; /* 2nd indice indexes controller */ 245 hpcreg pbus_dmacfgs[8][128]; /* 2nd indice indexes controller */ 246#define HPC3_PIODCFG_D3R 0x00000001 /* Cycles to spend in D3 for reads */ 247#define HPC3_PIODCFG_D4R 0x0000001e /* Cycles to spend in D4 for reads */ 248#define HPC3_PIODCFG_D5R 0x000001e0 /* Cycles to spend in D5 for reads */ 249#define HPC3_PIODCFG_D3W 0x00000200 /* Cycles to spend in D3 for writes */ 250#define HPC3_PIODCFG_D4W 0x00003c00 /* Cycles to spend in D4 for writes */ 251#define HPC3_PIODCFG_D5W 0x0003c000 /* Cycles to spend in D5 for writes */ 252#define HPC3_PIODCFG_HWORD 0x00040000 /* Enable 16-bit dma access mode */ 253#define HPC3_PIODCFG_EHI 0x00080000 /* Places halfwords on high 16 bits of bus */ 254#define HPC3_PIODCFG_RTIME 0x00200000 /* Make this device real time on GIO bus */ 255#define HPC3_PIODCFG_BURST 0x07c00000 /* 5 bit burst count for DMA device */ 256#define HPC3_PIODCFG_DRQLV 0x08000000 /* Use live pbus_dreq unsynchronized signal */ 257 258 hpcreg pbus_piocfgs[64][10]; /* 2nd indice indexes controller */ 259#define HPC3_PIOPCFG_RP2 0x00001 /* Cycles to spend in P2 state for reads */ 260#define HPC3_PIOPCFG_RP3 0x0001e /* Cycles to spend in P3 state for reads */ 261#define HPC3_PIOPCFG_RP4 0x001e0 /* Cycles to spend in P4 state for reads */ 262#define HPC3_PIOPCFG_WP2 0x00200 /* Cycles to spend in P2 state for writes */ 263#define HPC3_PIOPCFG_WP3 0x03c00 /* Cycles to spend in P3 state for writes */ 264#define HPC3_PIOPCFG_WP4 0x3c000 /* Cycles to spend in P4 state for writes */ 265#define HPC3_PIOPCFG_HW 0x40000 /* Enable 16-bit PIO accesses */ 266#define HPC3_PIOPCFG_EHI 0x80000 /* Place even address bits in bits <15:8> */ 267 268 /* PBUS PROM control regs. */ 269 hpcreg pbus_promwe; /* PROM write enable register */ 270#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */ 271 272 char _unused6[0x800 - sizeof(hpcreg)]; 273 hpcreg pbus_promswap; /* Chip select swap reg */ 274#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */ 275 276 char _unused7[0x800 - sizeof(hpcreg)]; 277 hpcreg pbus_gout; /* PROM general purpose output reg */ 278#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */ 279 280 char _unused8[0x1000 - sizeof(hpcreg)]; 281 hpcreg pbus_promram[16384]; /* 64k of PROM battery backed ram */ 282}; 283 284/* It is possible to have two HPC3's within the address space on 285 * one machine, though only having one is more likely on an INDY. 286 * Controller 0 lives at physical address 0x1fb80000 and the controller 287 * 1 if present lives at address 0x1fb00000. 288 */ 289extern struct hpc3_regs *hpc3c0, *hpc3c1; 290#define HPC3_CHIP0_PBASE 0x1fb80000 /* physical */ 291#define HPC3_CHIP1_PBASE 0x1fb00000 /* physical */ 292 293/* Control and misc status information, these live in pbus channel 6. */ 294struct hpc3_miscregs { 295 hpcreg pdata, pctrl, pstat, pdmactrl, pistat, pimask; 296 hpcreg ptimer1, ptimer2, ptimer3, ptimer4; 297 hpcreg _unused1[2]; 298 hpcreg ser1cmd, ser1data; 299 hpcreg ser0cmd, ser0data; 300 hpcreg kbdmouse0, kbdmouse1; 301 hpcreg gcsel, genctrl, panel; 302 hpcreg _unused2; 303 hpcreg sysid; 304 hpcreg _unused3; 305 hpcreg read, _unused4; 306 hpcreg dselect; 307#define HPC3_DSELECT_SCLK10MHZ 0x00 /* use 10MHZ serial clock */ 308#define HPC3_DSELECT_ISDNB 0x01 /* enable isdn B */ 309#define HPC3_DSELECT_ISDNA 0x02 /* enable isdn A */ 310#define HPC3_DSELECT_LPR 0x04 /* use parallel DMA */ 311#define HPC3_DSELECT_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ 312#define HPC3_DSELECT_SCLKEXT 0x20 /* use external serial clock */ 313 314 hpcreg _unused5; 315 hpcreg write1; 316#define HPC3_WRITE1_PRESET 0x01 /* 0=LPR_RESET, 1=NORMAL */ 317#define HPC3_WRITE1_KMRESET 0x02 /* 0=KBDMOUSE_RESET, 1=NORMAL */ 318#define HPC3_WRITE1_ERESET 0x04 /* 0=EISA_RESET, 1=NORMAL */ 319#define HPC3_WRITE1_GRESET 0x08 /* 0=MAGIC_GIO_RESET, 1=NORMAL */ 320#define HPC3_WRITE1_LC0OFF 0x10 /* turn led off (guiness=red, else green) */ 321#define HPC3_WRITE1_LC1OFF 0x20 /* turn led off (guiness=green, else amber) */ 322 323 hpcreg _unused6; 324 hpcreg write2; 325#define HPC3_WRITE2_NTHRESH 0x01 /* use 4.5db threshhold */ 326#define HPC3_WRITE2_TPSPEED 0x02 /* use 100ohm TP speed */ 327#define HPC3_WRITE2_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ 328#define HPC3_WRITE2_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ 329#define HPC3_WRITE2_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */ 330#define HPC3_WRITE2_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */ 331#define HPC3_WRITE2_MLO 0x40 /* 1=4.75V 0=+5V */ 332#define HPC3_WRITE2_MHI 0x80 /* 1=5.25V 0=+5V */ 333}; 334extern struct hpc3_miscregs *hpc3mregs; 335#define HPC3_MREGS_PBASE 0x1fbd9800 /* physical */ 336 337/* We need software copies of these because they are write only. */ 338extern unsigned int sgi_hpc_write1, sgi_hpc_write2; 339 340struct hpc_keyb { 341#ifdef __MIPSEB__ 342 unsigned char _unused0[3]; 343 volatile unsigned char data; 344 unsigned char _unused1[3]; 345 volatile unsigned char command; 346#else 347 volatile unsigned char data; 348 unsigned char _unused0[3]; 349 volatile unsigned char command; 350 unsigned char _unused1[3]; 351#endif 352}; 353 354/* Indy RTC */ 355 356/* The layout of registers for the INDY Dallas 1286 clock chipset. */ 357struct indy_clock { 358 volatile unsigned int hsec; 359 volatile unsigned int sec; 360 volatile unsigned int min; 361 volatile unsigned int malarm; 362 volatile unsigned int hr; 363 volatile unsigned int halarm; 364 volatile unsigned int day; 365 volatile unsigned int dalarm; 366 volatile unsigned int date; 367 volatile unsigned int month; 368 volatile unsigned int year; 369 volatile unsigned int cmd; 370 volatile unsigned int whsec; 371 volatile unsigned int wsec; 372 volatile unsigned int _unused0[50]; 373}; 374 375#define INDY_CLOCK_REGS (KSEG1ADDR(0x1fbe0000)) 376 377extern void sgihpc_init(void); 378 379#endif /* __ASM_SGI_SGIHPC_H */ 380