1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 11 * Copyright (C) 2003 Maciej W. Rozycki 12 */ 13#ifndef _ASM_MIPSREGS_H 14#define _ASM_MIPSREGS_H 15 16#include <linux/config.h> 17#include <linux/linkage.h> 18 19/* 20 * The following macros are especially useful for __asm__ 21 * inline assembler. 22 */ 23#ifndef __STR 24#define __STR(x) #x 25#endif 26#ifndef STR 27#define STR(x) __STR(x) 28#endif 29 30/* 31 * Configure language 32 */ 33#ifdef __ASSEMBLY__ 34#define _ULCAST_ 35#else 36#define _ULCAST_ (unsigned long) 37#endif 38 39/* 40 * Coprocessor 0 register names 41 */ 42#define CP0_INDEX $0 43#define CP0_RANDOM $1 44#define CP0_ENTRYLO0 $2 45#define CP0_ENTRYLO1 $3 46#define CP0_CONF $3 47#define CP0_CONTEXT $4 48#define CP0_PAGEMASK $5 49#define CP0_WIRED $6 50#define CP0_INFO $7 51#define CP0_BADVADDR $8 52#define CP0_COUNT $9 53#define CP0_ENTRYHI $10 54#define CP0_COMPARE $11 55#define CP0_STATUS $12 56#define CP0_CAUSE $13 57#define CP0_EPC $14 58#define CP0_PRID $15 59#define CP0_CONFIG $16 60#define CP0_LLADDR $17 61#define CP0_WATCHLO $18 62#define CP0_WATCHHI $19 63#define CP0_XCONTEXT $20 64#define CP0_FRAMEMASK $21 65#define CP0_DIAGNOSTIC $22 66#define CP0_DEBUG $23 67#define CP0_DEPC $24 68#define CP0_PERFORMANCE $25 69#define CP0_ECC $26 70#define CP0_CACHEERR $27 71#define CP0_TAGLO $28 72#define CP0_TAGHI $29 73#define CP0_ERROREPC $30 74#define CP0_DESAVE $31 75 76/* 77 * R4640/R4650 cp0 register names. These registers are listed 78 * here only for completeness; without MMU these CPUs are not useable 79 * by Linux. A future ELKS port might take make Linux run on them 80 * though ... 81 */ 82#define CP0_IBASE $0 83#define CP0_IBOUND $1 84#define CP0_DBASE $2 85#define CP0_DBOUND $3 86#define CP0_CALG $17 87#define CP0_IWATCH $18 88#define CP0_DWATCH $19 89 90/* 91 * Coprocessor 0 Set 1 register names 92 */ 93#define CP0_S1_DERRADDR0 $26 94#define CP0_S1_DERRADDR1 $27 95#define CP0_S1_INTCONTROL $20 96 97/* 98 * TX39 Series 99 */ 100#define CP0_TX39_CACHE $7 101 102/* 103 * Coprocessor 1 (FPU) register names 104 */ 105#define CP1_REVISION $0 106#define CP1_STATUS $31 107 108/* 109 * FPU Status Register Values 110 */ 111/* 112 * Status Register Values 113 */ 114 115#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 116#define FPU_CSR_COND 0x00800000 /* $fcc0 */ 117#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 118#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 119#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 120#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 121#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 122#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 123#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 124#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 125 126/* 127 * X the exception cause indicator 128 * E the exception enable 129 * S the sticky/flag bit 130*/ 131#define FPU_CSR_ALL_X 0x0003f000 132#define FPU_CSR_UNI_X 0x00020000 133#define FPU_CSR_INV_X 0x00010000 134#define FPU_CSR_DIV_X 0x00008000 135#define FPU_CSR_OVF_X 0x00004000 136#define FPU_CSR_UDF_X 0x00002000 137#define FPU_CSR_INE_X 0x00001000 138 139#define FPU_CSR_ALL_E 0x00000f80 140#define FPU_CSR_INV_E 0x00000800 141#define FPU_CSR_DIV_E 0x00000400 142#define FPU_CSR_OVF_E 0x00000200 143#define FPU_CSR_UDF_E 0x00000100 144#define FPU_CSR_INE_E 0x00000080 145 146#define FPU_CSR_ALL_S 0x0000007c 147#define FPU_CSR_INV_S 0x00000040 148#define FPU_CSR_DIV_S 0x00000020 149#define FPU_CSR_OVF_S 0x00000010 150#define FPU_CSR_UDF_S 0x00000008 151#define FPU_CSR_INE_S 0x00000004 152 153/* rounding mode */ 154#define FPU_CSR_RN 0x0 /* nearest */ 155#define FPU_CSR_RZ 0x1 /* towards zero */ 156#define FPU_CSR_RU 0x2 /* towards +Infinity */ 157#define FPU_CSR_RD 0x3 /* towards -Infinity */ 158 159 160/* 161 * Values for PageMask register 162 */ 163#ifdef CONFIG_CPU_VR41XX 164 165/* Why doesn't stupidity hurt ... */ 166 167#define PM_1K 0x00000000 168#define PM_4K 0x00001800 169#define PM_16K 0x00007800 170#define PM_64K 0x0001f800 171#define PM_256K 0x0007f800 172 173#else 174 175#define PM_4K 0x00000000 176#define PM_16K 0x00006000 177#define PM_64K 0x0001e000 178#define PM_256K 0x0007e000 179#define PM_1M 0x001fe000 180#define PM_4M 0x007fe000 181#define PM_16M 0x01ffe000 182#define PM_64M 0x07ffe000 183#define PM_256M 0x1fffe000 184 185#endif 186 187/* 188 * Values used for computation of new tlb entries 189 */ 190#define PL_4K 12 191#define PL_16K 14 192#define PL_64K 16 193#define PL_256K 18 194#define PL_1M 20 195#define PL_4M 22 196#define PL_16M 24 197#define PL_64M 26 198#define PL_256M 28 199 200/* 201 * R4x00 interrupt enable / cause bits 202 */ 203#define IE_SW0 (_ULCAST_(1) << 8) 204#define IE_SW1 (_ULCAST_(1) << 9) 205#define IE_IRQ0 (_ULCAST_(1) << 10) 206#define IE_IRQ1 (_ULCAST_(1) << 11) 207#define IE_IRQ2 (_ULCAST_(1) << 12) 208#define IE_IRQ3 (_ULCAST_(1) << 13) 209#define IE_IRQ4 (_ULCAST_(1) << 14) 210#define IE_IRQ5 (_ULCAST_(1) << 15) 211 212/* 213 * R4x00 interrupt cause bits 214 */ 215#define C_SW0 (_ULCAST_(1) << 8) 216#define C_SW1 (_ULCAST_(1) << 9) 217#define C_IRQ0 (_ULCAST_(1) << 10) 218#define C_IRQ1 (_ULCAST_(1) << 11) 219#define C_IRQ2 (_ULCAST_(1) << 12) 220#define C_IRQ3 (_ULCAST_(1) << 13) 221#define C_IRQ4 (_ULCAST_(1) << 14) 222#define C_IRQ5 (_ULCAST_(1) << 15) 223 224/* 225 * Bitfields in the R4xx0 cp0 status register 226 */ 227#define ST0_IE 0x00000001 228#define ST0_EXL 0x00000002 229#define ST0_ERL 0x00000004 230#define ST0_KSU 0x00000018 231# define KSU_USER 0x00000010 232# define KSU_SUPERVISOR 0x00000008 233# define KSU_KERNEL 0x00000000 234#define ST0_UX 0x00000020 235#define ST0_SX 0x00000040 236#define ST0_KX 0x00000080 237#define ST0_DE 0x00010000 238#define ST0_CE 0x00020000 239 240/* 241 * Bitfields in the R[23]000 cp0 status register. 242 */ 243#define ST0_IEC 0x00000001 244#define ST0_KUC 0x00000002 245#define ST0_IEP 0x00000004 246#define ST0_KUP 0x00000008 247#define ST0_IEO 0x00000010 248#define ST0_KUO 0x00000020 249/* bits 6 & 7 are reserved on R[23]000 */ 250#define ST0_ISC 0x00010000 251#define ST0_SWC 0x00020000 252#define ST0_CM 0x00080000 253 254/* 255 * Bits specific to the R4640/R4650 256 */ 257#define ST0_UM (_ULCAST_(1) << 4) 258#define ST0_IL (_ULCAST_(1) << 23) 259#define ST0_DL (_ULCAST_(1) << 24) 260 261/* 262 * Bitfields in the TX39 family CP0 Configuration Register 3 263 */ 264#define TX39_CONF_ICS_SHIFT 19 265#define TX39_CONF_ICS_MASK 0x00380000 266#define TX39_CONF_ICS_1KB 0x00000000 267#define TX39_CONF_ICS_2KB 0x00080000 268#define TX39_CONF_ICS_4KB 0x00100000 269#define TX39_CONF_ICS_8KB 0x00180000 270#define TX39_CONF_ICS_16KB 0x00200000 271 272#define TX39_CONF_DCS_SHIFT 16 273#define TX39_CONF_DCS_MASK 0x00070000 274#define TX39_CONF_DCS_1KB 0x00000000 275#define TX39_CONF_DCS_2KB 0x00010000 276#define TX39_CONF_DCS_4KB 0x00020000 277#define TX39_CONF_DCS_8KB 0x00030000 278#define TX39_CONF_DCS_16KB 0x00040000 279 280#define TX39_CONF_CWFON 0x00004000 281#define TX39_CONF_WBON 0x00002000 282#define TX39_CONF_RF_SHIFT 10 283#define TX39_CONF_RF_MASK 0x00000c00 284#define TX39_CONF_DOZE 0x00000200 285#define TX39_CONF_HALT 0x00000100 286#define TX39_CONF_LOCK 0x00000080 287#define TX39_CONF_ICE 0x00000020 288#define TX39_CONF_DCE 0x00000010 289#define TX39_CONF_IRSIZE_SHIFT 2 290#define TX39_CONF_IRSIZE_MASK 0x0000000c 291#define TX39_CONF_DRSIZE_SHIFT 0 292#define TX39_CONF_DRSIZE_MASK 0x00000003 293 294/* 295 * Status register bits available in all MIPS CPUs. 296 */ 297#define ST0_IM 0x0000ff00 298#define STATUSB_IP0 8 299#define STATUSF_IP0 (_ULCAST_(1) << 8) 300#define STATUSB_IP1 9 301#define STATUSF_IP1 (_ULCAST_(1) << 9) 302#define STATUSB_IP2 10 303#define STATUSF_IP2 (_ULCAST_(1) << 10) 304#define STATUSB_IP3 11 305#define STATUSF_IP3 (_ULCAST_(1) << 11) 306#define STATUSB_IP4 12 307#define STATUSF_IP4 (_ULCAST_(1) << 12) 308#define STATUSB_IP5 13 309#define STATUSF_IP5 (_ULCAST_(1) << 13) 310#define STATUSB_IP6 14 311#define STATUSF_IP6 (_ULCAST_(1) << 14) 312#define STATUSB_IP7 15 313#define STATUSF_IP7 (_ULCAST_(1) << 15) 314#define STATUSB_IP8 0 315#define STATUSF_IP8 (_ULCAST_(1) << 0) 316#define STATUSB_IP9 1 317#define STATUSF_IP9 (_ULCAST_(1) << 1) 318#define STATUSB_IP10 2 319#define STATUSF_IP10 (_ULCAST_(1) << 2) 320#define STATUSB_IP11 3 321#define STATUSF_IP11 (_ULCAST_(1) << 3) 322#define STATUSB_IP12 4 323#define STATUSF_IP12 (_ULCAST_(1) << 4) 324#define STATUSB_IP13 5 325#define STATUSF_IP13 (_ULCAST_(1) << 5) 326#define STATUSB_IP14 6 327#define STATUSF_IP14 (_ULCAST_(1) << 6) 328#define STATUSB_IP15 7 329#define STATUSF_IP15 (_ULCAST_(1) << 7) 330#define ST0_CH 0x00040000 331#define ST0_SR 0x00100000 332#define ST0_TS 0x00200000 333#define ST0_BEV 0x00400000 334#define ST0_RE 0x02000000 335#define ST0_FR 0x04000000 336#define ST0_CU 0xf0000000 337#define ST0_CU0 0x10000000 338#define ST0_CU1 0x20000000 339#define ST0_CU2 0x40000000 340#define ST0_CU3 0x80000000 341#define ST0_XX 0x80000000 /* MIPS IV naming */ 342 343/* 344 * Bitfields and bit numbers in the coprocessor 0 cause register. 345 * 346 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 347 */ 348#define CAUSEB_EXCCODE 2 349#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 350#define CAUSEB_IP 8 351#define CAUSEF_IP (_ULCAST_(255) << 8) 352#define CAUSEB_IP0 8 353#define CAUSEF_IP0 (_ULCAST_(1) << 8) 354#define CAUSEB_IP1 9 355#define CAUSEF_IP1 (_ULCAST_(1) << 9) 356#define CAUSEB_IP2 10 357#define CAUSEF_IP2 (_ULCAST_(1) << 10) 358#define CAUSEB_IP3 11 359#define CAUSEF_IP3 (_ULCAST_(1) << 11) 360#define CAUSEB_IP4 12 361#define CAUSEF_IP4 (_ULCAST_(1) << 12) 362#define CAUSEB_IP5 13 363#define CAUSEF_IP5 (_ULCAST_(1) << 13) 364#define CAUSEB_IP6 14 365#define CAUSEF_IP6 (_ULCAST_(1) << 14) 366#define CAUSEB_IP7 15 367#define CAUSEF_IP7 (_ULCAST_(1) << 15) 368#define CAUSEB_IV 23 369#define CAUSEF_IV (_ULCAST_(1) << 23) 370#define CAUSEB_CE 28 371#define CAUSEF_CE (_ULCAST_(3) << 28) 372#define CAUSEB_BD 31 373#define CAUSEF_BD (_ULCAST_(1) << 31) 374 375/* 376 * Bits in the coprozessor 0 config register. 377 */ 378#define CONF_CM_CACHABLE_NO_WA 0 379#define CONF_CM_CACHABLE_WA 1 380#define CONF_CM_UNCACHED 2 381#define CONF_CM_CACHABLE_NONCOHERENT 3 382#define CONF_CM_CACHABLE_CE 4 383#define CONF_CM_CACHABLE_COW 5 384#define CONF_CM_CACHABLE_CUW 6 385#define CONF_CM_CACHABLE_ACCELERATED 7 386#define CONF_CM_CMASK 7 387#define CONF_CU (_ULCAST_(1) << 3) 388#define CONF_DB (_ULCAST_(1) << 4) 389#define CONF_IB (_ULCAST_(1) << 5) 390#define CONF_SE (_ULCAST_(1) << 12) 391#define CONF_SC (_ULCAST_(1) << 17) 392#define CONF_AC (_ULCAST_(1) << 23) 393#define CONF_HALT (_ULCAST_(1) << 25) 394 395/* 396 * Bits in the TX49 coprozessor 0 config register. 397 */ 398#define TX49_CONF_DC (_ULCAST_(1) << 16) 399#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 400#define TX49_CONF_HALT (_ULCAST_(1) << 18) 401#define TX49_CONF_CWFON (_ULCAST_(1) << 27) 402 403 404/* 405 * Events counted by counter #0 406 */ 407#define CE0_CYCLES 0 408#define CE0_INSN_ISSUED 1 409#define CE0_LPSC_ISSUED 2 410#define CE0_S_ISSUED 3 411#define CE0_SC_ISSUED 4 412#define CE0_SC_FAILED 5 413#define CE0_BRANCH_DECODED 6 414#define CE0_QW_WB_SECONDARY 7 415#define CE0_CORRECTED_ECC_ERRORS 8 416#define CE0_ICACHE_MISSES 9 417#define CE0_SCACHE_I_MISSES 10 418#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 419#define CE0_EXT_INTERVENTIONS_REQ 12 420#define CE0_EXT_INVALIDATE_REQ 13 421#define CE0_VIRTUAL_COHERENCY_COND 14 422#define CE0_INSN_GRADUATED 15 423 424/* 425 * Events counted by counter #1 426 */ 427#define CE1_CYCLES 0 428#define CE1_INSN_GRADUATED 1 429#define CE1_LPSC_GRADUATED 2 430#define CE1_S_GRADUATED 3 431#define CE1_SC_GRADUATED 4 432#define CE1_FP_INSN_GRADUATED 5 433#define CE1_QW_WB_PRIMARY 6 434#define CE1_TLB_REFILL 7 435#define CE1_BRANCH_MISSPREDICTED 8 436#define CE1_DCACHE_MISS 9 437#define CE1_SCACHE_D_MISSES 10 438#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 439#define CE1_EXT_INTERVENTION_HITS 12 440#define CE1_EXT_INVALIDATE_REQ 13 441#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 442#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 443 444/* 445 * These flags define in which priviledge mode the counters count events 446 */ 447#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ 448#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ 449#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ 450#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ 451 452#ifndef __ASSEMBLY__ 453 454/* 455 * Functions to access the r10k performance counter and control registers 456 */ 457#define read_r10k_perf_cntr(counter) \ 458({ unsigned int __res; \ 459 __asm__ __volatile__( \ 460 "mfpc\t%0, "STR(counter) \ 461 : "=r" (__res)); \ 462 __res;}) 463 464#define write_r10k_perf_cntr(counter,val) \ 465 __asm__ __volatile__( \ 466 "mtpc\t%0, "STR(counter) \ 467 : : "r" (val)); 468 469#define read_r10k_perf_cntl(counter) \ 470({ unsigned int __res; \ 471 __asm__ __volatile__( \ 472 "mfps\t%0, "STR(counter) \ 473 : "=r" (__res)); \ 474 __res;}) 475 476#define write_r10k_perf_cntl(counter,val) \ 477 __asm__ __volatile__( \ 478 "mtps\t%0, "STR(counter) \ 479 : : "r" (val)); 480 481/* 482 * Macros to access the system control coprocessor 483 */ 484 485#define __read_32bit_c0_register(source, sel) \ 486({ int __res; \ 487 if (sel == 0) \ 488 __asm__ __volatile__( \ 489 "mfc0\t%0, " #source "\n\t" \ 490 : "=r" (__res)); \ 491 else \ 492 __asm__ __volatile__( \ 493 ".set\tmips32\n\t" \ 494 "mfc0\t%0, " #source ", " #sel "\n\t" \ 495 ".set\tmips0\n\t" \ 496 : "=r" (__res)); \ 497 __res; \ 498}) 499 500#define __read_64bit_c0_register(source, sel) \ 501({ unsigned long __res; \ 502 if (sel == 0) \ 503 __asm__ __volatile__( \ 504 ".set\tmips3\n\t" \ 505 "dmfc0\t%0, " #source "\n\t" \ 506 ".set\tmips0" \ 507 : "=r" (__res)); \ 508 else \ 509 __asm__ __volatile__( \ 510 ".set\tmips64\n\t" \ 511 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 512 ".set\tmips0" \ 513 : "=r" (__res)); \ 514 __res; \ 515}) 516 517#define __write_32bit_c0_register(register, sel, value) \ 518do { \ 519 if (sel == 0) \ 520 __asm__ __volatile__( \ 521 "mtc0\t%z0, " #register "\n\t" \ 522 : : "Jr" (value)); \ 523 else \ 524 __asm__ __volatile__( \ 525 ".set\tmips32\n\t" \ 526 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 527 ".set\tmips0" \ 528 : : "Jr" (value)); \ 529} while (0) 530 531#define __write_64bit_c0_register(register, sel, value) \ 532do { \ 533 if (sel == 0) \ 534 __asm__ __volatile__( \ 535 ".set\tmips3\n\t" \ 536 "dmtc0\t%z0, " #register "\n\t" \ 537 ".set\tmips0" \ 538 : : "Jr" (value)); \ 539 else \ 540 __asm__ __volatile__( \ 541 ".set\tmips64\n\t" \ 542 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 543 ".set\tmips0" \ 544 : : "Jr" (value)); \ 545} while (0) 546 547#define __read_ulong_c0_register(reg, sel) \ 548 ((sizeof(unsigned long) == 4) ? \ 549 __read_32bit_c0_register(reg, sel) : \ 550 __read_64bit_c0_register(reg, sel)) 551 552#define __write_ulong_c0_register(reg, sel, val) \ 553do { \ 554 if (sizeof(unsigned long) == 4) \ 555 __write_32bit_c0_register(reg, sel, val); \ 556 else \ 557 __write_64bit_c0_register(reg, sel, val); \ 558} while (0) 559 560/* 561 * These versions are only needed for systems with more than 38 bits of 562 * physical address space running the 32-bit kernel. That's none atm :-) 563 */ 564#define __read_64bit_c0_split(source, sel) \ 565({ \ 566 unsigned long long val; \ 567 unsigned long flags; \ 568 \ 569 local_irq_save(flags); \ 570 if (sel == 0) \ 571 __asm__ __volatile__( \ 572 ".set\tmips64\n\t" \ 573 "dmfc0\t%M0, " #source "\n\t" \ 574 "dsll\t%L0, %M0, 32\n\t" \ 575 "dsrl\t%M0, %M0, 32\n\t" \ 576 "dsrl\t%L0, %L0, 32\n\t" \ 577 ".set\tmips0" \ 578 : "=r" (val)); \ 579 else \ 580 __asm__ __volatile__( \ 581 ".set\tmips64\n\t" \ 582 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 583 "dsll\t%L0, %M0, 32\n\t" \ 584 "dsrl\t%M0, %M0, 32\n\t" \ 585 "dsrl\t%L0, %L0, 32\n\t" \ 586 ".set\tmips0" \ 587 : "=r" (val)); \ 588 local_irq_restore(flags); \ 589 \ 590 val; \ 591}) 592 593#define __write_64bit_c0_split(source, sel, val) \ 594do { \ 595 unsigned long flags; \ 596 \ 597 local_irq_save(flags); \ 598 if (sel == 0) \ 599 __asm__ __volatile__( \ 600 ".set\tmips64\n\t" \ 601 "dsll\t%L0, %L0, 32\n\t" \ 602 "dsrl\t%L0, %L0, 32\n\t" \ 603 "dsll\t%M0, %M0, 32\n\t" \ 604 "or\t%L0, %L0, %M0\n\t" \ 605 "dmtc0\t%L0, " #source "\n\t" \ 606 ".set\tmips0" \ 607 : : "r" (val)); \ 608 else \ 609 __asm__ __volatile__( \ 610 ".set\tmips64\n\t" \ 611 "dsll\t%L0, %L0, 32\n\t" \ 612 "dsrl\t%L0, %L0, 32\n\t" \ 613 "dsll\t%M0, %M0, 32\n\t" \ 614 "or\t%L0, %L0, %M0\n\t" \ 615 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 616 ".set\tmips0" \ 617 : : "r" (val)); \ 618 local_irq_restore(flags); \ 619} while (0) 620 621#define read_c0_index() __read_32bit_c0_register($0, 0) 622#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 623 624#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 625#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 626 627#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 628#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 629 630#define read_c0_conf() __read_32bit_c0_register($3, 0) 631#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 632 633#define read_c0_context() __read_ulong_c0_register($4, 0) 634#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 635 636#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 637#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 638 639#define read_c0_wired() __read_32bit_c0_register($6, 0) 640#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 641 642#define read_c0_info() __read_32bit_c0_register($7, 0) 643 644#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 645#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 646 647#define read_c0_count() __read_32bit_c0_register($9, 0) 648#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 649 650#define read_c0_entryhi() __read_ulong_c0_register($10, 0) 651#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 652 653#define read_c0_compare() __read_32bit_c0_register($11, 0) 654#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 655 656#define read_c0_status() __read_32bit_c0_register($12, 0) 657#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 658 659#define read_c0_cause() __read_32bit_c0_register($13, 0) 660#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 661 662#define read_c0_prid() __read_32bit_c0_register($15, 0) 663 664#define read_c0_config() __read_32bit_c0_register($16, 0) 665#define read_c0_config1() __read_32bit_c0_register($16, 1) 666#define read_c0_config2() __read_32bit_c0_register($16, 2) 667#define read_c0_config3() __read_32bit_c0_register($16, 3) 668#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 669#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 670#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 671#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 672 673/* 674 * The WatchLo register. There may be upto 8 of them. 675 */ 676#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 677#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 678#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 679#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 680#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 681#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 682#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 683#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 684#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 685#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 686#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 687#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 688#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 689#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 690#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 691#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 692 693/* 694 * The WatchHi register. There may be upto 8 of them. 695 */ 696#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 697#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 698#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 699#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 700#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 701#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 702#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 703#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 704 705#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 706#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 707#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 708#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 709#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 710#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 711#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 712#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 713 714#define read_c0_xcontext() __read_ulong_c0_register($20, 0) 715#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 716 717#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) 718#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) 719 720#define read_c0_framemask() __read_32bit_c0_register($21, 0) 721#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 722 723#define read_c0_debug() __read_32bit_c0_register($23, 0) 724#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 725 726#define read_c0_depc() __read_ulong_c0_register($24, 0) 727#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 728 729#define read_c0_ecc() __read_32bit_c0_register($26, 0) 730#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 731 732#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 733#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 734 735#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 736 737#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 738#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 739 740#define read_c0_taglo() __read_32bit_c0_register($28, 0) 741#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 742 743#define read_c0_taghi() __read_32bit_c0_register($29, 0) 744#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 745 746#define read_c0_errorepc() __read_ulong_c0_register($30, 0) 747#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 748 749/* 750 * Macros to access the floating point coprocessor control registers 751 */ 752#define read_32bit_cp1_register(source) \ 753({ int __res; \ 754 __asm__ __volatile__( \ 755 ".set\tpush\n\t" \ 756 ".set\treorder\n\t" \ 757 "cfc1\t%0,"STR(source)"\n\t" \ 758 ".set\tpop" \ 759 : "=r" (__res)); \ 760 __res;}) 761 762/* TLB operations. */ 763static inline void tlb_probe(void) 764{ 765 __asm__ __volatile__( 766 ".set noreorder\n\t" 767 "tlbp\n\t" 768 ".set reorder"); 769} 770 771static inline void tlb_read(void) 772{ 773 __asm__ __volatile__( 774 ".set noreorder\n\t" 775 "tlbr\n\t" 776 ".set reorder"); 777} 778 779static inline void tlb_write_indexed(void) 780{ 781 __asm__ __volatile__( 782 ".set noreorder\n\t" 783 "tlbwi\n\t" 784 ".set reorder"); 785} 786 787static inline void tlb_write_random(void) 788{ 789 __asm__ __volatile__( 790 ".set noreorder\n\t" 791 "tlbwr\n\t" 792 ".set reorder"); 793} 794 795/* 796 * Manipulate bits in a c0 register. 797 */ 798#define __BUILD_SET_C0(name,register) \ 799static inline unsigned int \ 800set_c0_##name(unsigned int set) \ 801{ \ 802 unsigned int res; \ 803 \ 804 res = read_c0_##name(); \ 805 res |= set; \ 806 write_c0_##name(res); \ 807 \ 808 return res; \ 809} \ 810 \ 811static inline unsigned int \ 812clear_c0_##name(unsigned int clear) \ 813{ \ 814 unsigned int res; \ 815 \ 816 res = read_c0_##name(); \ 817 res &= ~clear; \ 818 write_c0_##name(res); \ 819 \ 820 return res; \ 821} \ 822 \ 823static inline unsigned int \ 824change_c0_##name(unsigned int change, unsigned int new) \ 825{ \ 826 unsigned int res; \ 827 \ 828 res = read_c0_##name(); \ 829 res &= ~change; \ 830 res |= (new & change); \ 831 write_c0_##name(res); \ 832 \ 833 return res; \ 834} 835 836__BUILD_SET_C0(status,CP0_STATUS) 837__BUILD_SET_C0(cause,CP0_CAUSE) 838__BUILD_SET_C0(config,CP0_CONFIG) 839 840#endif /* !__ASSEMBLY__ */ 841 842#endif /* _ASM_MIPSREGS_H */ 843