1/* 2 * Common definitions for TX3927/TX4927 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2000 Toshiba Corporation 9 */ 10#ifndef __ASM_TXX927_H 11#define __ASM_TXX927_H 12 13#ifndef __ASSEMBLY__ 14 15struct txx927_tmr_reg { 16 volatile unsigned long tcr; 17 volatile unsigned long tisr; 18 volatile unsigned long cpra; 19 volatile unsigned long cprb; 20 volatile unsigned long itmr; 21 volatile unsigned long unused0[3]; 22 volatile unsigned long ccdr; 23 volatile unsigned long unused1[3]; 24 volatile unsigned long pgmr; 25 volatile unsigned long unused2[3]; 26 volatile unsigned long wtmr; 27 volatile unsigned long unused3[43]; 28 volatile unsigned long trr; 29}; 30 31struct txx927_sio_reg { 32 volatile unsigned long lcr; 33 volatile unsigned long dicr; 34 volatile unsigned long disr; 35 volatile unsigned long cisr; 36 volatile unsigned long fcr; 37 volatile unsigned long flcr; 38 volatile unsigned long bgr; 39 volatile unsigned long tfifo; 40 volatile unsigned long rfifo; 41}; 42 43struct txx927_pio_reg { 44 volatile unsigned long dout; 45 volatile unsigned long din; 46 volatile unsigned long dir; 47 volatile unsigned long od; 48 volatile unsigned long flag[2]; 49 volatile unsigned long pol; 50 volatile unsigned long intc; 51 volatile unsigned long maskcpu; 52 volatile unsigned long maskext; 53}; 54 55#endif /* !__ASSEMBLY__ */ 56 57 58/* 59 * TMR 60 */ 61/* TMTCR : Timer Control */ 62#define TXx927_TMTCR_TCE 0x00000080 63#define TXx927_TMTCR_CCDE 0x00000040 64#define TXx927_TMTCR_CRE 0x00000020 65#define TXx927_TMTCR_ECES 0x00000008 66#define TXx927_TMTCR_CCS 0x00000004 67#define TXx927_TMTCR_TMODE_MASK 0x00000003 68#define TXx927_TMTCR_TMODE_ITVL 0x00000000 69 70/* TMTISR : Timer Int. Status */ 71#define TXx927_TMTISR_TPIBS 0x00000004 72#define TXx927_TMTISR_TPIAS 0x00000002 73#define TXx927_TMTISR_TIIS 0x00000001 74 75/* TMTITMR : Interval Timer Mode */ 76#define TXx927_TMTITMR_TIIE 0x00008000 77#define TXx927_TMTITMR_TZCE 0x00000001 78 79/* 80 * SIO 81 */ 82/* SILCR : Line Control */ 83#define TXx927_SILCR_SCS_MASK 0x00000060 84#define TXx927_SILCR_SCS_IMCLK 0x00000000 85#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 86#define TXx927_SILCR_SCS_SCLK 0x00000040 87#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 88#define TXx927_SILCR_UEPS 0x00000010 89#define TXx927_SILCR_UPEN 0x00000008 90#define TXx927_SILCR_USBL_MASK 0x00000004 91#define TXx927_SILCR_USBL_1BIT 0x00000004 92#define TXx927_SILCR_USBL_2BIT 0x00000000 93#define TXx927_SILCR_UMODE_MASK 0x00000003 94#define TXx927_SILCR_UMODE_8BIT 0x00000000 95#define TXx927_SILCR_UMODE_7BIT 0x00000001 96 97/* SIDICR : DMA/Int. Control */ 98#define TXx927_SIDICR_TDE 0x00008000 99#define TXx927_SIDICR_RDE 0x00004000 100#define TXx927_SIDICR_TIE 0x00002000 101#define TXx927_SIDICR_RIE 0x00001000 102#define TXx927_SIDICR_SPIE 0x00000800 103#define TXx927_SIDICR_CTSAC 0x00000600 104#define TXx927_SIDICR_STIE_MASK 0x0000003f 105#define TXx927_SIDICR_STIE_OERS 0x00000020 106#define TXx927_SIDICR_STIE_CTSS 0x00000010 107#define TXx927_SIDICR_STIE_RBRKD 0x00000008 108#define TXx927_SIDICR_STIE_TRDY 0x00000004 109#define TXx927_SIDICR_STIE_TXALS 0x00000002 110#define TXx927_SIDICR_STIE_UBRKD 0x00000001 111 112/* SIDISR : DMA/Int. Status */ 113#define TXx927_SIDISR_UBRK 0x00008000 114#define TXx927_SIDISR_UVALID 0x00004000 115#define TXx927_SIDISR_UFER 0x00002000 116#define TXx927_SIDISR_UPER 0x00001000 117#define TXx927_SIDISR_UOER 0x00000800 118#define TXx927_SIDISR_ERI 0x00000400 119#define TXx927_SIDISR_TOUT 0x00000200 120#define TXx927_SIDISR_TDIS 0x00000100 121#define TXx927_SIDISR_RDIS 0x00000080 122#define TXx927_SIDISR_STIS 0x00000040 123#define TXx927_SIDISR_RFDN_MASK 0x0000001f 124 125/* SICISR : Change Int. Status */ 126#define TXx927_SICISR_OERS 0x00000020 127#define TXx927_SICISR_CTSS 0x00000010 128#define TXx927_SICISR_RBRKD 0x00000008 129#define TXx927_SICISR_TRDY 0x00000004 130#define TXx927_SICISR_TXALS 0x00000002 131#define TXx927_SICISR_UBRKD 0x00000001 132 133/* SIFCR : FIFO Control */ 134#define TXx927_SIFCR_SWRST 0x00008000 135#define TXx927_SIFCR_RDIL_MASK 0x00000180 136#define TXx927_SIFCR_RDIL_1 0x00000000 137#define TXx927_SIFCR_RDIL_4 0x00000080 138#define TXx927_SIFCR_RDIL_8 0x00000100 139#define TXx927_SIFCR_RDIL_12 0x00000180 140#define TXx927_SIFCR_RDIL_MAX 0x00000180 141#define TXx927_SIFCR_TDIL_MASK 0x00000018 142#define TXx927_SIFCR_TDIL_MASK 0x00000018 143#define TXx927_SIFCR_TDIL_1 0x00000000 144#define TXx927_SIFCR_TDIL_4 0x00000001 145#define TXx927_SIFCR_TDIL_8 0x00000010 146#define TXx927_SIFCR_TDIL_MAX 0x00000010 147#define TXx927_SIFCR_TFRST 0x00000004 148#define TXx927_SIFCR_RFRST 0x00000002 149#define TXx927_SIFCR_FRSTE 0x00000001 150#define TXx927_SIO_TX_FIFO 8 151#define TXx927_SIO_RX_FIFO 16 152 153/* SIFLCR : Flow Control */ 154#define TXx927_SIFLCR_RCS 0x00001000 155#define TXx927_SIFLCR_TES 0x00000800 156#define TXx927_SIFLCR_RTSSC 0x00000200 157#define TXx927_SIFLCR_RSDE 0x00000100 158#define TXx927_SIFLCR_TSDE 0x00000080 159#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e 160#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e 161#define TXx927_SIFLCR_TBRK 0x00000001 162 163/* SIBGR : Baudrate Control */ 164#define TXx927_SIBGR_BCLK_MASK 0x00000300 165#define TXx927_SIBGR_BCLK_T0 0x00000000 166#define TXx927_SIBGR_BCLK_T2 0x00000100 167#define TXx927_SIBGR_BCLK_T4 0x00000200 168#define TXx927_SIBGR_BCLK_T6 0x00000300 169#define TXx927_SIBGR_BRD_MASK 0x000000ff 170 171/* 172 * PIO 173 */ 174 175#endif /* __ASM_TXX927_H */ 176