1/* $Id: hubmd_next.h,v 1.1.1.1 2008/10/15 03:27:17 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. 8 */ 9#ifndef _ASM_IA64_SN_SN1_HUBMD_NEXT_H 10#define _ASM_IA64_SN_SN1_HUBMD_NEXT_H 11 12/* In fact, most of this stuff is wrong. Some is correct, such as 13 * MD_PAGE_SIZE and MD_PAGE_NUM_SHFT. 14 */ 15 16#define MD_PERF_COUNTERS 6 17#define MD_PERF_SETS 6 18 19#define MD_SIZE_EMPTY 0 20#define MD_SIZE_64MB 1 21#define MD_SIZE_128MB 2 22#define MD_SIZE_256MB 3 23#define MD_SIZE_512MB 4 24#define MD_SIZE_1GB 5 25 26#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x2000000L << (size)) 27#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 0x20 << (size)) 28#define MD_NUM_ENABLED(_x) ((_x & 0x1) + ((_x >> 1) & 0x1) + \ 29 ((_x >> 2) & 0x1) + ((_x >> 3) & 0x1)) 30 31 32/* Hardware page size and shift */ 33 34#define MD_PAGE_SIZE 16384 /* Page size in bytes */ 35#define MD_PAGE_NUM_SHFT 14 /* Address to page number shift */ 36 37#define MMC_IO_PROT (UINT64_CAST 1 << 45) 38 39/* Register offsets from LOCAL_HUB or REMOTE_HUB */ 40#define MD_PERF_SEL 0x210000 /* Select perf monitor events */ 41 42/* MD_MIG_VALUE_THRESH bit definitions */ 43 44#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63) 45#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff) 46 47/* MD_MIG_CANDIDATE bit definitions */ 48 49#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63) 50#define MD_MIG_CANDIDATE_VALID_SHFT 63 51#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30) 52#define MD_MIG_CANDIDATE_TYPE_SHFT 30 53#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29) 54#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29 55#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20) 56#define MD_MIG_CANDIDATE_NODEID_SHFT 20 57#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff) 58 59 60 61/* Premium SIMM protection entry shifts and masks. */ 62 63#define MD_PPROT_SHFT 0 /* Prot. field */ 64#define MD_PPROT_MASK 0xf 65#define MD_PPROT_REFCNT_SHFT 5 /* Reference count */ 66#define MD_PPROT_REFCNT_WIDTH 0x7ffff 67#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5) 68 69#define MD_PPROT_IO_SHFT 8 /* I/O Prot field */ 70 71/* Standard SIMM protection entry shifts and masks. */ 72 73#define MD_SPROT_SHFT 0 /* Prot. field */ 74#define MD_SPROT_MASK 0xf 75#define MD_SPROT_IO_SHFT 8 76#define MD_SPROT_REFCNT_SHFT 5 /* Reference count */ 77#define MD_SPROT_REFCNT_WIDTH 0x7ff 78#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5) 79 80/* Migration modes used in protection entries */ 81 82#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3) 83#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3) 84#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3) 85#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3) 86 87/* 88 * Operations on Memory/Directory DIMM control register 89 */ 90 91#define DIRTYPE_PREMIUM 1 92#define DIRTYPE_STANDARD 0 93 94/* 95 * Operations on page migration count difference and absolute threshold 96 * registers 97 */ 98 99#define MD_MIG_VALUE_THRESH_GET(region) ( \ 100 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \ 101 MD_MIG_VALUE_THRES_VALUE_MASK) 102 103#define MD_MIG_VALUE_THRESH_SET(region, value) ( \ 104 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ 105 MD_MIG_VALUE_THRES_VALID_MASK | (value))) 106 107#define MD_MIG_VALUE_THRESH_ENABLE(region) ( \ 108 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ 109 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) \ 110 | MD_MIG_VALUE_THRES_VALID_MASK)) 111 112/* 113 * Operations on page migration candidate register 114 */ 115 116#define MD_MIG_CANDIDATE_GET(my_region_id) ( \ 117 REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR)) 118 119#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK) 120 121#define MD_MIG_CANDIDATE_NODEID(value) ( \ 122 ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT) 123 124#define MD_MIG_CANDIDATE_TYPE(value) ( \ 125 ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT) 126 127#define MD_MIG_CANDIDATE_VALID(value) ( \ 128 ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT) 129 130/* 131 * Macros to retrieve fields in the protection entry 132 */ 133 134/* for Premium SIMM */ 135#define MD_PPROT_REFCNT_GET(value) ( \ 136 ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT) 137 138/* for Standard SIMM */ 139#define MD_SPROT_REFCNT_GET(value) ( \ 140 ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT) 141 142#ifndef __ASSEMBLY__ 143#ifdef LITTLE_ENDIAN 144 145typedef union md_perf_sel { 146 uint64_t perf_sel_reg; 147 struct { 148 uint64_t perf_sel : 3, 149 perf_en : 1, 150 perf_rsvd : 60; 151 } perf_sel_bits; 152} md_perf_sel_t; 153 154#else 155 156typedef union md_perf_sel { 157 uint64_t perf_sel_reg; 158 struct { 159 uint64_t perf_rsvd : 60, 160 perf_en : 1, 161 perf_sel : 3; 162 } perf_sel_bits; 163} md_perf_sel_t; 164 165#endif 166#endif /* __ASSEMBLY__ */ 167 168 169/* Like SN0, SN1 supports a mostly-flat address space with 8 170 CPU-visible, evenly spaced, contiguous regions, or "software 171 banks". On SN1, software bank n begins at addresses n * 1GB, 172 0 <= n < 8. 173 174 Physically (and very unlike SN0), each SN1 node board contains 8 175 dimm sockets, arranged as 4 "DIMM banks" of 2 dimms each. DIMM 176 size and width (x4/x8) is assigned per dimm bank. Each DIMM bank 177 consists of 2 "physical banks", one on the front sides of the 2 178 DIMMs and the other on the back sides. Therefore a node has a 179 total of 8 ( = 4 * 2) physical banks. They are collectively 180 referred to as "locational banks", since the locational bank number 181 depends on the physical location of the DIMMs on the board. 182 183 Dimm bank 0, Phys bank 0a (locational bank 0a) 184 Slot D0 ---------------------------------------------- 185 Dimm bank 0, Phys bank 1a (locational bank 1a) 186 187 Dimm bank 1, Phys bank 0a (locational bank 2a) 188 Slot D1 ---------------------------------------------- 189 Dimm bank 1, Phys bank 1a (locational bank 3a) 190 191 Dimm bank 2, Phys bank 0a (locational bank 4a) 192 Slot D2 ---------------------------------------------- 193 Dimm bank 2, Phys bank 1a (locational bank 5a) 194 195 Dimm bank 3, Phys bank 0a (locational bank 6a) 196 Slot D3 ---------------------------------------------- 197 Dimm bank 3, Phys bank 1a (locational bank 7a) 198 199 Dimm bank 0, Phys bank 0b (locational bank 0b) 200 Slot D4 ---------------------------------------------- 201 Dimm bank 0, Phys bank 1b (locational bank 1b) 202 203 Dimm bank 1, Phys bank 0b (locational bank 2b) 204 Slot D5 ---------------------------------------------- 205 Dimm bank 1, Phys bank 1b (locational bank 3b) 206 207 Dimm bank 2, Phys bank 0b (locational bank 4b) 208 Slot D6 ---------------------------------------------- 209 Dimm bank 2, Phys bank 1b (locational bank 5b) 210 211 Dimm bank 3, Phys bank 0b (locational bank 6b) 212 Slot D7 ---------------------------------------------- 213 Dimm bank 3, Phys bank 1b (locational bank 7b) 214 215 Since bank size is assigned per DIMM bank, each pair of locational 216 banks must have the same size. However, they may be 217 enabled/disabled individually. 218 219 The locational banks map to the software banks via the dimm0_sel 220 field in MD_MEMORY_CONFIG. When the field is 0 (the usual case), 221 the mapping is direct: eg. locational bank 1 (dimm bank 0, 222 physical bank 1, which is the back side of the first DIMM pair) 223 corresponds to software bank 1, at node offset 1GB. More 224 generally, locational bank = software bank XOR dimm0_sel. 225 226 All the PROM's data structures (promlog variables, klconfig, etc.) 227 track memory by the locational bank number. The kernel usually 228 tracks memory by the software bank number. 229 memsupport.c:slot_psize_compute() performs the mapping. 230 231 (Note: the terms "locational bank" and "software bank" are not 232 offical in any way, but I've tried to make the PROM use them 233 consistently -- bjj.) 234 */ 235 236#define MD_MEM_BANKS 8 237#define MD_MEM_DIMM_BANKS 4 238#define MD_BANK_SHFT 30 /* log2(1 GB) */ 239#define MD_BANK_MASK (UINT64_CAST 0x7 << 30) 240#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 1 GB */ 241#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT) 242#define MD_BANK_GET(addr) (((addr) & MD_BANK_MASK) >> MD_BANK_SHFT) 243#define MD_BANK_TO_DIMM_BANK(_b) (( (_b) >> 1) & 0x3) 244#define MD_BANK_TO_PHYS_BANK(_b) (( (_b) >> 0) & 0x1) 245#define MD_DIMM_BANK_GET(addr) MD_BANK_TO_DIMM_BANK(MD_BANK_GET(addr)) 246#define MD_PHYS_BANK_GET(addr) MD_BANK_TO_PHYS_BANK(MD_BANK_GET(addr)) 247 248 249/* Split an MD pointer (or message source & suppl. fields) into node, device */ 250 251#define MD_PTR_NODE_SHFT 3 252#define MD_PTR_DEVICE_MASK 0x7 253#define MD_PTR_SUBNODE0_MASK 0x1 254#define MD_PTR_SUBNODE1_MASK 0x4 255 256 257/********************************************************************** 258 259 Backdoor protection and page counter structures 260 261**********************************************************************/ 262 263/* Protection entries and page counters are interleaved at 4 separate 264 addresses, 0x10 apart. Software must read/write all four. */ 265 266#define BD_ITLV_COUNT 4 267#define BD_ITLV_STRIDE 0x10 268 269/* Protection entries */ 270 271/* (these macros work for standard (_rgn < 32) or premium DIMMs) */ 272#define MD_PROT_SHFT(_rgn, _io) ((((_rgn) & 0x20) >> 2 | \ 273 ((_rgn) & 0x01) << 2 | \ 274 ((_io) & 0x1) << 1) * 8) 275#define MD_PROT_MASK(_rgn, _io) (0xff << MD_PROT_SHFT(_rgn, _io)) 276#define MD_PROT_GET(_val, _rgn, _io) \ 277 (((_val) & MD_PROT_MASK(_rgn, _io)) >> MD_PROT_SHFT(_rgn, _io)) 278 279/* Protection field values */ 280 281#define MD_PROT_RW (UINT64_CAST 0xff) 282#define MD_PROT_RO (UINT64_CAST 0x0f) 283#define MD_PROT_NO (UINT64_CAST 0x00) 284 285 286 287 288/********************************************************************** 289 290 Directory format structures 291 292***********************************************************************/ 293 294#ifndef __ASSEMBLY__ 295 296/* Standard Directory Entries */ 297 298#ifdef LITTLE_ENDIAN 299 300struct md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ 301 bdrkreg_t sdp_format : 2; 302 bdrkreg_t sdp_state : 3; 303 bdrkreg_t sdp_priority : 3; 304 bdrkreg_t sdp_pointer1 : 8; 305 bdrkreg_t sdp_ecc : 6; 306 bdrkreg_t sdp_locprot : 1; 307 bdrkreg_t sdp_reserved : 1; 308 bdrkreg_t sdp_crit_word_off : 3; 309 bdrkreg_t sdp_pointer2 : 5; 310 bdrkreg_t sdp_fill : 32; 311}; 312 313#else 314 315struct md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ 316 bdrkreg_t sdp_fill : 32; 317 bdrkreg_t sdp_pointer2 : 5; 318 bdrkreg_t sdp_crit_word_off : 3; 319 bdrkreg_t sdp_reserved : 1; 320 bdrkreg_t sdp_locprot : 1; 321 bdrkreg_t sdp_ecc : 6; 322 bdrkreg_t sdp_pointer1 : 8; 323 bdrkreg_t sdp_priority : 3; 324 bdrkreg_t sdp_state : 3; 325 bdrkreg_t sdp_format : 2; 326}; 327 328#endif 329 330#ifdef LITTLE_ENDIAN 331 332struct md_sdir_fine_fmt { /* shared (fine) */ 333 bdrkreg_t sdf_format : 2; 334 bdrkreg_t sdf_tag1 : 3; 335 bdrkreg_t sdf_tag2 : 3; 336 bdrkreg_t sdf_vector1 : 8; 337 bdrkreg_t sdf_ecc : 6; 338 bdrkreg_t sdf_locprot : 1; 339 bdrkreg_t sdf_tag2valid : 1; 340 bdrkreg_t sdf_vector2 : 8; 341 bdrkreg_t sdf_fill : 32; 342}; 343 344#else 345 346struct md_sdir_fine_fmt { /* shared (fine) */ 347 bdrkreg_t sdf_fill : 32; 348 bdrkreg_t sdf_vector2 : 8; 349 bdrkreg_t sdf_tag2valid : 1; 350 bdrkreg_t sdf_locprot : 1; 351 bdrkreg_t sdf_ecc : 6; 352 bdrkreg_t sdf_vector1 : 8; 353 bdrkreg_t sdf_tag2 : 3; 354 bdrkreg_t sdf_tag1 : 3; 355 bdrkreg_t sdf_format : 2; 356}; 357 358#endif 359 360#ifdef LITTLE_ENDIAN 361 362struct md_sdir_coarse_fmt { /* shared (coarse) */ 363 bdrkreg_t sdc_format : 2; 364 bdrkreg_t sdc_reserved_1 : 6; 365 bdrkreg_t sdc_vector_a : 8; 366 bdrkreg_t sdc_ecc : 6; 367 bdrkreg_t sdc_locprot : 1; 368 bdrkreg_t sdc_reserved : 1; 369 bdrkreg_t sdc_vector_b : 8; 370 bdrkreg_t sdc_fill : 32; 371}; 372 373#else 374 375struct md_sdir_coarse_fmt { /* shared (coarse) */ 376 bdrkreg_t sdc_fill : 32; 377 bdrkreg_t sdc_vector_b : 8; 378 bdrkreg_t sdc_reserved : 1; 379 bdrkreg_t sdc_locprot : 1; 380 bdrkreg_t sdc_ecc : 6; 381 bdrkreg_t sdc_vector_a : 8; 382 bdrkreg_t sdc_reserved_1 : 6; 383 bdrkreg_t sdc_format : 2; 384}; 385 386#endif 387 388typedef union md_sdir { 389 /* The 32 bits of standard directory, in bits 31:0 */ 390 uint64_t sd_val; 391 struct md_sdir_pointer_fmt sdp_fmt; 392 struct md_sdir_fine_fmt sdf_fmt; 393 struct md_sdir_coarse_fmt sdc_fmt; 394} md_sdir_t; 395 396 397/* Premium Directory Entries */ 398 399#ifdef LITTLE_ENDIAN 400 401struct md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ 402 bdrkreg_t pdp_format : 2; 403 bdrkreg_t pdp_state : 3; 404 bdrkreg_t pdp_priority : 3; 405 bdrkreg_t pdp_pointer1_a : 8; 406 bdrkreg_t pdp_reserved_4 : 6; 407 bdrkreg_t pdp_pointer1_b : 3; 408 bdrkreg_t pdp_reserved_3 : 7; 409 bdrkreg_t pdp_ecc_a : 6; 410 bdrkreg_t pdp_locprot : 1; 411 bdrkreg_t pdp_reserved_2 : 1; 412 bdrkreg_t pdp_crit_word_off : 3; 413 bdrkreg_t pdp_pointer2_a : 5; 414 bdrkreg_t pdp_ecc_b : 1; 415 bdrkreg_t pdp_reserved_1 : 5; 416 bdrkreg_t pdp_pointer2_b : 3; 417 bdrkreg_t pdp_reserved : 7; 418}; 419 420#else 421 422struct md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ 423 bdrkreg_t pdp_reserved : 7; 424 bdrkreg_t pdp_pointer2_b : 3; 425 bdrkreg_t pdp_reserved_1 : 5; 426 bdrkreg_t pdp_ecc_b : 1; 427 bdrkreg_t pdp_pointer2_a : 5; 428 bdrkreg_t pdp_crit_word_off : 3; 429 bdrkreg_t pdp_reserved_2 : 1; 430 bdrkreg_t pdp_locprot : 1; 431 bdrkreg_t pdp_ecc_a : 6; 432 bdrkreg_t pdp_reserved_3 : 7; 433 bdrkreg_t pdp_pointer1_b : 3; 434 bdrkreg_t pdp_reserved_4 : 6; 435 bdrkreg_t pdp_pointer1_a : 8; 436 bdrkreg_t pdp_priority : 3; 437 bdrkreg_t pdp_state : 3; 438 bdrkreg_t pdp_format : 2; 439}; 440 441#endif 442 443#ifdef LITTLE_ENDIAN 444 445struct md_pdir_fine_fmt { /* shared (fine) */ 446 bdrkreg_t pdf_format : 2; 447 bdrkreg_t pdf_tag1_a : 3; 448 bdrkreg_t pdf_tag2_a : 3; 449 bdrkreg_t pdf_vector1_a : 8; 450 bdrkreg_t pdf_reserved_1 : 6; 451 bdrkreg_t pdf_tag1_b : 2; 452 bdrkreg_t pdf_vector1_b : 8; 453 bdrkreg_t pdf_ecc_a : 6; 454 bdrkreg_t pdf_locprot : 1; 455 bdrkreg_t pdf_tag2valid : 1; 456 bdrkreg_t pdf_vector2_a : 8; 457 bdrkreg_t pdf_ecc_b : 1; 458 bdrkreg_t pdf_reserved : 5; 459 bdrkreg_t pdf_tag2_b : 2; 460 bdrkreg_t pdf_vector2_b : 8; 461}; 462 463#else 464 465struct md_pdir_fine_fmt { /* shared (fine) */ 466 bdrkreg_t pdf_vector2_b : 8; 467 bdrkreg_t pdf_tag2_b : 2; 468 bdrkreg_t pdf_reserved : 5; 469 bdrkreg_t pdf_ecc_b : 1; 470 bdrkreg_t pdf_vector2_a : 8; 471 bdrkreg_t pdf_tag2valid : 1; 472 bdrkreg_t pdf_locprot : 1; 473 bdrkreg_t pdf_ecc_a : 6; 474 bdrkreg_t pdf_vector1_b : 8; 475 bdrkreg_t pdf_tag1_b : 2; 476 bdrkreg_t pdf_reserved_1 : 6; 477 bdrkreg_t pdf_vector1_a : 8; 478 bdrkreg_t pdf_tag2_a : 3; 479 bdrkreg_t pdf_tag1_a : 3; 480 bdrkreg_t pdf_format : 2; 481}; 482 483#endif 484 485#ifdef LITTLE_ENDIAN 486 487struct md_pdir_sparse_fmt { /* shared (sparse) */ 488 bdrkreg_t pds_format : 2; 489 bdrkreg_t pds_column_a : 6; 490 bdrkreg_t pds_row_a : 8; 491 bdrkreg_t pds_column_b : 16; 492 bdrkreg_t pds_ecc_a : 6; 493 bdrkreg_t pds_locprot : 1; 494 bdrkreg_t pds_reserved_1 : 1; 495 bdrkreg_t pds_row_b : 8; 496 bdrkreg_t pds_ecc_b : 1; 497 bdrkreg_t pds_column_c : 10; 498 bdrkreg_t pds_reserved : 5; 499}; 500 501#else 502 503struct md_pdir_sparse_fmt { /* shared (sparse) */ 504 bdrkreg_t pds_reserved : 5; 505 bdrkreg_t pds_column_c : 10; 506 bdrkreg_t pds_ecc_b : 1; 507 bdrkreg_t pds_row_b : 8; 508 bdrkreg_t pds_reserved_1 : 1; 509 bdrkreg_t pds_locprot : 1; 510 bdrkreg_t pds_ecc_a : 6; 511 bdrkreg_t pds_column_b : 16; 512 bdrkreg_t pds_row_a : 8; 513 bdrkreg_t pds_column_a : 6; 514 bdrkreg_t pds_format : 2; 515}; 516 517#endif 518 519typedef union md_pdir { 520 /* The 64 bits of premium directory */ 521 uint64_t pd_val; 522 struct md_pdir_pointer_fmt pdp_fmt; 523 struct md_pdir_fine_fmt pdf_fmt; 524 struct md_pdir_sparse_fmt pds_fmt; 525} md_pdir_t; 526 527#endif /* __ASSEMBLY__ */ 528 529 530/********************************************************************** 531 532 The defines for backdoor directory and backdoor ECC. 533 534***********************************************************************/ 535 536/* Directory formats, for each format's "format" field */ 537 538#define MD_FORMAT_UNOWNED (UINT64_CAST 0x0) /* 00 */ 539#define MD_FORMAT_POINTER (UINT64_CAST 0x1) /* 01 */ 540#define MD_FORMAT_SHFINE (UINT64_CAST 0x2) /* 10 */ 541#define MD_FORMAT_SHCOARSE (UINT64_CAST 0x3) /* 11 */ 542 /* Shared coarse (standard) and shared sparse (premium) both use fmt 0x3 */ 543 544 545/* 546 * Cacheline state values. 547 * 548 * These are really *software* notions of the "state" of a cacheline; but the 549 * actual values have been carefully chosen to align with some hardware values! 550 * The MD_FMT_ST_TO_STATE macro is used to convert from hardware format/state 551 * pairs in the directory entried into one of these cacheline state values. 552 */ 553 554#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x0) /* ptr format, hw-defined */ 555#define MD_DIR_UNOWNED (UINT64_CAST 0x1) /* format=0 */ 556#define MD_DIR_SHARED (UINT64_CAST 0x2) /* format=2,3 */ 557#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x4) /* ptr format, hw-defined */ 558#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x5) /* ptr format, hw-defined */ 559#define MD_DIR_WAIT (UINT64_CAST 0x6) /* ptr format, hw-defined */ 560#define MD_DIR_POISONED (UINT64_CAST 0x7) /* ptr format, hw-defined */ 561 562#ifndef __ASSEMBLY__ 563 564/* Convert format and state fields into a single "cacheline state" value, defined above */ 565 566#define MD_FMT_ST_TO_STATE(fmt, state) \ 567 ((fmt) == MD_FORMAT_POINTER ? (state) : \ 568 (fmt) == MD_FORMAT_UNOWNED ? MD_DIR_UNOWNED : \ 569 MD_DIR_SHARED) 570#define MD_DIR_STATE(x) MD_FMT_ST_TO_STATE(MD_DIR_FORMAT(x), MD_DIR_STVAL(x)) 571 572#endif /* __ASSEMBLY__ */ 573 574 575 576/* Directory field shifts and masks */ 577 578/* Standard */ 579 580#define MD_SDIR_FORMAT_SHFT 0 /* All formats */ 581#define MD_SDIR_FORMAT_MASK (0x3 << 0) 582#define MD_SDIR_STATE_SHFT 2 /* Pointer fmt. only */ 583#define MD_SDIR_STATE_MASK (0x7 << 2) 584 585/* Premium */ 586 587#define MD_PDIR_FORMAT_SHFT 0 /* All formats */ 588#define MD_PDIR_FORMAT_MASK (0x3 << 0) 589#define MD_PDIR_STATE_SHFT 2 /* Pointer fmt. only */ 590#define MD_PDIR_STATE_MASK (0x7 << 2) 591 592/* Generic */ 593 594#define MD_FORMAT_SHFT 0 /* All formats */ 595#define MD_FORMAT_MASK (0x3 << 0) 596#define MD_STATE_SHFT 2 /* Pointer fmt. only */ 597#define MD_STATE_MASK (0x7 << 2) 598 599 600/* Special shifts to reconstruct fields from the _a and _b parts */ 601 602/* Standard: only shared coarse has split fields */ 603 604#define MD_SDC_VECTORB_SHFT 8 /* eg: sdc_vector_a is 8 bits */ 605 606/* Premium: pointer, shared fine, shared sparse */ 607 608#define MD_PDP_POINTER1A_MASK 0xFF 609#define MD_PDP_POINTER1B_SHFT 8 610#define MD_PDP_POINTER2B_SHFT 5 611#define MD_PDP_ECCB_SHFT 6 612 613#define MD_PDF_VECTOR1B_SHFT 8 614#define MD_PDF_VECTOR2B_SHFT 8 615#define MD_PDF_TAG1B_SHFT 3 616#define MD_PDF_TAG2B_SHFT 3 617#define MD_PDF_ECC_SHFT 6 618 619#define MD_PDS_ROWB_SHFT 8 620#define MD_PDS_COLUMNB_SHFT 6 621#define MD_PDS_COLUMNC_SHFT (MD_PDS_COLUMNB_SHFT + 16) 622#define MD_PDS_ECC_SHFT 6 623 624 625 626/* 627 * Directory/protection/counter initialization values, premium and standard 628 */ 629 630#define MD_PDIR_INIT 0 631#define MD_PDIR_INIT_CNT 0 632#define MD_PDIR_INIT_PROT 0 633 634#define MD_SDIR_INIT 0 635#define MD_SDIR_INIT_CNT 0 636#define MD_SDIR_INIT_PROT 0 637 638#define MD_PDIR_MASK 0xffffffffffffffff 639#define MD_SDIR_MASK 0xffffffff 640 641/* When premium mode is on for probing but standard directory memory 642 is installed, the valid directory bits depend on the phys. bank */ 643#define MD_PDIR_PROBE_MASK(pb) 0xffffffffffffffff 644#define MD_SDIR_PROBE_MASK(pb) (0xffff0000ffff << ((pb) ? 16 : 0)) 645 646 647/* 648 * Misc. field extractions and conversions 649 */ 650 651/* Convert an MD pointer (or message source, supplemental fields) */ 652 653#define MD_PTR_NODE(x) ((x) >> MD_PTR_NODE_SHFT) 654#define MD_PTR_DEVICE(x) ((x) & MD_PTR_DEVICE_MASK) 655#define MD_PTR_SLICE(x) (((x) & MD_PTR_SUBNODE0_MASK) | \ 656 ((x) & MD_PTR_SUBNODE1_MASK) >> 1) 657#define MD_PTR_OWNER_CPU(x) (! ((x) & 2)) 658#define MD_PTR_OWNER_IO(x) ((x) & 2) 659 660/* Extract format and raw state from a directory entry */ 661 662#define MD_DIR_FORMAT(x) ((x) >> MD_SDIR_FORMAT_SHFT & \ 663 MD_SDIR_FORMAT_MASK >> MD_SDIR_FORMAT_SHFT) 664#define MD_DIR_STVAL(x) ((x) >> MD_SDIR_STATE_SHFT & \ 665 MD_SDIR_STATE_MASK >> MD_SDIR_STATE_SHFT) 666 667/* Mask & Shift to get HSPEC_ADDR from MD DIR_ERROR register */ 668#define ERROR_ADDR_SHFT 3 669#define ERROR_HSPEC_SHFT 3 670#define DIR_ERR_HSPEC_MASK 0x1fffffff8 671 672/* 673 * DIR_ERR* and MEM_ERR* defines are used to avoid ugly 674 * #ifdefs for SN0 and SN1 in memerror.c code. See SN0/hubmd.h 675 * for corresponding SN0 definitions. 676 */ 677#define md_dir_error_t md_dir_error_u_t 678#define md_mem_error_t md_mem_error_u_t 679#define derr_reg md_dir_error_regval 680#define merr_reg md_mem_error_regval 681 682#define DIR_ERR_UCE_VALID dir_err.md_dir_error_fld_s.de_uce_valid 683#define DIR_ERR_AE_VALID dir_err.md_dir_error_fld_s.de_ae_valid 684#define DIR_ERR_BAD_SYN dir_err.md_dir_error_fld_s.de_bad_syn 685#define DIR_ERR_CE_OVERRUN dir_err.md_dir_error_fld_s.de_ce_overrun 686#define MEM_ERR_ADDRESS mem_err.md_mem_error_fld_s.me_address 687 /* BRINGUP Can the overrun bit be set without the valid bit? */ 688#define MEM_ERR_CE_OVERRUN (mem_err.md_mem_error_fld_s.me_read_ce >> 1) 689#define MEM_ERR_BAD_SYN mem_err.md_mem_error_fld_s.me_bad_syn 690#define MEM_ERR_UCE_VALID (mem_err.md_mem_error_fld_s.me_read_uce & 1) 691 692 693 694/********************************************************************* 695 696 We have the shift and masks of various fields defined below. 697 698 *********************************************************************/ 699 700/* MD_REFRESH_CONTROL fields */ 701 702#define MRC_ENABLE_SHFT 63 703#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63) 704#define MRC_ENABLE (UINT64_CAST 1 << 63) 705#define MRC_COUNTER_SHFT 12 706#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12) 707#define MRC_CNT_THRESH_MASK 0xfff 708#define MRC_RESET_DEFAULTS (UINT64_CAST 0x800) 709 710/* MD_DIR_CONFIG fields */ 711 712#define MDC_DIR_PREMIUM (UINT64_CAST 1 << 0) 713#define MDC_IGNORE_ECC_SHFT 1 714#define MDC_IGNORE_ECC_MASK (UINT64_CAST 1 << 1) 715 716/* MD_MEMORY_CONFIG fields */ 717 718#define MMC_RP_CONFIG_SHFT 61 719#define MMC_RP_CONFIG_MASK (UINT64_CAST 1 << 61) 720#define MMC_RCD_CONFIG_SHFT 60 721#define MMC_RCD_CONFIG_MASK (UINT64_CAST 1 << 60) 722#define MMC_MB_NEG_EDGE_SHFT 56 723#define MMC_MB_NEG_EDGE_MASK (UINT64_CAST 0x7 << 56) 724#define MMC_SAMPLE_TIME_SHFT 52 725#define MMC_SAMPLE_TIME_MASK (UINT64_CAST 0x3 << 52) 726#define MMC_DELAY_MUX_SEL_SHFT 50 727#define MMC_DELAY_MUX_SEL_MASK (UINT64_CAST 0x3 << 50) 728#define MMC_PHASE_DELAY_SHFT 49 729#define MMC_PHASE_DELAY_MASK (UINT64_CAST 1 << 49) 730#define MMC_DB_NEG_EDGE_SHFT 48 731#define MMC_DB_NEG_EDGE_MASK (UINT64_CAST 1 << 48) 732#define MMC_CPU_PROT_IGNORE_SHFT 47 733#define MMC_CPU_PROT_IGNORE_MASK (UINT64_CAST 1 << 47) 734#define MMC_IO_PROT_IGNORE_SHFT 46 735#define MMC_IO_PROT_IGNORE_MASK (UINT64_CAST 1 << 46) 736#define MMC_IO_PROT_EN_SHFT 45 737#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 45) 738#define MMC_CC_ENABLE_SHFT 44 739#define MMC_CC_ENABLE_MASK (UINT64_CAST 1 << 44) 740#define MMC_DIMM0_SEL_SHFT 32 741#define MMC_DIMM0_SEL_MASK (UINT64_CAST 0x3 << 32) 742#define MMC_DIMM_SIZE_SHFT(_dimm) ((_dimm << 3) + 4) 743#define MMC_DIMM_SIZE_MASK(_dimm) (UINT64_CAST 0xf << MMC_DIMM_SIZE_SHFT(_dimm)) 744#define MMC_DIMM_WIDTH_SHFT(_dimm) ((_dimm << 3) + 3) 745#define MMC_DIMM_WIDTH_MASK(_dimm) (UINT64_CAST 0x1 << MMC_DIMM_WIDTH_SHFT(_dimm)) 746#define MMC_DIMM_BANKS_SHFT(_dimm) (_dimm << 3) 747#define MMC_DIMM_BANKS_MASK(_dimm) (UINT64_CAST 0x3 << MMC_DIMM_BANKS_SHFT(_dimm)) 748#define MMC_BANK_ALL_MASK 0xffffffffLL 749/* Default values for write-only bits in MD_MEMORY_CONFIG */ 750#define MMC_DEFAULT_BITS (UINT64_CAST 0x7 << MMC_MB_NEG_EDGE_SHFT) 751 752/* MD_MB_ECC_CONFIG fields */ 753 754#define MEC_IGNORE_ECC (UINT64_CAST 0x1 << 0) 755 756/* MD_BIST_DATA fields */ 757 758#define MBD_BIST_WRITE (UINT64_CAST 1 << 7) 759#define MBD_BIST_CYCLE (UINT64_CAST 1 << 6) 760#define MBD_BIST_BYTE (UINT64_CAST 1 << 5) 761#define MBD_BIST_NIBBLE (UINT64_CAST 1 << 4) 762#define MBD_BIST_DATA_MASK 0xf 763 764/* MD_BIST_CTL fields */ 765 766#define MBC_DIMM_SHFT 5 767#define MBC_DIMM_MASK (UINT64_CAST 0x3 << 5) 768#define MBC_BANK_SHFT 4 769#define MBC_BANK_MASK (UINT64_CAST 0x1 << 4) 770#define MBC_BIST_RESET (UINT64_CAST 0x1 << 2) 771#define MBC_BIST_STOP (UINT64_CAST 0x1 << 1) 772#define MBC_BIST_START (UINT64_CAST 0x1 << 0) 773 774#define MBC_GO(dimm, bank) \ 775 (((dimm) << MBC_DIMM_SHFT) & MBC_DIMM_MASK | \ 776 ((bank) << MBC_BANK_SHFT) & MBC_BANK_MASK | \ 777 MBC_BIST_START) 778 779/* MD_BIST_STATUS fields */ 780 781#define MBS_BIST_DONE (UINT64_CAST 0X1 << 1) 782#define MBS_BIST_PASSED (UINT64_CAST 0X1 << 0) 783 784/* MD_JUNK_BUS_TIMING fields */ 785 786#define MJT_SYNERGY_ENABLE_SHFT 40 787#define MJT_SYNERGY_ENABLE_MASK (UINT64_CAST 0Xff << MJT_SYNERGY_ENABLE_SHFT) 788#define MJT_SYNERGY_SETUP_SHFT 32 789#define MJT_SYNERGY_SETUP_MASK (UINT64_CAST 0Xff << MJT_SYNERGY_SETUP_SHFT) 790#define MJT_UART_ENABLE_SHFT 24 791#define MJT_UART_ENABLE_MASK (UINT64_CAST 0Xff << MJT_UART_ENABLE_SHFT) 792#define MJT_UART_SETUP_SHFT 16 793#define MJT_UART_SETUP_MASK (UINT64_CAST 0Xff << MJT_UART_SETUP_SHFT) 794#define MJT_FPROM_ENABLE_SHFT 8 795#define MJT_FPROM_ENABLE_MASK (UINT64_CAST 0Xff << MJT_FPROM_ENABLE_SHFT) 796#define MJT_FPROM_SETUP_SHFT 0 797#define MJT_FPROM_SETUP_MASK (UINT64_CAST 0Xff << MJT_FPROM_SETUP_SHFT) 798 799#define MEM_ERROR_VALID_CE 1 800 801 802/* MD_FANDOP_CAC_STAT0, MD_FANDOP_CAC_STAT1 addr field shift */ 803 804#define MFC_ADDR_SHFT 6 805 806#endif /* _ASM_IA64_SN_SN1_HUBMD_NEXT_H */ 807