1/* $Id: pcibr_private.h,v 1.1.1.1 2008/10/15 03:27:17 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. 8 */ 9#ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H 10#define _ASM_SN_PCI_PCIBR_PRIVATE_H 11 12/* 13 * pcibr_private.h -- private definitions for pcibr 14 * only the pcibr driver (and its closest friends) 15 * should ever peek into this file. 16 */ 17 18#include <asm/sn/pci/pcibr.h> 19#include <asm/sn/pci/pciio_private.h> 20#include <asm/sn/ksys/l1.h> 21 22/* 23 * convenience typedefs 24 */ 25 26typedef uint64_t pcibr_DMattr_t; 27typedef uint32_t pcibr_ATEattr_t; 28 29typedef struct pcibr_info_s *pcibr_info_t, **pcibr_info_h; 30typedef struct pcibr_soft_s *pcibr_soft_t; 31typedef struct pcibr_soft_slot_s *pcibr_soft_slot_t; 32typedef struct pcibr_hints_s *pcibr_hints_t; 33typedef struct pcibr_intr_list_s *pcibr_intr_list_t; 34typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t; 35typedef struct pcibr_intr_cbuf_s *pcibr_intr_cbuf_t; 36 37/* 38 * Bridge sets up PIO using this information. 39 */ 40struct pcibr_piomap_s { 41 struct pciio_piomap_s bp_pp; /* generic stuff */ 42 43#define bp_flags bp_pp.pp_flags /* PCIBR_PIOMAP flags */ 44#define bp_dev bp_pp.pp_dev /* associated pci card */ 45#define bp_slot bp_pp.pp_slot /* which slot the card is in */ 46#define bp_space bp_pp.pp_space /* which address space */ 47#define bp_pciaddr bp_pp.pp_pciaddr /* starting offset of mapping */ 48#define bp_mapsz bp_pp.pp_mapsz /* size of this mapping */ 49#define bp_kvaddr bp_pp.pp_kvaddr /* kernel virtual address to use */ 50 51 iopaddr_t bp_xtalk_addr; /* corresponding xtalk address */ 52 xtalk_piomap_t bp_xtalk_pio; /* corresponding xtalk resource */ 53 pcibr_piomap_t bp_next; /* Next piomap on the list */ 54 pcibr_soft_t bp_soft; /* backpointer to bridge soft data */ 55 atomic_t bp_toc[1]; /* PCI timeout counter */ 56 57}; 58 59/* 60 * Bridge sets up DMA using this information. 61 */ 62struct pcibr_dmamap_s { 63 struct pciio_dmamap_s bd_pd; 64#define bd_flags bd_pd.pd_flags /* PCIBR_DMAMAP flags */ 65#define bd_dev bd_pd.pd_dev /* associated pci card */ 66#define bd_slot bd_pd.pd_slot /* which slot the card is in */ 67 struct pcibr_soft_s *bd_soft; /* pcibr soft state backptr */ 68 xtalk_dmamap_t bd_xtalk; /* associated xtalk resources */ 69 70 size_t bd_max_size; /* maximum size of mapping */ 71 xwidgetnum_t bd_xio_port; /* target XIO port */ 72 iopaddr_t bd_xio_addr; /* target XIO address */ 73 iopaddr_t bd_pci_addr; /* via PCI address */ 74 75 int bd_ate_index; /* Address Translation Entry Index */ 76 int bd_ate_count; /* number of ATE's allocated */ 77 bridge_ate_p bd_ate_ptr; /* where to write first ATE */ 78 bridge_ate_t bd_ate_proto; /* prototype ATE (for xioaddr=0) */ 79 bridge_ate_t bd_ate_prime; /* value of 1st ATE written */ 80}; 81 82#define IBUFSIZE 5 /* size of circular buffer (holds 4) */ 83 84/* 85 * Circular buffer used for interrupt processing 86 */ 87struct pcibr_intr_cbuf_s { 88 spinlock_t ib_lock; /* cbuf 'put' lock */ 89 int ib_in; /* index of next free entry */ 90 int ib_out; /* index of next full entry */ 91 pcibr_intr_wrap_t ib_cbuf[IBUFSIZE]; /* circular buffer of wrap */ 92}; 93 94/* 95 * Bridge sets up interrupts using this information. 96 */ 97 98struct pcibr_intr_s { 99 struct pciio_intr_s bi_pi; 100#define bi_flags bi_pi.pi_flags /* PCIBR_INTR flags */ 101#define bi_dev bi_pi.pi_dev /* associated pci card */ 102#define bi_lines bi_pi.pi_lines /* which PCI interrupt line(s) */ 103#define bi_mustruncpu bi_pi.pi_mustruncpu /* Where we must run. */ 104#define bi_irq bi_pi.pi_irq /* IRQ assigned. */ 105#define bi_cpu bi_pi.pi_cpu /* cpu assigned. */ 106 unsigned bi_ibits; /* which Bridge interrupt bit(s) */ 107 pcibr_soft_t bi_soft; /* shortcut to soft info */ 108 struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */ 109}; 110 111/* 112 * per-connect point pcibr data, including 113 * standard pciio data in-line: 114 */ 115struct pcibr_info_s { 116 struct pciio_info_s f_c; /* MUST BE FIRST. */ 117#define f_vertex f_c.c_vertex /* back pointer to vertex */ 118#define f_bus f_c.c_bus /* which bus the card is in */ 119#define f_slot f_c.c_slot /* which slot the card is in */ 120#define f_func f_c.c_func /* which func (on multi-func cards) */ 121#define f_vendor f_c.c_vendor /* PCI card "vendor" code */ 122#define f_device f_c.c_device /* PCI card "device" code */ 123#define f_master f_c.c_master /* PCI bus provider */ 124#define f_mfast f_c.c_mfast /* cached fastinfo from c_master */ 125#define f_pops f_c.c_pops /* cached provider from c_master */ 126#define f_efunc f_c.c_efunc /* error handling function */ 127#define f_einfo f_c.c_einfo /* first parameter for efunc */ 128#define f_window f_c.c_window /* state of BASE regs */ 129#define f_rbase f_c.c_rbase /* expansion rom base */ 130#define f_rsize f_c.c_rsize /* expansion rom size */ 131#define f_piospace f_c.c_piospace /* additional I/O spaces allocated */ 132 133 /* pcibr-specific connection state */ 134 int f_ibit[4]; /* Bridge bit for each INTx */ 135 pcibr_piomap_t f_piomap; 136 int f_att_det_error; 137}; 138 139/* ===================================================================== 140 * Shared Interrupt Information 141 */ 142 143struct pcibr_intr_list_s { 144 pcibr_intr_list_t il_next; 145 pcibr_intr_t il_intr; 146 volatile bridgereg_t *il_wrbf; /* ptr to b_wr_req_buf[] */ 147}; 148 149/* ===================================================================== 150 * Interrupt Wrapper Data 151 */ 152struct pcibr_intr_wrap_s { 153 pcibr_soft_t iw_soft; /* which bridge */ 154 volatile bridgereg_t *iw_stat; /* ptr to b_int_status */ 155 bridgereg_t iw_intr; /* bit in b_int_status */ 156 pcibr_intr_list_t iw_list; /* ghostbusters! */ 157 int iw_hdlrcnt; /* running handler count */ 158 int iw_shared; /* if Bridge bit is shared */ 159 int iw_connected; /* if already connected */ 160}; 161 162#define PCIBR_ISR_ERR_START 8 163#define PCIBR_ISR_MAX_ERRS 32 164 165/* ===================================================================== 166 * Bridge Device State structure 167 * 168 * one instance of this structure is kept for each 169 * Bridge ASIC in the system. 170 */ 171 172struct pcibr_soft_s { 173 devfs_handle_t bs_conn; /* xtalk connection point */ 174 devfs_handle_t bs_vhdl; /* vertex owned by pcibr */ 175 int bs_int_enable; /* Mask of enabled intrs */ 176 bridge_t *bs_base; /* PIO pointer to Bridge chip */ 177 char *bs_name; /* hw graph name */ 178 xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ 179 devfs_handle_t bs_master; /* xtalk master vertex */ 180 xwidgetnum_t bs_mxid; /* master's xtalk ID number */ 181 pciio_slot_t bs_first_slot; /* first existing slot */ 182 pciio_slot_t bs_last_slot; /* last existing slot */ 183 184 185 iopaddr_t bs_dir_xbase; /* xtalk address for 32-bit PCI direct map */ 186 xwidgetnum_t bs_dir_xport; /* xtalk port for 32-bit PCI direct map */ 187 188 struct map *bs_int_ate_map; /* rmalloc map for internal ATEs */ 189 struct map *bs_ext_ate_map; /* rmalloc map for external ATEs */ 190 short bs_int_ate_size; /* number of internal ates */ 191 short bs_xbridge; /* if 1 then xbridge */ 192 193 int bs_rev_num; /* revision number of Bridge */ 194 195 unsigned bs_dma_flags; /* revision-implied DMA flags */ 196 197 l1sc_t *bs_l1sc; /* io brick l1 system cntr */ 198 moduleid_t bs_moduleid; /* io brick moduleid */ 199 200 /* 201 * Lock used primarily to get mutual exclusion while managing any 202 * bridge resources.. 203 */ 204 spinlock_t bs_lock; 205 206 devfs_handle_t bs_noslot_conn; /* NO-SLOT connection point */ 207 pcibr_info_t bs_noslot_info; 208 struct pcibr_soft_slot_s { 209 /* information we keep about each CFG slot */ 210 211 /* some devices (ioc3 in non-slotted 212 * configurations, sometimes) make use 213 * of more than one REQ/GNT/INT* signal 214 * sets. The slot corresponding to the 215 * IDSEL that the device responds to is 216 * called the host slot; the slot 217 * numbers that the device is stealing 218 * REQ/GNT/INT bits from are known as 219 * the guest slots. 220 */ 221 int has_host; 222 pciio_slot_t host_slot; 223 devfs_handle_t slot_conn; 224 225 int slot_status; 226 227 /* Potentially several connection points 228 * for this slot. bss_ninfo is how many, 229 * and bss_infos is a pointer to 230 * an array pcibr_info_t values (which are 231 * pointers to pcibr_info structs, stored 232 * as device_info in connection ponts). 233 */ 234 int bss_ninfo; 235 pcibr_info_h bss_infos; 236 237 /* Temporary Compatibility Macros, for 238 * stuff that has moved out of bs_slot 239 * and into the info structure. These 240 * will go away when their users have 241 * converted over to multifunction- 242 * friendly use of bss_{ninfo,infos}. 243 */ 244#define bss_vendor_id bss_infos[0]->f_vendor 245#define bss_device_id bss_infos[0]->f_device 246#define bss_window bss_infos[0]->f_window 247#define bssw_space w_space 248#define bssw_base w_base 249#define bssw_size w_size 250 251 /* Where is DevIO(x) pointing? */ 252 /* bssd_space is NONE if it is not assigned. */ 253 struct { 254 pciio_space_t bssd_space; 255 iopaddr_t bssd_base; 256 int bssd_ref_cnt; 257 } bss_devio; 258 259 /* Shadow value for Device(x) register, 260 * so we don't have to go to the chip. 261 */ 262 bridgereg_t bss_device; 263 264 /* Number of sets on GBR/REALTIME bit outstanding 265 * Used by Priority I/O for tracking reservations 266 */ 267 int bss_pri_uctr; 268 269 /* Number of "uses" of PMU, 32-bit direct, 270 * and 64-bit direct DMA (0:none, <0: trans, 271 * >0: how many dmamaps). Device(x) bits 272 * controlling attribute of each kind of 273 * channel can't be changed by dmamap_alloc 274 * or dmatrans if the controlling counter 275 * is nonzero. dmatrans is forever. 276 */ 277 int bss_pmu_uctr; 278 int bss_d32_uctr; 279 int bss_d64_uctr; 280 281 /* When the contents of mapping configuration 282 * information is locked down by dmatrans, 283 * repeated checks of the same flags should 284 * be shortcircuited for efficiency. 285 */ 286 iopaddr_t bss_d64_base; 287 unsigned bss_d64_flags; 288 iopaddr_t bss_d32_base; 289 unsigned bss_d32_flags; 290 291 /* Shadow information used for implementing 292 * Bridge Hardware WAR #484930 293 */ 294 atomic_t bss_ext_ates_active; 295 volatile unsigned *bss_cmd_pointer; 296 unsigned bss_cmd_shadow; 297 298 } bs_slot[8]; 299 300 pcibr_intr_bits_f *bs_intr_bits; 301 302 /* RRB MANAGEMENT 303 * bs_rrb_fixed: bitmap of slots whose RRB 304 * allocations we should not "automatically" change 305 * bs_rrb_avail: number of RRBs that have not 306 * been allocated or reserved for {even,odd} slots 307 * bs_rrb_res: number of RRBs reserved for the 308 * use of the index slot number 309 * bs_rrb_valid: number of RRBs marked valid 310 * for the indexed slot number; indexes 8-15 311 * are for the virtual channels for slots 0-7. 312 */ 313 int bs_rrb_fixed; 314 int bs_rrb_avail[2]; 315 int bs_rrb_res[8]; 316 int bs_rrb_res_dflt[8]; 317 int bs_rrb_valid[16]; 318 int bs_rrb_valid_dflt[16]; 319 320 struct { 321 /* Each Bridge interrupt bit has a single XIO 322 * interrupt channel allocated. 323 */ 324 xtalk_intr_t bsi_xtalk_intr; 325 /* 326 * A wrapper structure is associated with each 327 * Bridge interrupt bit. 328 */ 329 struct pcibr_intr_wrap_s bsi_pcibr_intr_wrap; 330 331 } bs_intr[8]; 332 333 xtalk_intr_t bsi_err_intr; 334 335 /* 336 * We stash away some information in this structure on getting 337 * an error interrupt. This information is used during PIO read/ 338 * write error handling. 339 * 340 * As it stands now, we do not re-enable the error interrupt 341 * till the error is resolved. Error resolution happens either at 342 * bus error time for PIO Read errors (~100 microseconds), or at 343 * the scheduled timeout time for PIO write errors (~milliseconds). 344 * If this delay causes problems, we may need to move towards 345 * a different scheme.. 346 * 347 * Note that there is no locking while looking at this data structure. 348 * There should not be any race between bus error code and 349 * error interrupt code.. will look into this if needed. 350 */ 351 struct br_errintr_info { 352 int bserr_toutcnt; 353#ifdef LATER 354 toid_t bserr_toutid; /* Timeout started by errintr */ 355#endif 356 iopaddr_t bserr_addr; /* Address where error occurred */ 357 bridgereg_t bserr_intstat; /* interrupts active at error time */ 358 } bs_errinfo; 359 360 /* 361 * PCI Bus Space allocation data structure. 362 * This info is used to satisfy the callers of pcibr_piospace_alloc 363 * interface. Most of these users need "large" amounts of PIO 364 * space (typically in Megabytes), and they generally tend to 365 * take once and never release.. 366 * For Now use a simple algorithm to manage it. On allocation, 367 * Update the _base field to reflect next free address. 368 * 369 * Freeing does nothing.. So, once allocated, it's gone for good. 370 */ 371 struct br_pcisp_info { 372 iopaddr_t pci_io_base; 373 iopaddr_t pci_io_last; 374 iopaddr_t pci_swin_base; 375 iopaddr_t pci_swin_last; 376 iopaddr_t pci_mem_base; 377 iopaddr_t pci_mem_last; 378 } bs_spinfo; 379 380 struct bs_errintr_stat_s { 381 uint32_t bs_errcount_total; 382 uint32_t bs_lasterr_timestamp; 383 uint32_t bs_lasterr_snapshot; 384 } bs_errintr_stat[PCIBR_ISR_MAX_ERRS]; 385 386 /* 387 * Bridge-wide endianness control for 388 * large-window PIO mappings 389 * 390 * These fields are set to PCIIO_BYTE_SWAP 391 * or PCIIO_WORD_VALUES once the swapper 392 * has been configured, one way or the other, 393 * for the direct windows. If they are zero, 394 * nobody has a PIO mapping through that window, 395 * and the swapper can be set either way. 396 */ 397 unsigned bs_pio_end_io; 398 unsigned bs_pio_end_mem; 399}; 400 401#define PCIBR_ERRTIME_THRESHOLD (100) 402#define PCIBR_ERRRATE_THRESHOLD (100) 403 404/* 405 * pcibr will respond to hints dropped in its vertex 406 * using the following structure. 407 */ 408struct pcibr_hints_s { 409 /* ph_host_slot is actually +1 so "0" means "no host" */ 410 pciio_slot_t ph_host_slot[8]; /* REQ/GNT/INT in use by ... */ 411 unsigned ph_rrb_fixed; /* do not change RRB allocations */ 412 unsigned ph_hands_off; /* prevent further pcibr operations */ 413 rrb_alloc_funct_t rrb_alloc_funct; /* do dynamic rrb allocation */ 414 pcibr_intr_bits_f *ph_intr_bits; /* map PCI INT[ABCD] to Bridge Int(n) */ 415}; 416 417extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; 418 419/* 420 * Number of bridge non-fatal error interrupts we can see before 421 * we decide to disable that interrupt. 422 */ 423#define PCIBR_ERRINTR_DISABLE_LEVEL 10000 424 425/* ===================================================================== 426 * Bridge (pcibr) state management functions 427 * 428 * pcibr_soft_get is here because we do it in a lot 429 * of places and I want to make sure they all stay 430 * in step with each other. 431 * 432 * pcibr_soft_set is here because I want it to be 433 * closely associated with pcibr_soft_get, even 434 * though it is only called in one place. 435 */ 436 437#define pcibr_soft_get(v) ((pcibr_soft_t)hwgraph_fastinfo_get((v))) 438#define pcibr_soft_set(v,i) (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i))) 439 440/* Use io spin locks. This ensures that all the PIO writes from a particular 441 * CPU to a particular IO device are synched before the start of the next 442 * set of PIO operations to the same device. 443 */ 444#define pcibr_lock(pcibr_soft) io_splock(&pcibr_soft->bs_lock) 445#define pcibr_unlock(pcibr_soft,s) io_spunlock(&pcibr_soft->bs_lock,s) 446 447/* 448 * mem alloc/free macros 449 */ 450#define NEWAf(ptr,n,f) (ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)), (f&PCIIO_NOSLEEP)?KM_NOSLEEP:KM_SLEEP)) 451#define NEWA(ptr,n) (ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)), KM_SLEEP)) 452#define DELA(ptr,n) (kfree(ptr)) 453 454#define NEWf(ptr,f) NEWAf(ptr,1,f) 455#define NEW(ptr) NEWA(ptr,1) 456#define DEL(ptr) DELA(ptr,1) 457 458typedef volatile unsigned *cfg_p; 459typedef volatile bridgereg_t *reg_p; 460 461#define PCIBR_RRB_SLOT_VIRTUAL 8 462#define PCIBR_VALID_SLOT(s) (s < 8) 463#define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF) 464#define PCIBR_D32_BASE_UNSET (0xFFFFFFFF) 465#define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev" 466 467#define PCIBR_SOFT_LIST 1 468#if PCIBR_SOFT_LIST 469typedef struct pcibr_list_s *pcibr_list_p; 470struct pcibr_list_s { 471 pcibr_list_p bl_next; 472 pcibr_soft_t bl_soft; 473 devfs_handle_t bl_vhdl; 474}; 475#endif /* PCIBR_SOFT_LIST */ 476 477#endif /* _ASM_SN_PCI_PCIBR_PRIVATE_H */ 478