1/*
2 * File:	mca_asm.h
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Copyright (C) Vijay Chander (vijay@engr.sgi.com)
6 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
7 * Copyright (C) 2000 Hewlett-Packard Co.
8 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
11 */
12#ifndef _ASM_IA64_MCA_ASM_H
13#define _ASM_IA64_MCA_ASM_H
14
15#define PSR_IC		13
16#define PSR_I		14
17#define	PSR_DT		17
18#define PSR_RT		27
19#define PSR_IT		36
20#define PSR_BN		44
21
22/*
23 * This macro converts a instruction virtual address to a physical address
24 * Right now for simulation purposes the virtual addresses are
25 * direct mapped to physical addresses.
26 *	1. Lop off bits 61 thru 63 in the virtual address
27 */
28#define INST_VA_TO_PA(addr)							\
29	dep	addr	= 0, addr, 61, 3
30/*
31 * This macro converts a data virtual address to a physical address
32 * Right now for simulation purposes the virtual addresses are
33 * direct mapped to physical addresses.
34 *	1. Lop off bits 61 thru 63 in the virtual address
35 */
36#define DATA_VA_TO_PA(addr)							\
37	dep	addr	= 0, addr, 61, 3
38/*
39 * This macro converts a data physical address to a virtual address
40 * Right now for simulation purposes the virtual addresses are
41 * direct mapped to physical addresses.
42 *	1. Put 0x7 in bits 61 thru 63.
43 */
44#define DATA_PA_TO_VA(addr,temp)							\
45	mov	temp	= 0x7	;;							\
46	dep	addr	= temp, addr, 61, 3
47
48/*
49 * This macro jumps to the instruction at the given virtual address
50 * and starts execution in physical mode with all the address
51 * translations turned off.
52 *	1.	Save the current psr
53 *	2.	Make sure that all the upper 32 bits are off
54 *
55 *	3.	Clear the interrupt enable and interrupt state collection bits
56 *		in the psr before updating the ipsr and iip.
57 *
58 *	4.	Turn off the instruction, data and rse translation bits of the psr
59 *		and store the new value into ipsr
60 *		Also make sure that the interrupts are disabled.
61 *		Ensure that we are in little endian mode.
62 *		[psr.{rt, it, dt, i, be} = 0]
63 *
64 *	5.	Get the physical address corresponding to the virtual address
65 *		of the next instruction bundle and put it in iip.
66 *		(Using magic numbers 24 and 40 in the deposint instruction since
67 *		 the IA64_SDK code directly maps to lower 24bits as physical address
68 *		 from a virtual address).
69 *
70 *	6.	Do an rfi to move the values from ipsr to psr and iip to ip.
71 */
72#define  PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr)				\
73	mov	old_psr = psr;								\
74	;;										\
75	dep	old_psr = 0, old_psr, 32, 32;						\
76											\
77	mov	ar.rsc = 0 ;								\
78	;;										\
79	srlz.d;										\
80	mov	temp2 = ar.bspstore;							\
81	;;										\
82	DATA_VA_TO_PA(temp2);								\
83	;;										\
84	mov	temp1 = ar.rnat;							\
85	;;										\
86	mov	ar.bspstore = temp2;							\
87	;;										\
88	mov	ar.rnat = temp1;							\
89	mov	temp1 = psr;								\
90	mov	temp2 = psr;								\
91	;;										\
92											\
93	dep	temp2 = 0, temp2, PSR_IC, 2;						\
94	;;										\
95	mov	psr.l = temp2;								\
96	;;										\
97	srlz.d;										\
98	dep	temp1 = 0, temp1, 32, 32;						\
99	;;										\
100	dep	temp1 = 0, temp1, PSR_IT, 1;						\
101	;;										\
102	dep	temp1 = 0, temp1, PSR_DT, 1;						\
103	;;										\
104	dep	temp1 = 0, temp1, PSR_RT, 1;						\
105	;;										\
106	dep	temp1 = 0, temp1, PSR_I, 1;						\
107	;;										\
108	dep	temp1 = 0, temp1, PSR_IC, 1;						\
109	;;										\
110	movl	temp2 = start_addr;							\
111	mov	cr.ipsr = temp1;							\
112	;;										\
113	INST_VA_TO_PA(temp2);								\
114	;;										\
115	mov	cr.iip = temp2;								\
116	mov	cr.ifs = r0;								\
117	DATA_VA_TO_PA(sp);								\
118	DATA_VA_TO_PA(gp);								\
119	;;										\
120	srlz.i;										\
121	;;										\
122	nop	1;									\
123	nop	2;									\
124	nop	1;									\
125	nop	2;									\
126	rfi;										\
127	;;
128
129/*
130 * This macro jumps to the instruction at the given virtual address
131 * and starts execution in virtual mode with all the address
132 * translations turned on.
133 *	1.	Get the old saved psr
134 *
135 *	2.	Clear the interrupt state collection bit in the current psr.
136 *
137 *	3.	Set the instruction translation bit back in the old psr
138 *		Note we have to do this since we are right now saving only the
139 *		lower 32-bits of old psr.(Also the old psr has the data and
140 *		rse translation bits on)
141 *
142 *	4.	Set ipsr to this old_psr with "it" bit set and "bn" = 1.
143 *
144 *	5.	Reset the current thread pointer (r13).
145 *
146 *	6.	Set iip to the virtual address of the next instruction bundle.
147 *
148 *	7.	Do an rfi to move ipsr to psr and iip to ip.
149 */
150
151#define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr)	\
152	mov	temp2 = psr;					\
153	;;							\
154	mov	old_psr = temp2;				\
155	;;							\
156	dep	temp2 = 0, temp2, PSR_IC, 2;			\
157	;;							\
158	mov	psr.l = temp2;					\
159	mov	ar.rsc = 0;					\
160	;;							\
161	srlz.d;							\
162	mov	r13 = ar.k6;					\
163	;;							\
164	DATA_PA_TO_VA(r13,temp1);				\
165	;;							\
166	mov	temp2 = ar.bspstore;				\
167	;;							\
168	DATA_PA_TO_VA(temp2,temp1);				\
169	;;							\
170	mov	temp1 = ar.rnat;				\
171	;;							\
172	mov	ar.bspstore = temp2;				\
173	;;							\
174	mov	ar.rnat = temp1;				\
175	;;							\
176	mov	temp1 = old_psr;				\
177	;;							\
178	mov	temp2 = 1;					\
179	;;							\
180	dep	temp1 = temp2, temp1, PSR_IC, 1;		\
181	;;							\
182	dep	temp1 = temp2, temp1, PSR_IT, 1;		\
183	;;							\
184	dep	temp1 = temp2, temp1, PSR_DT, 1;		\
185	;;							\
186	dep	temp1 = temp2, temp1, PSR_RT, 1;		\
187	;;							\
188	dep	temp1 = temp2, temp1, PSR_BN, 1;		\
189	;;							\
190								\
191	mov     cr.ipsr = temp1;				\
192	movl	temp2 = start_addr;				\
193	;;							\
194	mov	cr.iip = temp2;					\
195	;;							\
196	DATA_PA_TO_VA(sp, temp1);				\
197	DATA_PA_TO_VA(gp, temp2);				\
198	srlz.i;							\
199	;;							\
200	nop	1;						\
201	nop	2;						\
202	nop	1;						\
203	rfi							\
204	;;
205
206/*
207 * The following offsets capture the order in which the
208 * RSE related registers from the old context are
209 * saved onto the new stack frame.
210 *
211 *	+-----------------------+
212 *	|NDIRTY [BSP - BSPSTORE]|
213 *	+-----------------------+
214 *	|	RNAT		|
215 *	+-----------------------+
216 *	|	BSPSTORE	|
217 *	+-----------------------+
218 *	|	IFS		|
219 *	+-----------------------+
220 *	|	PFS		|
221 *	+-----------------------+
222 *	|	RSC		|
223 *	+-----------------------+ <-------- Bottom of new stack frame
224 */
225#define  rse_rsc_offset		0
226#define  rse_pfs_offset		(rse_rsc_offset+0x08)
227#define  rse_ifs_offset		(rse_pfs_offset+0x08)
228#define  rse_bspstore_offset	(rse_ifs_offset+0x08)
229#define  rse_rnat_offset	(rse_bspstore_offset+0x08)
230#define  rse_ndirty_offset	(rse_rnat_offset+0x08)
231
232/*
233 * rse_switch_context
234 *
235 *	1. Save old RSC onto the new stack frame
236 *	2. Save PFS onto new stack frame
237 *	3. Cover the old frame and start a new frame.
238 *	4. Save IFS onto new stack frame
239 *	5. Save the old BSPSTORE on the new stack frame
240 *	6. Save the old RNAT on the new stack frame
241 *	7. Write BSPSTORE with the new backing store pointer
242 *	8. Read and save the new BSP to calculate the #dirty registers
243 * NOTE: Look at pages 11-10, 11-11 in PRM Vol 2
244 */
245#define rse_switch_context(temp,p_stackframe,p_bspstore)			\
246	;;									\
247	mov     temp=ar.rsc;;							\
248	st8     [p_stackframe]=temp,8;;					\
249	mov     temp=ar.pfs;;							\
250	st8     [p_stackframe]=temp,8;						\
251	cover ;;								\
252	mov     temp=cr.ifs;;							\
253	st8     [p_stackframe]=temp,8;;						\
254	mov     temp=ar.bspstore;;						\
255	st8     [p_stackframe]=temp,8;;					\
256	mov     temp=ar.rnat;;							\
257	st8     [p_stackframe]=temp,8;						\
258	mov     ar.bspstore=p_bspstore;;					\
259	mov     temp=ar.bsp;;							\
260	sub     temp=temp,p_bspstore;;						\
261	st8     [p_stackframe]=temp,8;;
262
263/*
264 * rse_return_context
265 *	1. Allocate a zero-sized frame
266 *	2. Store the number of dirty registers RSC.loadrs field
267 *	3. Issue a loadrs to insure that any registers from the interrupted
268 *	   context which were saved on the new stack frame have been loaded
269 *	   back into the stacked registers
270 *	4. Restore BSPSTORE
271 *	5. Restore RNAT
272 *	6. Restore PFS
273 *	7. Restore IFS
274 *	8. Restore RSC
275 *	9. Issue an RFI
276 */
277#define rse_return_context(psr_mask_reg,temp,p_stackframe)			\
278	;;									\
279	alloc   temp=ar.pfs,0,0,0,0;						\
280	add     p_stackframe=rse_ndirty_offset,p_stackframe;;			\
281	ld8     temp=[p_stackframe];;						\
282	shl     temp=temp,16;;							\
283	mov     ar.rsc=temp;;							\
284	loadrs;;								\
285	add     p_stackframe=-rse_ndirty_offset+rse_bspstore_offset,p_stackframe;;\
286	ld8     temp=[p_stackframe];;						\
287	mov     ar.bspstore=temp;;						\
288	add     p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
289	ld8     temp=[p_stackframe];;						\
290	mov     ar.rnat=temp;;							\
291	add     p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;;	\
292	ld8     temp=[p_stackframe];;						\
293	mov     ar.pfs=temp;;							\
294	add     p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;;	\
295	ld8     temp=[p_stackframe];;						\
296	mov     cr.ifs=temp;;							\
297	add     p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;;	\
298	ld8     temp=[p_stackframe];;						\
299	mov     ar.rsc=temp ;							\
300	mov     temp=psr;;							\
301	or      temp=temp,psr_mask_reg;;					\
302	mov     cr.ipsr=temp;;							\
303	mov     temp=ip;;							\
304	add     temp=0x30,temp;;						\
305	mov     cr.iip=temp;;							\
306	srlz.i;;								\
307	rfi;;
308
309#endif /* _ASM_IA64_MCA_ASM_H */
310