1#ifndef __ASM_IO_APIC_H 2#define __ASM_IO_APIC_H 3 4#include <linux/config.h> 5#include <asm/types.h> 6 7/* 8 * Intel IO-APIC support for SMP and UP systems. 9 * 10 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar 11 */ 12 13#ifdef CONFIG_X86_IO_APIC 14 15#define APIC_MISMATCH_DEBUG 16 17#define IO_APIC_BASE(idx) \ 18 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \ 19 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK))) 20 21/* 22 * The structure of the IO-APIC: 23 */ 24struct IO_APIC_reg_00 { 25 __u32 __reserved_2 : 24, 26 ID : 4, 27 __reserved_1 : 4; 28} __attribute__ ((packed)); 29 30struct IO_APIC_reg_01 { 31 __u32 version : 8, 32 __reserved_2 : 7, 33 PRQ : 1, 34 entries : 8, 35 __reserved_1 : 8; 36} __attribute__ ((packed)); 37 38struct IO_APIC_reg_02 { 39 __u32 __reserved_2 : 24, 40 arbitration : 4, 41 __reserved_1 : 4; 42} __attribute__ ((packed)); 43 44/* 45 * # of IO-APICs and # of IRQ routing registers 46 */ 47extern int nr_ioapics; 48extern int nr_ioapic_registers[MAX_IO_APICS]; 49 50enum ioapic_irq_destination_types { 51 dest_Fixed = 0, 52 dest_LowestPrio = 1, 53 dest_SMI = 2, 54 dest__reserved_1 = 3, 55 dest_NMI = 4, 56 dest_INIT = 5, 57 dest__reserved_2 = 6, 58 dest_ExtINT = 7 59}; 60 61struct IO_APIC_route_entry { 62 __u32 vector : 8, 63 delivery_mode : 3, /* 000: FIXED 64 * 001: lowest prio 65 * 111: ExtINT 66 */ 67 dest_mode : 1, /* 0: physical, 1: logical */ 68 delivery_status : 1, 69 polarity : 1, 70 irr : 1, 71 trigger : 1, /* 0: edge, 1: level */ 72 mask : 1, /* 0: enabled, 1: disabled */ 73 __reserved_2 : 15; 74 75 union { struct { __u32 76 __reserved_1 : 24, 77 physical_dest : 4, 78 __reserved_2 : 4; 79 } physical; 80 81 struct { __u32 82 __reserved_1 : 24, 83 logical_dest : 8; 84 } logical; 85 } dest; 86 87} __attribute__ ((packed)); 88 89/* 90 * MP-BIOS irq configuration table structures: 91 */ 92 93/* I/O APIC entries */ 94extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; 95 96/* # of MP IRQ source entries */ 97extern int mp_irq_entries; 98 99/* MP IRQ source entries */ 100extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; 101 102/* non-0 if default (table-less) MP configuration */ 103extern int mpc_default_type; 104 105static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) 106{ 107 *IO_APIC_BASE(apic) = reg; 108 return *(IO_APIC_BASE(apic)+4); 109} 110 111static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) 112{ 113 *IO_APIC_BASE(apic) = reg; 114 *(IO_APIC_BASE(apic)+4) = value; 115} 116 117/* 118 * Re-write a value: to be used for read-modify-write 119 * cycles where the read already set up the index register. 120 */ 121static inline void io_apic_modify(unsigned int apic, unsigned int value) 122{ 123 *(IO_APIC_BASE(apic)+4) = value; 124} 125 126/* 127 * Synchronize the IO-APIC and the CPU by doing 128 * a dummy read from the IO-APIC 129 */ 130static inline void io_apic_sync(unsigned int apic) 131{ 132 (void) *(IO_APIC_BASE(apic)+4); 133} 134 135/* 1 if "noapic" boot option passed */ 136extern int skip_ioapic_setup; 137 138/* 139 * If we use the IO-APIC for IRQ routing, disable automatic 140 * assignment of PCI IRQ's. 141 */ 142#define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup) 143 144#else /* !CONFIG_X86_IO_APIC */ 145#define io_apic_assign_pci_irqs 0 146#endif 147 148#endif 149