1/*
2 * linux/include/asm-arm/arch-sa1100/system3.h
3 *
4 * Copyright (C) 2001 Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
5 *
6 * $Id: system3.h,v 1.1.1.1 2008/10/15 03:27:16 james26_jang Exp $
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * $Log: system3.h,v $
13 * Revision 1.1.1.1  2008/10/15 03:27:16  james26_jang
14 * Initial.
15 *
16 * Revision 1.1.1.1  2008/07/21 09:15:48  james26_jang
17 * New UI, New QoS, New wireless driver(4.151.10.29), ipmonitor.
18 *
19 * Revision 1.1.1.1  2008/07/02 14:40:09  james26_jang
20 * 4.100.10.29, New QoS and New UI.
21 *
22 * Revision 1.1.1.1  2007/02/15 12:12:00  jiahao
23 * initial update
24 *
25 * Revision 1.1.1.1  2007/01/25 12:52:04  jiahao_jhou
26 *
27 *
28 * Revision 1.1.1.1  2003/02/03 22:38:05  mhuang
29 * LINUX_2_4 branch snapshot from linux-mips.org CVS
30 *
31 * Revision 1.2.4.2  2001/12/04 14:58:50  seletz
32 * - removed neponset hack
33 * - removed irq definitions (now in irqs.h)
34 *
35 * Revision 1.2.4.1  2001/12/04 12:51:18  seletz
36 * - re-added from linux_2_4_8_ac12_rmk1_np1_pt1
37 *
38 * Revision 1.2.2.2  2001/11/16 13:58:43  seletz
39 * - simplified cpld register access
40 *
41 * Revision 1.2.2.1  2001/10/15 16:17:20  seletz
42 * - first revision
43 *
44 *
45 */
46
47#ifndef __ASM_ARCH_HARDWARE_H
48#error "include <asm/hardware.h> instead"
49#endif
50
51/* System 3 LCD */
52#define SYS3LCD			SKPEN0
53#define SYS3LCDBACKL	SKPEN1
54#define SYS3LCDBRIGHT	SKPWM0
55#define SYS3LCDCONTR	SKPWM1
56
57#define PT_CPLD_BASE		(0x10000000)
58#define PT_SMC_BASE			(0x18000000)
59#define PT_SA1111_BASE		(0x40000000)
60
61#define Ptcpld_p2v( x )	((x) - PT_CPLD_BASE + 0xf3000000)
62#define Ptcpld_v2p( x )	((x) - 0xf3000000 + PT_CPLD_BASE)
63
64#define _PT_SYSID	( PT_CPLD_BASE + 0x00 )
65#define _PT_IRQSR	( PT_CPLD_BASE + 0x24 )
66#define _PT_CTRL0	( PT_CPLD_BASE + 0x90 )
67#define _PT_CTRL1	( PT_CPLD_BASE + 0xA0 )
68#define _PT_CTRL2	( PT_CPLD_BASE + 0xB0 )
69
70#define PT_SYSID	(*((volatile u_char *)Ptcpld_p2v( _PT_SYSID )))
71#define PT_IRQSR	(*((volatile u_char *)Ptcpld_p2v( _PT_IRQSR )))
72#define PT_CTRL0	(*((volatile u_char *)Ptcpld_p2v( _PT_CTRL0 )))
73#define PT_CTRL1	(*((volatile u_char *)Ptcpld_p2v( _PT_CTRL1 )))
74#define PT_CTRL2	(*((volatile u_char *)Ptcpld_p2v( _PT_CTRL2 )))
75
76#define PTCTRL0_set( x )	PT_CTRL0 |= (x)
77#define PTCTRL1_set( x )	PT_CTRL1 |= (x)
78#define PTCTRL2_set( x )	PT_CTRL2 |= (x)
79#define PTCTRL0_clear( x )	PT_CTRL0 &= ~(x)
80#define PTCTRL1_clear( x )	PT_CTRL1 &= ~(x)
81#define PTCTRL2_clear( x )	PT_CTRL2 &= ~(x)
82
83/* System ID register */
84
85/* IRQ Source Register */
86#define PT_IRQ_LAN		( 1<<0 )
87#define PT_IRQ_X		( 1<<1 )
88#define PT_IRQ_SA1111	( 1<<2 )
89#define PT_IRQ_RS1		( 1<<3 )
90#define PT_IRQ_RS1_RING	( 1<<4 )
91#define PT_IRQ_RS1_DCD	( 1<<5 )
92#define PT_IRQ_RS1_DSR	( 1<<6 )
93#define PT_IRQ_RS2		( 1<<7 )
94
95#define PT_IRQ_USAR		( 1<<1 )
96
97/* CTRL 0 */
98#define PT_CTRL0_USBSLAVE	( 1<<0 )
99#define PT_CTRL0_USBHOST	( 1<<1 )
100#define PT_CTRL0_LCD_BL		( 1<<2 )
101#define PT_CTRL0_LAN_EN		( 1<<3 )	/* active low */
102#define PT_CTRL0_IRDA_M(x)	( (((u_char)x)&0x03)<<4 )
103#define PT_CTRL0_IRDA_M0	( 1<<4 )
104#define PT_CTRL0_IRDA_M1	( 1<<5 )
105#define PT_CTRL0_IRDA_FSEL	( 1<<6 )
106#define PT_CTRL0_LCD_EN		( 1<<7 )
107
108#define PT_CTRL0_INIT	( PT_CTRL0_USBSLAVE | PT_CTRL0_USBHOST | \
109						PT_CTRL0_LCD_BL | PT_CTRL0_LAN_EN | PT_CTRL0_LCD_EN )
110
111/* CTRL 1 */
112#define PT_CTRL1_RS3_MUX(x) ( (((u_char)x)&0x03)<<0 )
113#define PT_CTRL1_RS3_MUX0	( 1<<0 )
114#define PT_CTRL1_RS3_MUX1	( 1<<1 )
115#define PT_CTRL1_RS3_RST	( 1<<2 )
116#define PT_CTRL1_RS3_RS485_TERM	( 1<<4 )
117#define PT_CTRL1_X			( 1<<4 )
118#define PT_CTRL1_PCMCIA_A0VPP	( 1<<6 )
119#define PT_CTRL1_PCMCIA_A1VPP	( 1<<7 )
120
121#define PT_RS3_MUX_ALIRS	( 0 )
122#define PT_RS3_MUX_IDATA	( 1 )
123#define PT_RS3_MUX_RADIO	( 2 )
124#define PT_RS3_MUX_RS485	( 3 )
125
126/* CTRL 2 */
127#define PT_CTRL2_RS1_RTS	( 1<<0 )
128#define PT_CTRL2_RS1_DTR	( 1<<1 )
129