1/* 2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device 3 * 4 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha 5 * 6 * $Id: tgafb.c,v 1.1.1.1 2008/10/15 03:27:05 james26_jang Exp $ 7 * 8 * This driver is partly based on the original TGA framebuffer device, which 9 * was partly based on the original TGA console driver, which are 10 * 11 * Copyright (C) 1997 Geert Uytterhoeven 12 * Copyright (C) 1995 Jay Estabrook 13 * 14 * This file is subject to the terms and conditions of the GNU General Public 15 * License. See the file COPYING in the main directory of this archive for 16 * more details. 17 */ 18 19/* KNOWN PROBLEMS/TO DO ===================================================== * 20 * 21 * - How to set a single color register on 24-plane cards? 22 * 23 * - Hardware cursor/other text acceleration methods 24 * 25 * - Some redraws can stall kernel for several seconds 26 * [This should now be solved by the fast memmove() patch in 2.3.6] 27 * 28 * KNOWN PROBLEMS/TO DO ==================================================== */ 29 30#include <linux/module.h> 31#include <linux/sched.h> 32#include <linux/kernel.h> 33#include <linux/errno.h> 34#include <linux/string.h> 35#include <linux/mm.h> 36#include <linux/tty.h> 37#include <linux/slab.h> 38#include <linux/vmalloc.h> 39#include <linux/delay.h> 40#include <linux/interrupt.h> 41#include <linux/fb.h> 42#include <linux/init.h> 43#include <linux/pci.h> 44#include <linux/selection.h> 45#include <linux/console.h> 46#include <asm/io.h> 47 48#include <video/fbcon.h> 49#include <video/fbcon-cfb8.h> 50#include <video/fbcon-cfb32.h> 51#include "tgafb.h" 52 53 54 /* 55 * Global declarations 56 */ 57 58static struct tgafb_info fb_info; 59static struct tgafb_par current_par; 60static int current_par_valid = 0; 61static struct display disp; 62 63static char default_fontname[40] __initdata = { 0 }; 64static struct fb_var_screeninfo default_var; 65static int default_var_valid = 0; 66 67static int currcon = 0; 68 69static struct { u_char red, green, blue, pad; } palette[256]; 70#ifdef FBCON_HAS_CFB32 71static u32 fbcon_cfb32_cmap[16]; 72#endif 73 74 75 /* 76 * Hardware presets 77 */ 78 79static unsigned int fb_offset_presets[4] = { 80 TGA_8PLANE_FB_OFFSET, 81 TGA_24PLANE_FB_OFFSET, 82 0xffffffff, 83 TGA_24PLUSZ_FB_OFFSET 84}; 85 86static unsigned int deep_presets[4] = { 87 0x00014000, 88 0x0001440d, 89 0xffffffff, 90 0x0001441d 91}; 92 93static unsigned int rasterop_presets[4] = { 94 0x00000003, 95 0x00000303, 96 0xffffffff, 97 0x00000303 98}; 99 100static unsigned int mode_presets[4] = { 101 0x00002000, 102 0x00002300, 103 0xffffffff, 104 0x00002300 105}; 106 107static unsigned int base_addr_presets[4] = { 108 0x00000000, 109 0x00000001, 110 0xffffffff, 111 0x00000001 112}; 113 114 115 116static struct { 117 const char *name; 118 struct fb_var_screeninfo var; 119} tgafb_predefined[] __initdata = { 120 { "640x480-60", { 121 640, 480, 640, 480, 0, 0, 0, 0, 122 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 123 0, 0, -1, -1, FB_ACCELF_TEXT, 39722, 40, 24, 32, 11, 96, 2, 124 0, 125 FB_VMODE_NONINTERLACED 126 }}, 127 { "800x600-56", { 128 800, 600, 800, 600, 0, 0, 0, 0, 129 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 130 0, 0, -1, -1, FB_ACCELF_TEXT, 27777, 128, 24, 22, 1, 72, 2, 131 0, 132 FB_VMODE_NONINTERLACED 133 }}, 134 { "640x480-72", { 135 640, 480, 640, 480, 0, 0, 0, 0, 136 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 137 0, 0, -1, -1, FB_ACCELF_TEXT, 31746, 144, 40, 30, 8, 40, 3, 138 0, 139 FB_VMODE_NONINTERLACED 140 }}, 141 { "800x600-60", { 142 800, 600, 800, 600, 0, 0, 0, 0, 143 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 144 0, 0, -1, -1, FB_ACCELF_TEXT, 25000, 88, 40, 23, 1, 128, 4, 145 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, 146 FB_VMODE_NONINTERLACED 147 }}, 148 { "800x600-72", { 149 800, 600, 800, 600, 0, 0, 0, 0, 150 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 151 0, 0, -1, -1, FB_ACCELF_TEXT, 20000, 64, 56, 23, 37, 120, 6, 152 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, 153 FB_VMODE_NONINTERLACED 154 }}, 155 { "1024x768-60", { 156 1024, 768, 1024, 768, 0, 0, 0, 0, 157 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 158 0, 0, -1, -1, FB_ACCELF_TEXT, 15384, 168, 8, 29, 3, 144, 6, 159 0, 160 FB_VMODE_NONINTERLACED 161 }}, 162 { "1152x864-60", { 163 1152, 864, 1152, 864, 0, 0, 0, 0, 164 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 165 0, 0, -1, -1, FB_ACCELF_TEXT, 11123, 208, 64, 16, 4, 256, 8, 166 0, 167 FB_VMODE_NONINTERLACED 168 }}, 169 { "1024x768-70", { 170 1024, 768, 1024, 768, 0, 0, 0, 0, 171 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 172 0, 0, -1, -1, FB_ACCELF_TEXT, 13333, 144, 24, 29, 3, 136, 6, 173 0, 174 FB_VMODE_NONINTERLACED 175 }}, 176 { "1024x768-76", { 177 1024, 768, 1024, 768, 0, 0, 0, 0, 178 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 179 0, 0, -1, -1, FB_ACCELF_TEXT, 11764, 208, 8, 36, 16, 120, 3, 180 0, 181 FB_VMODE_NONINTERLACED 182 }}, 183 { "1152x864-70", { 184 1152, 864, 1152, 864, 0, 0, 0, 0, 185 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 186 0, 0, -1, -1, FB_ACCELF_TEXT, 10869, 106, 56, 20, 1, 160, 10, 187 0, 188 FB_VMODE_NONINTERLACED 189 }}, 190 { "1280x1024-61", { 191 1280, 1024, 1280, 1024, 0, 0, 0, 0, 192 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 193 0, 0, -1, -1, FB_ACCELF_TEXT, 9090, 200, 48, 26, 1, 184, 3, 194 0, 195 FB_VMODE_NONINTERLACED 196 }}, 197 { "1024x768-85", { 198 1024, 768, 1024, 768, 0, 0, 0, 0, 199 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 200 0, 0, -1, -1, FB_ACCELF_TEXT, 10111, 192, 32, 34, 14, 160, 6, 201 0, 202 FB_VMODE_NONINTERLACED 203 }}, 204 { "1280x1024-70", { 205 1280, 1024, 1280, 1024, 0, 0, 0, 0, 206 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 207 0, 0, -1, -1, FB_ACCELF_TEXT, 7905, 224, 32, 28, 8, 160, 8, 208 0, 209 FB_VMODE_NONINTERLACED 210 }}, 211 { "1152x864-84", { 212 1152, 864, 1152, 864, 0, 0, 0, 0, 213 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 214 0, 0, -1, -1, FB_ACCELF_TEXT, 7407, 184, 312, 32, 0, 128, 12, 215 0, 216 FB_VMODE_NONINTERLACED 217 }}, 218 { "1280x1024-76", { 219 1280, 1024, 1280, 1024, 0, 0, 0, 0, 220 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 221 0, 0, -1, -1, FB_ACCELF_TEXT, 7407, 248, 32, 34, 3, 104, 3, 222 0, 223 FB_VMODE_NONINTERLACED 224 }}, 225 { "1280x1024-85", { 226 1280, 1024, 1280, 1024, 0, 0, 0, 0, 227 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 228 0, 0, -1, -1, FB_ACCELF_TEXT, 6349, 224, 64, 44, 1, 160, 3, 229 0, 230 FB_VMODE_NONINTERLACED 231 }}, 232 233 /* These are modes used by the two fixed-frequency monitors I have at home. 234 * You may or may not find these useful. 235 */ 236 237 { "WYSE1", { /* 1280x1024 @ 72 Hz, 130 Mhz clock */ 238 1280, 1024, 1280, 1024, 0, 0, 0, 0, 239 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 240 0, 0, -1, -1, FB_ACCELF_TEXT, 7692, 192, 32, 47, 0, 192, 5, 241 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, 242 FB_VMODE_NONINTERLACED 243 }}, 244 { "IBM3", { /* 1280x1024 @ 70 Hz, 120 Mhz clock */ 245 1280, 1024, 1280, 1024, 0, 0, 0, 0, 246 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 247 0, 0, -1, -1, FB_ACCELF_TEXT, 8333, 192, 32, 47, 0, 192, 5, 248 0, 249 FB_VMODE_NONINTERLACED 250 }} 251}; 252 253#define NUM_TOTAL_MODES ARRAY_SIZE(tgafb_predefined) 254 255 256 /* 257 * Interface used by the world 258 */ 259 260static void tgafb_detect(void); 261static int tgafb_encode_fix(struct fb_fix_screeninfo *fix, const void *fb_par, 262 struct fb_info_gen *info); 263static int tgafb_decode_var(const struct fb_var_screeninfo *var, void *fb_par, 264 struct fb_info_gen *info); 265static int tgafb_encode_var(struct fb_var_screeninfo *var, const void *fb_par, 266 struct fb_info_gen *info); 267static void tgafb_get_par(void *fb_par, struct fb_info_gen *info); 268static void tgafb_set_par(const void *fb_par, struct fb_info_gen *info); 269static int tgafb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue, 270 u_int *transp, struct fb_info *info); 271static int tgafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 272 u_int transp, struct fb_info *info); 273static int tgafb_blank(int blank, struct fb_info_gen *info); 274static void tgafb_set_disp(const void *fb_par, struct display *disp, 275 struct fb_info_gen *info); 276 277#ifndef MODULE 278int tgafb_setup(char*); 279#endif 280 281static void tgafb_set_pll(int f); 282static int tgafb_set_cmap(struct fb_cmap *cmap, int kspc, int con, 283 struct fb_info *info); 284static void tgafb_update_palette(void); 285 286 287 /* 288 * Chipset specific functions 289 */ 290 291 292static void tgafb_detect(void) 293{ 294 return; 295} 296 297 298static int tgafb_encode_fix(struct fb_fix_screeninfo *fix, const void *fb_par, 299 struct fb_info_gen *info) 300{ 301 struct tgafb_par *par = (struct tgafb_par *)fb_par; 302 303 strcpy(fix->id, fb_info.gen.info.modename); 304 305 fix->type = FB_TYPE_PACKED_PIXELS; 306 fix->type_aux = 0; 307 if (fb_info.tga_type == TGA_TYPE_8PLANE) { 308 fix->visual = FB_VISUAL_PSEUDOCOLOR; 309 } else { 310 fix->visual = FB_VISUAL_TRUECOLOR; 311 } 312 313 fix->line_length = par->xres * (par->bits_per_pixel >> 3); 314 fix->smem_start = fb_info.tga_fb_base; 315 fix->smem_len = fix->line_length * par->yres; 316 fix->mmio_start = fb_info.tga_regs_base; 317 fix->mmio_len = 0x1000; /* Is this sufficient? */ 318 fix->xpanstep = fix->ypanstep = fix->ywrapstep = 0; 319 fix->accel = FB_ACCEL_DEC_TGA; 320 321 return 0; 322} 323 324 325static int tgafb_decode_var(const struct fb_var_screeninfo *var, void *fb_par, 326 struct fb_info_gen *info) 327{ 328 struct tgafb_par *par = (struct tgafb_par *)fb_par; 329 330 /* round up some */ 331 if (fb_info.tga_type == TGA_TYPE_8PLANE) { 332 if (var->bits_per_pixel > 8) { 333 return -EINVAL; 334 } 335 par->bits_per_pixel = 8; 336 } else { 337 if (var->bits_per_pixel > 32) { 338 return -EINVAL; 339 } 340 par->bits_per_pixel = 32; 341 } 342 343 /* check the values for sanity */ 344 if (var->xres_virtual != var->xres || 345 var->yres_virtual != var->yres || 346 var->nonstd || (1000000000/var->pixclock) > TGA_PLL_MAX_FREQ || 347 (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED 348 ) 349 return -EINVAL; 350 351 /* encode video timings */ 352 par->htimings = ((var->xres/4) & TGA_HORIZ_ACT_LSB) | 353 (((var->xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB); 354 par->vtimings = (var->yres & TGA_VERT_ACTIVE); 355 par->htimings |= ((var->right_margin/4) << 9) & TGA_HORIZ_FP; 356 par->vtimings |= (var->lower_margin << 11) & TGA_VERT_FP; 357 par->htimings |= ((var->hsync_len/4) << 14) & TGA_HORIZ_SYNC; 358 par->vtimings |= (var->vsync_len << 16) & TGA_VERT_SYNC; 359 par->htimings |= ((var->left_margin/4) << 21) & TGA_HORIZ_BP; 360 par->vtimings |= (var->upper_margin << 22) & TGA_VERT_BP; 361 362 if (var->sync & FB_SYNC_HOR_HIGH_ACT) 363 par->htimings |= TGA_HORIZ_POLARITY; 364 if (var->sync & FB_SYNC_VERT_HIGH_ACT) 365 par->vtimings |= TGA_VERT_POLARITY; 366 if (var->sync & FB_SYNC_ON_GREEN) { 367 par->sync_on_green = 1; 368 } else { 369 par->sync_on_green = 0; 370 } 371 372 /* store other useful values in par */ 373 par->xres = var->xres; 374 par->yres = var->yres; 375 par->pll_freq = 1000000000/var->pixclock; 376 par->bits_per_pixel = var->bits_per_pixel; 377 378 return 0; 379} 380 381 382static int tgafb_encode_var(struct fb_var_screeninfo *var, const void *fb_par, 383 struct fb_info_gen *info) 384{ 385 struct tgafb_par *par = (struct tgafb_par *)fb_par; 386 387 /* decode video timings */ 388 var->xres = ((par->htimings & TGA_HORIZ_ACT_LSB) | ((par->htimings & TGA_HORIZ_ACT_MSB) >> 19)) * 4; 389 var->yres = (par->vtimings & TGA_VERT_ACTIVE); 390 var->right_margin = ((par->htimings & TGA_HORIZ_FP) >> 9) * 4; 391 var->lower_margin = ((par->vtimings & TGA_VERT_FP) >> 11); 392 var->hsync_len = ((par->htimings & TGA_HORIZ_SYNC) >> 14) * 4; 393 var->vsync_len = ((par->vtimings & TGA_VERT_SYNC) >> 16); 394 var->left_margin = ((par->htimings & TGA_HORIZ_BP) >> 21) * 4; 395 var->upper_margin = ((par->vtimings & TGA_VERT_BP) >> 22); 396 397 if (par->htimings & TGA_HORIZ_POLARITY) 398 var->sync |= FB_SYNC_HOR_HIGH_ACT; 399 if (par->vtimings & TGA_VERT_POLARITY) 400 var->sync |= FB_SYNC_VERT_HIGH_ACT; 401 if (par->sync_on_green == 1) 402 var->sync |= FB_SYNC_ON_GREEN; 403 404 var->xres_virtual = var->xres; 405 var->yres_virtual = var->yres; 406 var->xoffset = var->yoffset = 0; 407 408 /* depth-related */ 409 if (fb_info.tga_type == TGA_TYPE_8PLANE) { 410 var->red.offset = 0; 411 var->green.offset = 0; 412 var->blue.offset = 0; 413 } else { 414 var->red.offset = 16; 415 var->green.offset = 8; 416 var->blue.offset = 0; 417 } 418 var->bits_per_pixel = par->bits_per_pixel; 419 var->grayscale = 0; 420 var->red.length = var->green.length = var->blue.length = 8; 421 var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0; 422 var->transp.offset = var->transp.length = var->transp.msb_right = 0; 423 424 /* others */ 425 var->xoffset = var->yoffset = 0; 426 var->pixclock = 1000000000/par->pll_freq; 427 var->nonstd = 0; 428 var->activate = 0; 429 var->height = var->width = -1; 430 var->accel_flags = 0; 431 432 return 0; 433} 434 435 436static void tgafb_get_par(void *fb_par, struct fb_info_gen *info) 437{ 438 struct tgafb_par *par = (struct tgafb_par *)fb_par; 439 440 if (current_par_valid) 441 *par = current_par; 442 else { 443 if (fb_info.tga_type == TGA_TYPE_8PLANE) 444 default_var.bits_per_pixel = 8; 445 else 446 default_var.bits_per_pixel = 32; 447 448 tgafb_decode_var(&default_var, par, info); 449 } 450} 451 452 453static void tgafb_set_par(const void *fb_par, struct fb_info_gen *info) 454{ 455 int i, j; 456 struct tgafb_par *par = (struct tgafb_par *)fb_par; 457 458 current_par = *par; 459 current_par_valid = 1; 460 461 /* first, disable video */ 462 TGA_WRITE_REG(TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG); 463 464 /* write the DEEP register */ 465 while (TGA_READ_REG(TGA_CMD_STAT_REG) & 1) /* wait for not busy */ 466 continue; 467 468 mb(); 469 TGA_WRITE_REG(deep_presets[fb_info.tga_type], TGA_DEEP_REG); 470 while (TGA_READ_REG(TGA_CMD_STAT_REG) & 1) /* wait for not busy */ 471 continue; 472 mb(); 473 474 /* write some more registers */ 475 TGA_WRITE_REG(rasterop_presets[fb_info.tga_type], TGA_RASTEROP_REG); 476 TGA_WRITE_REG(mode_presets[fb_info.tga_type], TGA_MODE_REG); 477 TGA_WRITE_REG(base_addr_presets[fb_info.tga_type], TGA_BASE_ADDR_REG); 478 479 /* calculate & write the PLL */ 480 tgafb_set_pll(par->pll_freq); 481 482 /* write some more registers */ 483 TGA_WRITE_REG(0xffffffff, TGA_PLANEMASK_REG); 484 TGA_WRITE_REG(0xffffffff, TGA_PIXELMASK_REG); 485 TGA_WRITE_REG(0x12345678, TGA_BLOCK_COLOR0_REG); 486 TGA_WRITE_REG(0x12345678, TGA_BLOCK_COLOR1_REG); 487 488 /* init video timing regs */ 489 TGA_WRITE_REG(par->htimings, TGA_HORIZ_REG); 490 TGA_WRITE_REG(par->vtimings, TGA_VERT_REG); 491 492 /* initalise RAMDAC */ 493 if (fb_info.tga_type == TGA_TYPE_8PLANE) { 494 495 /* init BT485 RAMDAC registers */ 496 BT485_WRITE(0xa2 | (par->sync_on_green ? 0x8 : 0x0), BT485_CMD_0); 497 BT485_WRITE(0x01, BT485_ADDR_PAL_WRITE); 498 BT485_WRITE(0x14, BT485_CMD_3); /* cursor 64x64 */ 499 BT485_WRITE(0x40, BT485_CMD_1); 500 BT485_WRITE(0x20, BT485_CMD_2); /* cursor off, for now */ 501 BT485_WRITE(0xff, BT485_PIXEL_MASK); 502 503 /* fill palette registers */ 504 BT485_WRITE(0x00, BT485_ADDR_PAL_WRITE); 505 TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); 506 507 for (i = 0; i < 16; i++) { 508 j = color_table[i]; 509 TGA_WRITE_REG(default_red[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); 510 TGA_WRITE_REG(default_grn[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); 511 TGA_WRITE_REG(default_blu[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); 512 palette[i].red=default_red[j]; 513 palette[i].green=default_grn[j]; 514 palette[i].blue=default_blu[j]; 515 } 516 for (i = 0; i < 240*3; i += 4) { 517 TGA_WRITE_REG(0x55|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); 518 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); 519 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); 520 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); 521 } 522 523 } else { /* 24-plane or 24plusZ */ 524 525 /* init BT463 registers */ 526 BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_0, 0x40); 527 BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_1, 0x08); 528 BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_2, 529 (par->sync_on_green ? 0x80 : 0x40)); 530 531 BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_0, 0xff); 532 BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_1, 0xff); 533 BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_2, 0xff); 534 BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_3, 0x0f); 535 536 BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00); 537 BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00); 538 BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00); 539 BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00); 540 541 /* fill the palette */ 542 BT463_LOAD_ADDR(0x0000); 543 TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG); 544 545 for (i = 0; i < 16; i++) { 546 j = color_table[i]; 547 TGA_WRITE_REG(default_red[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 548 TGA_WRITE_REG(default_grn[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 549 TGA_WRITE_REG(default_blu[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 550 } 551 for (i = 0; i < 512*3; i += 4) { 552 TGA_WRITE_REG(0x55|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 553 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 554 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 555 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 556 } 557 558 /* fill window type table after start of vertical retrace */ 559 while (!(TGA_READ_REG(TGA_INTR_STAT_REG) & 0x01)) 560 continue; 561 TGA_WRITE_REG(0x01, TGA_INTR_STAT_REG); 562 mb(); 563 while (!(TGA_READ_REG(TGA_INTR_STAT_REG) & 0x01)) 564 continue; 565 TGA_WRITE_REG(0x01, TGA_INTR_STAT_REG); 566 567 BT463_LOAD_ADDR(BT463_WINDOW_TYPE_BASE); 568 TGA_WRITE_REG((BT463_REG_ACC<<2), TGA_RAMDAC_SETUP_REG); 569 570 for (i = 0; i < 16; i++) { 571 TGA_WRITE_REG(0x00|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); 572 TGA_WRITE_REG(0x01|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); 573 TGA_WRITE_REG(0x80|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); 574 } 575 576 } 577 578 /* finally, enable video scan 579 (and pray for the monitor... :-) */ 580 TGA_WRITE_REG(TGA_VALID_VIDEO, TGA_VALID_REG); 581} 582 583 584#define DIFFCHECK(x) { if( m <= 0x3f ) { \ 585 int delta = f - (TGA_PLL_BASE_FREQ * (x)) / (r << shift); \ 586 if (delta < 0) delta = -delta; \ 587 if (delta < min_diff) min_diff = delta, vm = m, va = a, vr = r; } } 588 589static void tgafb_set_pll(int f) 590{ 591 int n, shift, base, min_diff, target; 592 int r,a,m,vm = 34, va = 1, vr = 30; 593 594 for( r = 0 ; r < 12 ; r++ ) 595 TGA_WRITE_REG(!r, TGA_CLOCK_REG); 596 597 if (f > TGA_PLL_MAX_FREQ) 598 f = TGA_PLL_MAX_FREQ; 599 600 if (f >= TGA_PLL_MAX_FREQ / 2) 601 shift = 0; 602 else if (f >= TGA_PLL_MAX_FREQ / 4) 603 shift = 1; 604 else 605 shift = 2; 606 607 TGA_WRITE_REG(shift & 1, TGA_CLOCK_REG); 608 TGA_WRITE_REG(shift >> 1, TGA_CLOCK_REG); 609 610 for( r = 0 ; r < 10 ; r++ ) { 611 TGA_WRITE_REG(0, TGA_CLOCK_REG); 612 } 613 614 if (f <= 120000) { 615 TGA_WRITE_REG(0, TGA_CLOCK_REG); 616 TGA_WRITE_REG(0, TGA_CLOCK_REG); 617 } 618 else if (f <= 200000) { 619 TGA_WRITE_REG(1, TGA_CLOCK_REG); 620 TGA_WRITE_REG(0, TGA_CLOCK_REG); 621 } 622 else { 623 TGA_WRITE_REG(0, TGA_CLOCK_REG); 624 TGA_WRITE_REG(1, TGA_CLOCK_REG); 625 } 626 627 TGA_WRITE_REG(1, TGA_CLOCK_REG); 628 TGA_WRITE_REG(0, TGA_CLOCK_REG); 629 TGA_WRITE_REG(0, TGA_CLOCK_REG); 630 TGA_WRITE_REG(1, TGA_CLOCK_REG); 631 TGA_WRITE_REG(0, TGA_CLOCK_REG); 632 TGA_WRITE_REG(1, TGA_CLOCK_REG); 633 634 target = (f << shift) / TGA_PLL_BASE_FREQ; 635 min_diff = TGA_PLL_MAX_FREQ; 636 637 r = 7 / target; 638 if (!r) 639 r = 1; 640 641 base = target * r; 642 while (base < 449) { 643 for (n = base < 7 ? 7 : base ; n < base + target && n < 449; n++) { 644 m = ((n + 3) / 7) - 1; 645 a = 0; 646 DIFFCHECK((m + 1) * 7); 647 m++; 648 DIFFCHECK((m + 1) * 7); 649 m = (n / 6) - 1; 650 if( (a = n % 6)) 651 DIFFCHECK( n ); 652 } 653 r++; 654 base += target; 655 } 656 657 vr--; 658 659 for( r=0; r<8 ; r++) { 660 TGA_WRITE_REG((vm >> r) & 1, TGA_CLOCK_REG); 661 } 662 for( r=0; r<8 ; r++) { 663 TGA_WRITE_REG((va >> r) & 1, TGA_CLOCK_REG); 664 } 665 for( r=0; r<7 ; r++) { 666 TGA_WRITE_REG((vr >> r) & 1, TGA_CLOCK_REG); 667 } 668 TGA_WRITE_REG(((vr >> 7) & 1)|2, TGA_CLOCK_REG); 669} 670 671 672static int tgafb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue, 673 u_int *transp, struct fb_info *info) 674{ 675 if (regno > 255) 676 return 1; 677 *red = (palette[regno].red<<8) | palette[regno].red; 678 *green = (palette[regno].green<<8) | palette[regno].green; 679 *blue = (palette[regno].blue<<8) | palette[regno].blue; 680 *transp = 0; 681 return 0; 682} 683 684 685static int tgafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 686 u_int transp, struct fb_info *info) 687{ 688 if (regno > 255) 689 return 1; 690 red >>= 8; 691 green >>= 8; 692 blue >>= 8; 693 palette[regno].red = red; 694 palette[regno].green = green; 695 palette[regno].blue = blue; 696 697#ifdef FBCON_HAS_CFB32 698 if (regno < 16 && fb_info.tga_type != TGA_TYPE_8PLANE) 699 fbcon_cfb32_cmap[regno] = (red << 16) | (green << 8) | blue; 700#endif 701 702 if (fb_info.tga_type == TGA_TYPE_8PLANE) { 703 BT485_WRITE(regno, BT485_ADDR_PAL_WRITE); 704 TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); 705 TGA_WRITE_REG(red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 706 TGA_WRITE_REG(green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 707 TGA_WRITE_REG(blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 708 } 709 /* How to set a single color register on 24-plane cards?? */ 710 711 return 0; 712} 713 714 715static int tgafb_set_cmap(struct fb_cmap *cmap, int kspc, int con, 716 struct fb_info *info) 717{ 718 int err; 719 720 if (!fb_display[con].cmap.len) { /* no colormap allocated? */ 721 if ((err = fb_alloc_cmap(&fb_display[con].cmap, 256, 0))) 722 return err; 723 } 724 if (con == currcon) { /* current console? */ 725 err = fb_set_cmap(cmap, kspc, tgafb_setcolreg, info); 726 if (fb_info.tga_type != TGA_TYPE_8PLANE) 727 tgafb_update_palette(); 728 return err; 729 } else 730 fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1); 731 return 0; 732} 733 734static void tgafb_update_palette(void) 735{ 736 int i; 737 738 BT463_LOAD_ADDR(0x0000); 739 TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG); 740 741 for (i = 0; i < 256; i++) { 742 TGA_WRITE_REG(palette[i].red|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 743 TGA_WRITE_REG(palette[i].green|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 744 TGA_WRITE_REG(palette[i].blue|(BT463_PALETTE<<10), TGA_RAMDAC_REG); 745 } 746} 747 748 749static int tgafb_blank(int blank, struct fb_info_gen *info) 750{ 751 static int tga_vesa_blanked = 0; 752 u32 vhcr, vvcr, vvvr; 753 unsigned long flags; 754 755 save_flags(flags); 756 cli(); 757 758 vhcr = TGA_READ_REG(TGA_HORIZ_REG); 759 vvcr = TGA_READ_REG(TGA_VERT_REG); 760 vvvr = TGA_READ_REG(TGA_VALID_REG) & ~(TGA_VALID_VIDEO | TGA_VALID_BLANK); 761 762 switch (blank) { 763 case 0: /* Unblanking */ 764 if (tga_vesa_blanked) { 765 TGA_WRITE_REG(vhcr & 0xbfffffff, TGA_HORIZ_REG); 766 TGA_WRITE_REG(vvcr & 0xbfffffff, TGA_VERT_REG); 767 tga_vesa_blanked = 0; 768 } 769 TGA_WRITE_REG(vvvr | TGA_VALID_VIDEO, TGA_VALID_REG); 770 break; 771 772 case 1: /* Normal blanking */ 773 TGA_WRITE_REG(vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG); 774 break; 775 776 case 2: /* VESA blank (vsync off) */ 777 TGA_WRITE_REG(vvcr | 0x40000000, TGA_VERT_REG); 778 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 779 tga_vesa_blanked = 1; 780 break; 781 782 case 3: /* VESA blank (hsync off) */ 783 TGA_WRITE_REG(vhcr | 0x40000000, TGA_HORIZ_REG); 784 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 785 tga_vesa_blanked = 1; 786 break; 787 788 case 4: /* Poweroff */ 789 TGA_WRITE_REG(vhcr | 0x40000000, TGA_HORIZ_REG); 790 TGA_WRITE_REG(vvcr | 0x40000000, TGA_VERT_REG); 791 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 792 tga_vesa_blanked = 1; 793 break; 794 } 795 796 restore_flags(flags); 797 return 0; 798} 799 800 801static void tgafb_set_disp(const void *fb_par, struct display *disp, 802 struct fb_info_gen *info) 803{ 804 disp->screen_base = (char *)fb_info.tga_fb_base; 805 switch (fb_info.tga_type) { 806#ifdef FBCON_HAS_CFB8 807 case TGA_TYPE_8PLANE: 808 disp->dispsw = &fbcon_cfb8; 809 break; 810#endif 811#ifdef FBCON_HAS_CFB32 812 case TGA_TYPE_24PLANE: 813 case TGA_TYPE_24PLUSZ: 814 disp->dispsw = &fbcon_cfb32; 815 disp->dispsw_data = &fbcon_cfb32_cmap; 816 break; 817#endif 818 default: 819 disp->dispsw = &fbcon_dummy; 820 } 821 822 disp->scrollmode = SCROLL_YREDRAW; 823} 824 825 826struct fbgen_hwswitch tgafb_hwswitch = { 827 tgafb_detect, tgafb_encode_fix, tgafb_decode_var, tgafb_encode_var, tgafb_get_par, 828 tgafb_set_par, tgafb_getcolreg, tgafb_setcolreg, NULL, tgafb_blank, 829 tgafb_set_disp 830}; 831 832 833 /* 834 * Hardware Independent functions 835 */ 836 837 838 /* 839 * Frame buffer operations 840 */ 841 842static struct fb_ops tgafb_ops = { 843 owner: THIS_MODULE, 844 fb_get_fix: fbgen_get_fix, 845 fb_get_var: fbgen_get_var, 846 fb_set_var: fbgen_set_var, 847 fb_get_cmap: fbgen_get_cmap, 848 fb_set_cmap: tgafb_set_cmap, 849}; 850 851 852#ifndef MODULE 853 /* 854 * Setup 855 */ 856 857int __init tgafb_setup(char *options) { 858 char *this_opt; 859 int i; 860 861 if (options && *options) { 862 while ((this_opt = strsep(&options, ",")) != NULL) { 863 if (!*this_opt) { continue; } 864 865 if (!strncmp(this_opt, "font:", 5)) { 866 strncpy(default_fontname, this_opt+5, sizeof default_fontname); 867 } 868 869 else if (!strncmp(this_opt, "mode:", 5)) { 870 for (i = 0; i < NUM_TOTAL_MODES; i++) { 871 if (!strcmp(this_opt+5, tgafb_predefined[i].name)) 872 default_var = tgafb_predefined[i].var; 873 default_var_valid = 1; 874 } 875 } 876 877 else { 878 printk(KERN_ERR "tgafb: unknown parameter %s\n", this_opt); 879 } 880 } 881 } 882 return 0; 883} 884#endif 885 886 887 /* 888 * Initialisation 889 */ 890 891int __init tgafb_init(void) 892{ 893 struct pci_dev *pdev; 894 895 pdev = pci_find_device(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, NULL); 896 if (!pdev) 897 return -ENXIO; 898 899 /* divine board type */ 900 901 fb_info.tga_mem_base = (unsigned long)ioremap(pdev->resource[0].start, 0); 902 fb_info.tga_type = (readl(fb_info.tga_mem_base) >> 12) & 0x0f; 903 fb_info.tga_regs_base = fb_info.tga_mem_base + TGA_REGS_OFFSET; 904 fb_info.tga_fb_base = (fb_info.tga_mem_base 905 + fb_offset_presets[fb_info.tga_type]); 906 pci_read_config_byte(pdev, PCI_REVISION_ID, &fb_info.tga_chip_rev); 907 908 /* setup framebuffer */ 909 910 fb_info.gen.info.node = -1; 911 fb_info.gen.info.flags = FBINFO_FLAG_DEFAULT; 912 fb_info.gen.info.fbops = &tgafb_ops; 913 fb_info.gen.info.disp = &disp; 914 fb_info.gen.info.changevar = NULL; 915 fb_info.gen.info.switch_con = &fbgen_switch; 916 fb_info.gen.info.updatevar = &fbgen_update_var; 917 fb_info.gen.info.blank = &fbgen_blank; 918 strcpy(fb_info.gen.info.fontname, default_fontname); 919 fb_info.gen.parsize = sizeof (struct tgafb_par); 920 fb_info.gen.fbhw = &tgafb_hwswitch; 921 fb_info.gen.fbhw->detect(); 922 923 printk (KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n", fb_info.tga_chip_rev); 924 printk (KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n", 925 pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 926 927 switch (fb_info.tga_type) 928 { 929 case TGA_TYPE_8PLANE: 930 strcpy (fb_info.gen.info.modename,"Digital ZLXp-E1"); 931 break; 932 933 case TGA_TYPE_24PLANE: 934 strcpy (fb_info.gen.info.modename,"Digital ZLXp-E2"); 935 break; 936 937 case TGA_TYPE_24PLUSZ: 938 strcpy (fb_info.gen.info.modename,"Digital ZLXp-E3"); 939 break; 940 } 941 942 /* This should give a reasonable default video mode */ 943 944 if (!default_var_valid) { 945 default_var = tgafb_predefined[0].var; 946 } 947 fbgen_get_var(&disp.var, -1, &fb_info.gen.info); 948 disp.var.activate = FB_ACTIVATE_NOW; 949 fbgen_do_set_var(&disp.var, 1, &fb_info.gen); 950 fbgen_set_disp(-1, &fb_info.gen); 951 fbgen_install_cmap(0, &fb_info.gen); 952 if (register_framebuffer(&fb_info.gen.info) < 0) 953 return -EINVAL; 954 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n", 955 GET_FB_IDX(fb_info.gen.info.node), fb_info.gen.info.modename, 956 pdev->resource[0].start); 957 return 0; 958} 959 960 961 /* 962 * Cleanup 963 */ 964 965void __exit tgafb_cleanup(void) 966{ 967 unregister_framebuffer(&fb_info.gen.info); 968} 969 970 971 /* 972 * Modularisation 973 */ 974 975#ifdef MODULE 976MODULE_LICENSE("GPL"); 977module_init(tgafb_init); 978#endif 979 980module_exit(tgafb_cleanup); 981