1#ifndef __LINUX_UHCI_H 2#define __LINUX_UHCI_H 3 4#include <linux/list.h> 5#include <linux/usb.h> 6 7/* 8 * Universal Host Controller Interface data structures and defines 9 */ 10 11/* Command register */ 12#define USBCMD 0 13#define USBCMD_RS 0x0001 /* Run/Stop */ 14#define USBCMD_HCRESET 0x0002 /* Host reset */ 15#define USBCMD_GRESET 0x0004 /* Global reset */ 16#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 17#define USBCMD_FGR 0x0010 /* Force Global Resume */ 18#define USBCMD_SWDBG 0x0020 /* SW Debug mode */ 19#define USBCMD_CF 0x0040 /* Config Flag (sw only) */ 20#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ 21 22/* Status register */ 23#define USBSTS 2 24#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ 25#define USBSTS_ERROR 0x0002 /* Interrupt due to error */ 26#define USBSTS_RD 0x0004 /* Resume Detect */ 27#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */ 28#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */ 29#define USBSTS_HCH 0x0020 /* HC Halted */ 30 31/* Interrupt enable register */ 32#define USBINTR 4 33#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ 34#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 35#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ 36#define USBINTR_SP 0x0008 /* Short packet interrupt enable */ 37 38#define USBFRNUM 6 39#define USBFLBASEADD 8 40#define USBSOF 12 41 42/* USB port status and control registers */ 43#define USBPORTSC1 16 44#define USBPORTSC2 18 45#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */ 46#define USBPORTSC_CSC 0x0002 /* Connect Status Change */ 47#define USBPORTSC_PE 0x0004 /* Port Enable */ 48#define USBPORTSC_PEC 0x0008 /* Port Enable Change */ 49#define USBPORTSC_LS 0x0030 /* Line Status */ 50#define USBPORTSC_RD 0x0040 /* Resume Detect */ 51#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ 52#define USBPORTSC_PR 0x0200 /* Port Reset */ 53#define USBPORTSC_SUSP 0x1000 /* Suspend */ 54 55/* Legacy support register */ 56#define USBLEGSUP 0xc0 57#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 58 59#define UHCI_NULL_DATA_SIZE 0x7FF /* for UHCI controller TD */ 60 61#define UHCI_PTR_BITS 0x000F 62#define UHCI_PTR_TERM 0x0001 63#define UHCI_PTR_QH 0x0002 64#define UHCI_PTR_DEPTH 0x0004 65 66#define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ 67#define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ 68#define CAN_SCHEDULE_FRAMES 1000 /* how far future frames can be scheduled */ 69 70struct uhci_frame_list { 71 __u32 frame[UHCI_NUMFRAMES]; 72 73 void *frame_cpu[UHCI_NUMFRAMES]; 74 75 dma_addr_t dma_handle; 76}; 77 78struct urb_priv; 79 80struct uhci_qh { 81 /* Hardware fields */ 82 __u32 link; /* Next queue */ 83 __u32 element; /* Queue element pointer */ 84 85 /* Software fields */ 86 dma_addr_t dma_handle; 87 88 struct usb_device *dev; 89 struct urb_priv *urbp; 90 91 struct list_head list; /* P: uhci->frame_list_lock */ 92 struct list_head remove_list; /* P: uhci->remove_list_lock */ 93} __attribute__((aligned(16))); 94 95/* 96 * for TD <status>: 97 */ 98#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ 99#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ 100#define TD_CTRL_C_ERR_SHIFT 27 101#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ 102#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ 103#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ 104#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ 105#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ 106#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ 107#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ 108#define TD_CTRL_NAK (1 << 19) /* NAK Received */ 109#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ 110#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ 111#define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ 112 113#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ 114 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) 115 116#define uhci_status_bits(ctrl_sts) (ctrl_sts & 0xFE0000) 117#define uhci_actual_length(ctrl_sts) ((ctrl_sts + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */ 118 119/* 120 * for TD <info>: (a.k.a. Token) 121 */ 122#define TD_TOKEN_TOGGLE_SHIFT 19 123#define TD_TOKEN_TOGGLE (1 << 19) 124#define TD_TOKEN_PID_MASK 0xFF 125#define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n - 1 */ 126 127#define uhci_maxlen(token) ((token) >> 21) 128#define uhci_expected_length(info) (((info >> 21) + 1) & TD_TOKEN_EXPLEN_MASK) /* 1-based */ 129#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) 130#define uhci_endpoint(token) (((token) >> 15) & 0xf) 131#define uhci_devaddr(token) (((token) >> 8) & 0x7f) 132#define uhci_devep(token) (((token) >> 8) & 0x7ff) 133#define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) 134#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) 135#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) 136 137/* 138 * The documentation says "4 words for hardware, 4 words for software". 139 * 140 * That's silly, the hardware doesn't care. The hardware only cares that 141 * the hardware words are 16-byte aligned, and we can have any amount of 142 * sw space after the TD entry as far as I can tell. 143 * 144 * But let's just go with the documentation, at least for 32-bit machines. 145 * On 64-bit machines we probably want to take advantage of the fact that 146 * hw doesn't really care about the size of the sw-only area. 147 * 148 * Alas, not anymore, we have more than 4 words for software, woops. 149 * Everything still works tho, surprise! -jerdfelt 150 */ 151struct uhci_td { 152 /* Hardware fields */ 153 __u32 link; 154 __u32 status; 155 __u32 info; 156 __u32 buffer; 157 158 /* Software fields */ 159 dma_addr_t dma_handle; 160 161 struct usb_device *dev; 162 struct urb *urb; 163 164 struct list_head list; /* P: urb->lock */ 165 166 int frame; 167 struct list_head fl_list; /* P: uhci->frame_list_lock */ 168} __attribute__((aligned(16))); 169 170/* 171 * There are various standard queues. We set up several different 172 * queues for each of the three basic queue types: interrupt, 173 * control, and bulk. 174 * 175 * - There are various different interrupt latencies: ranging from 176 * every other USB frame (2 ms apart) to every 256 USB frames (ie 177 * 256 ms apart). Make your choice according to how obnoxious you 178 * want to be on the wire, vs how critical latency is for you. 179 * - The control list is done every frame. 180 * - There are 4 bulk lists, so that up to four devices can have a 181 * bulk list of their own and when run concurrently all four lists 182 * will be be serviced. 183 * 184 * This is a bit misleading, there are various interrupt latencies, but they 185 * vary a bit, interrupt2 isn't exactly 2ms, it can vary up to 4ms since the 186 * other queues can "override" it. interrupt4 can vary up to 8ms, etc. Minor 187 * problem 188 * 189 * In the case of the root hub, these QH's are just head's of qh's. Don't 190 * be scared, it kinda makes sense. Look at this wonderful picture care of 191 * Linus: 192 * 193 * generic- -> dev1- -> generic- -> dev1- -> control- -> bulk- -> ... 194 * iso-QH iso-QH irq-QH irq-QH QH QH 195 * | | | | | | 196 * End dev1-iso-TD1 End dev1-irq-TD1 ... ... 197 * | 198 * dev1-iso-TD2 199 * | 200 * .... 201 * 202 * This may vary a bit (the UHCI docs don't explicitly say you can put iso 203 * transfers in QH's and all of their pictures don't have that either) but 204 * other than that, that is what we're doing now 205 * 206 * And now we don't put Iso transfers in QH's, so we don't waste one on it 207 * --jerdfelt 208 * 209 * To keep with Linus' nomenclature, this is called the QH skeleton. These 210 * labels (below) are only signficant to the root hub's QH's 211 */ 212 213#define UHCI_NUM_SKELTD 10 214#define skel_int1_td skeltd[0] 215#define skel_int2_td skeltd[1] 216#define skel_int4_td skeltd[2] 217#define skel_int8_td skeltd[3] 218#define skel_int16_td skeltd[4] 219#define skel_int32_td skeltd[5] 220#define skel_int64_td skeltd[6] 221#define skel_int128_td skeltd[7] 222#define skel_int256_td skeltd[8] 223#define skel_term_td skeltd[9] /* To work around PIIX UHCI bug */ 224 225#define UHCI_NUM_SKELQH 4 226#define skel_ls_control_qh skelqh[0] 227#define skel_hs_control_qh skelqh[1] 228#define skel_bulk_qh skelqh[2] 229#define skel_term_qh skelqh[3] 230 231/* 232 * Search tree for determining where <interval> fits in the 233 * skelqh[] skeleton. 234 * 235 * An interrupt request should be placed into the slowest skelqh[] 236 * which meets the interval/period/frequency requirement. 237 * An interrupt request is allowed to be faster than <interval> but not slower. 238 * 239 * For a given <interval>, this function returns the appropriate/matching 240 * skelqh[] index value. 241 * 242 * NOTE: For UHCI, we don't really need int256_qh since the maximum interval 243 * is 255 ms. However, we do need an int1_qh since 1 is a valid interval 244 * and we should meet that frequency when requested to do so. 245 * This will require some change(s) to the UHCI skeleton. 246 */ 247static inline int __interval_to_skel(int interval) 248{ 249 if (interval < 16) { 250 if (interval < 4) { 251 if (interval < 2) 252 return 0; /* int1 for 0-1 ms */ 253 return 1; /* int2 for 2-3 ms */ 254 } 255 if (interval < 8) 256 return 2; /* int4 for 4-7 ms */ 257 return 3; /* int8 for 8-15 ms */ 258 } 259 if (interval < 64) { 260 if (interval < 32) 261 return 4; /* int16 for 16-31 ms */ 262 return 5; /* int32 for 32-63 ms */ 263 } 264 if (interval < 128) 265 return 6; /* int64 for 64-127 ms */ 266 return 7; /* int128 for 128-255 ms (Max.) */ 267} 268 269struct virt_root_hub { 270 struct usb_device *dev; 271 int devnum; /* Address of Root Hub endpoint */ 272 struct urb *urb; 273 void *int_addr; 274 int send; 275 int interval; 276 int numports; 277 int c_p_r[8]; 278 struct timer_list rh_int_timer; 279}; 280 281/* 282 * This describes the full uhci information. 283 * 284 * Note how the "proper" USB information is just 285 * a subset of what the full implementation needs. 286 */ 287struct uhci { 288 struct pci_dev *dev; 289 290#ifdef CONFIG_PROC_FS 291 /* procfs */ 292 int num; 293 struct proc_dir_entry *proc_entry; 294#endif 295 296 /* Grabbed from PCI */ 297 int irq; 298 unsigned int io_addr; 299 unsigned int io_size; 300 301 struct pci_pool *qh_pool; 302 struct pci_pool *td_pool; 303 304 struct usb_bus *bus; 305 306 struct uhci_td *skeltd[UHCI_NUM_SKELTD]; /* Skeleton TD's */ 307 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QH's */ 308 309 spinlock_t frame_list_lock; 310 struct uhci_frame_list *fl; /* P: uhci->frame_list_lock */ 311 int fsbr; /* Full speed bandwidth reclamation */ 312 unsigned long fsbrtimeout; /* FSBR delay */ 313 int is_suspended; 314 315 /* Main list of URB's currently controlled by this HC */ 316 spinlock_t urb_list_lock; 317 struct list_head urb_list; /* P: uhci->urb_list_lock */ 318 319 /* List of QH's that are done, but waiting to be unlinked (race) */ 320 spinlock_t qh_remove_list_lock; 321 struct list_head qh_remove_list; /* P: uhci->qh_remove_list_lock */ 322 323 /* List of asynchronously unlinked URB's */ 324 spinlock_t urb_remove_list_lock; 325 struct list_head urb_remove_list; /* P: uhci->urb_remove_list_lock */ 326 327 /* List of URB's awaiting completion callback */ 328 spinlock_t complete_list_lock; 329 struct list_head complete_list; /* P: uhci->complete_list_lock */ 330 331 struct virt_root_hub rh; /* private data of the virtual root hub */ 332}; 333 334struct urb_priv { 335 struct urb *urb; 336 struct usb_device *dev; 337 338 dma_addr_t setup_packet_dma_handle; 339 dma_addr_t transfer_buffer_dma_handle; 340 341 struct uhci_qh *qh; /* QH for this URB */ 342 struct list_head td_list; /* P: urb->lock */ 343 344 int fsbr : 1; /* URB turned on FSBR */ 345 int fsbr_timeout : 1; /* URB timed out on FSBR */ 346 int queued : 1; /* QH was queued (not linked in) */ 347 int short_control_packet : 1; /* If we get a short packet during */ 348 /* a control transfer, retrigger */ 349 /* the status phase */ 350 351 int status; /* Final status */ 352 353 unsigned long inserttime; /* In jiffies */ 354 unsigned long fsbrtime; /* In jiffies */ 355 356 struct list_head queue_list; /* P: uhci->frame_list_lock */ 357 struct list_head complete_list; /* P: uhci->complete_list_lock */ 358}; 359 360/* 361 * Locking in uhci.c 362 * 363 * spinlocks are used extensively to protect the many lists and data 364 * structures we have. It's not that pretty, but it's necessary. We 365 * need to be done with all of the locks (except complete_list_lock) when 366 * we call urb->complete. I've tried to make it simple enough so I don't 367 * have to spend hours racking my brain trying to figure out if the 368 * locking is safe. 369 * 370 * Here's the safe locking order to prevent deadlocks: 371 * 372 * #1 uhci->urb_list_lock 373 * #2 urb->lock 374 * #3 uhci->urb_remove_list_lock, uhci->frame_list_lock, 375 * uhci->qh_remove_list_lock 376 * #4 uhci->complete_list_lock 377 * 378 * If you're going to grab 2 or more locks at once, ALWAYS grab the lock 379 * at the lowest level FIRST and NEVER grab locks at the same level at the 380 * same time. 381 * 382 * So, if you need uhci->urb_list_lock, grab it before you grab urb->lock 383 */ 384 385/* ------------------------------------------------------------------------- 386 Virtual Root HUB 387 ------------------------------------------------------------------------- */ 388/* destination of request */ 389#define RH_DEVICE 0x00 390#define RH_INTERFACE 0x01 391#define RH_ENDPOINT 0x02 392#define RH_OTHER 0x03 393 394#define RH_CLASS 0x20 395#define RH_VENDOR 0x40 396 397/* Requests: bRequest << 8 | bmRequestType */ 398#define RH_GET_STATUS 0x0080 399#define RH_CLEAR_FEATURE 0x0100 400#define RH_SET_FEATURE 0x0300 401#define RH_SET_ADDRESS 0x0500 402#define RH_GET_DESCRIPTOR 0x0680 403#define RH_SET_DESCRIPTOR 0x0700 404#define RH_GET_CONFIGURATION 0x0880 405#define RH_SET_CONFIGURATION 0x0900 406#define RH_GET_STATE 0x0280 407#define RH_GET_INTERFACE 0x0A80 408#define RH_SET_INTERFACE 0x0B00 409#define RH_SYNC_FRAME 0x0C80 410/* Our Vendor Specific Request */ 411#define RH_SET_EP 0x2000 412 413/* Hub port features */ 414#define RH_PORT_CONNECTION 0x00 415#define RH_PORT_ENABLE 0x01 416#define RH_PORT_SUSPEND 0x02 417#define RH_PORT_OVER_CURRENT 0x03 418#define RH_PORT_RESET 0x04 419#define RH_PORT_POWER 0x08 420#define RH_PORT_LOW_SPEED 0x09 421#define RH_C_PORT_CONNECTION 0x10 422#define RH_C_PORT_ENABLE 0x11 423#define RH_C_PORT_SUSPEND 0x12 424#define RH_C_PORT_OVER_CURRENT 0x13 425#define RH_C_PORT_RESET 0x14 426 427/* Hub features */ 428#define RH_C_HUB_LOCAL_POWER 0x00 429#define RH_C_HUB_OVER_CURRENT 0x01 430#define RH_DEVICE_REMOTE_WAKEUP 0x00 431#define RH_ENDPOINT_STALL 0x01 432 433/* Our Vendor Specific feature */ 434#define RH_REMOVE_EP 0x00 435 436#define RH_ACK 0x01 437#define RH_REQ_ERR -1 438#define RH_NACK 0x00 439 440#endif 441 442