1/* 2 * Intel i810 and friends ICH driver for Linux 3 * Alan Cox <alan@redhat.com> 4 * 5 * Built from: 6 * Low level code: Zach Brown (original nonworking i810 OSS driver) 7 * Jaroslav Kysela <perex@suse.cz> (working ALSA driver) 8 * 9 * Framework: Thomas Sailer <sailer@ife.ee.ethz.ch> 10 * Extended by: Zach Brown <zab@redhat.com> 11 * and others.. 12 * 13 * Hardware Provided By: 14 * Analog Devices (A major AC97 codec maker) 15 * Intel Corp (you've probably heard of them already) 16 * 17 * AC97 clues and assistance provided by 18 * Analog Devices 19 * Zach 'Fufu' Brown 20 * Jeff Garzik 21 * 22 * This program is free software; you can redistribute it and/or modify 23 * it under the terms of the GNU General Public License as published by 24 * the Free Software Foundation; either version 2 of the License, or 25 * (at your option) any later version. 26 * 27 * This program is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * GNU General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 35 * 36 * 37 * Intel 810 theory of operation 38 * 39 * The chipset provides three DMA channels that talk to an AC97 40 * CODEC (AC97 is a digital/analog mixer standard). At its simplest 41 * you get 48Khz audio with basic volume and mixer controls. At the 42 * best you get rate adaption in the codec. We set the card up so 43 * that we never take completion interrupts but instead keep the card 44 * chasing its tail around a ring buffer. This is needed for mmap 45 * mode audio and happens to work rather well for non-mmap modes too. 46 * 47 * The board has one output channel for PCM audio (supported) and 48 * a stereo line in and mono microphone input. Again these are normally 49 * locked to 48Khz only. Right now recording is not finished. 50 * 51 * There is no midi support, no synth support. Use timidity. To get 52 * esd working you need to use esd -r 48000 as it won't probe 48KHz 53 * by default. mpg123 can't handle 48Khz only audio so use xmms. 54 * 55 * Fix The Sound On Dell 56 * 57 * Not everyone uses 48KHz. We know of no way to detect this reliably 58 * and certainly not to get the right data. If your i810 audio sounds 59 * stupid you may need to investigate other speeds. According to Analog 60 * they tend to use a 14.318MHz clock which gives you a base rate of 61 * 41194Hz. 62 * 63 * This is available via the 'ftsodell=1' option. 64 * 65 * If you need to force a specific rate set the clocking= option 66 * 67 * This driver is cursed. (Ben LaHaise) 68 */ 69 70#include <linux/module.h> 71#include <linux/version.h> 72#include <linux/string.h> 73#include <linux/ctype.h> 74#include <linux/ioport.h> 75#include <linux/sched.h> 76#include <linux/delay.h> 77#include <linux/sound.h> 78#include <linux/slab.h> 79#include <linux/soundcard.h> 80#include <linux/pci.h> 81#include <asm/io.h> 82#include <asm/dma.h> 83#include <linux/init.h> 84#include <linux/poll.h> 85#include <linux/spinlock.h> 86#include <linux/smp_lock.h> 87#include <linux/ac97_codec.h> 88#include <linux/wrapper.h> 89#include <asm/uaccess.h> 90#include <asm/hardirq.h> 91 92#ifndef PCI_DEVICE_ID_INTEL_82801 93#define PCI_DEVICE_ID_INTEL_82801 0x2415 94#endif 95#ifndef PCI_DEVICE_ID_INTEL_82901 96#define PCI_DEVICE_ID_INTEL_82901 0x2425 97#endif 98#ifndef PCI_DEVICE_ID_INTEL_ICH2 99#define PCI_DEVICE_ID_INTEL_ICH2 0x2445 100#endif 101#ifndef PCI_DEVICE_ID_INTEL_ICH3 102#define PCI_DEVICE_ID_INTEL_ICH3 0x2485 103#endif 104#ifndef PCI_DEVICE_ID_INTEL_ICH4 105#define PCI_DEVICE_ID_INTEL_ICH4 0x24c5 106#endif 107#ifndef PCI_DEVICE_ID_INTEL_440MX 108#define PCI_DEVICE_ID_INTEL_440MX 0x7195 109#endif 110#ifndef PCI_DEVICE_ID_SI_7012 111#define PCI_DEVICE_ID_SI_7012 0x7012 112#endif 113#ifndef PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO 114#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO 0x01b1 115#endif 116#ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 117#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a 118#endif 119#ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 120#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da 121#endif 122#ifndef PCI_DEVICE_ID_AMD_768_AUDIO 123#define PCI_DEVICE_ID_AMD_768_AUDIO 0x7445 124#endif 125 126static int ftsodell=0; 127static int strict_clocking=0; 128static unsigned int clocking=0; 129static int spdif_locked=0; 130 131//#define DEBUG 132//#define DEBUG2 133//#define DEBUG_INTERRUPTS 134//#define DEBUG_MMAP 135 136#define ADC_RUNNING 1 137#define DAC_RUNNING 2 138 139#define I810_FMT_16BIT 1 140#define I810_FMT_STEREO 2 141#define I810_FMT_MASK 3 142 143#define SPDIF_ON 0x0004 144#define SURR_ON 0x0010 145#define CENTER_LFE_ON 0x0020 146#define VOL_MUTED 0x8000 147 148/* the 810's array of pointers to data buffers */ 149 150struct sg_item { 151#define BUSADDR_MASK 0xFFFFFFFE 152 u32 busaddr; 153#define CON_IOC 0x80000000 /* interrupt on completion */ 154#define CON_BUFPAD 0x40000000 /* pad underrun with last sample, else 0 */ 155#define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */ 156 u32 control; 157}; 158 159/* an instance of the i810 channel */ 160#define SG_LEN 32 161struct i810_channel 162{ 163 /* these sg guys should probably be allocated 164 seperately as nocache. Must be 8 byte aligned */ 165 struct sg_item sg[SG_LEN]; /* 32*8 */ 166 u32 offset; /* 4 */ 167 u32 port; /* 4 */ 168 u32 used; 169 u32 num; 170}; 171 172/* 173 * we have 3 seperate dma engines. pcm in, pcm out, and mic. 174 * each dma engine has controlling registers. These goofy 175 * names are from the datasheet, but make it easy to write 176 * code while leafing through it. 177 */ 178 179#define ENUM_ENGINE(PRE,DIG) \ 180enum { \ 181 PRE##_BDBAR = 0x##DIG##0, /* Buffer Descriptor list Base Address */ \ 182 PRE##_CIV = 0x##DIG##4, /* Current Index Value */ \ 183 PRE##_LVI = 0x##DIG##5, /* Last Valid Index */ \ 184 PRE##_SR = 0x##DIG##6, /* Status Register */ \ 185 PRE##_PICB = 0x##DIG##8, /* Position In Current Buffer */ \ 186 PRE##_PIV = 0x##DIG##a, /* Prefetched Index Value */ \ 187 PRE##_CR = 0x##DIG##b /* Control Register */ \ 188} 189 190ENUM_ENGINE(OFF,0); /* Offsets */ 191ENUM_ENGINE(PI,0); /* PCM In */ 192ENUM_ENGINE(PO,1); /* PCM Out */ 193ENUM_ENGINE(MC,2); /* Mic In */ 194 195enum { 196 GLOB_CNT = 0x2c, /* Global Control */ 197 GLOB_STA = 0x30, /* Global Status */ 198 CAS = 0x34 /* Codec Write Semaphore Register */ 199}; 200 201/* interrupts for a dma engine */ 202#define DMA_INT_FIFO (1<<4) /* fifo under/over flow */ 203#define DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */ 204#define DMA_INT_LVI (1<<2) /* last valid done */ 205#define DMA_INT_CELV (1<<1) /* last valid is current */ 206#define DMA_INT_DCH (1) /* DMA Controller Halted (happens on LVI interrupts) */ 207#define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI) 208 209/* interrupts for the whole chip */ 210#define INT_SEC (1<<11) 211#define INT_PRI (1<<10) 212#define INT_MC (1<<7) 213#define INT_PO (1<<6) 214#define INT_PI (1<<5) 215#define INT_MO (1<<2) 216#define INT_NI (1<<1) 217#define INT_GPI (1<<0) 218#define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI) 219 220 221#define DRIVER_VERSION "0.21" 222 223/* magic numbers to protect our data structures */ 224#define I810_CARD_MAGIC 0x5072696E /* "Prin" */ 225#define I810_STATE_MAGIC 0x63657373 /* "cess" */ 226#define I810_DMA_MASK 0xffffffff /* DMA buffer mask for pci_alloc_consist */ 227#define NR_HW_CH 3 228 229/* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */ 230#define NR_AC97 2 231 232/* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */ 233/* stream at a minimum for this card to be happy */ 234static const unsigned sample_size[] = { 1, 2, 2, 4 }; 235/* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */ 236/* values are one less than might be expected */ 237static const unsigned sample_shift[] = { -1, 0, 0, 1 }; 238 239enum { 240 ICH82801AA = 0, 241 ICH82901AB, 242 INTEL440MX, 243 INTELICH2, 244 INTELICH3, 245 INTELICH4, 246 SI7012, 247 NVIDIA_NFORCE, 248 AMD768, 249 AMD8111 250}; 251 252static char * card_names[] = { 253 "Intel ICH 82801AA", 254 "Intel ICH 82901AB", 255 "Intel 440MX", 256 "Intel ICH2", 257 "Intel ICH3", 258 "Intel ICH4", 259 "SiS 7012", 260 "NVIDIA nForce Audio", 261 "AMD 768", 262 "AMD-8111 IOHub" 263}; 264 265static struct pci_device_id i810_pci_tbl [] __initdata = { 266 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801, 267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82801AA}, 268 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82901, 269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82901AB}, 270 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_440MX, 271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTEL440MX}, 272 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, 273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH2}, 274 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH3, 275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH3}, 276 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, 277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4}, 278 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7012, 279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SI7012}, 280 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, 281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE}, 282 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, 283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE}, 284 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, 285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE}, 286 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_768_AUDIO, 287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD768}, 288 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_AC97, 289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD8111}, 290 {0,} 291}; 292 293MODULE_DEVICE_TABLE (pci, i810_pci_tbl); 294 295#ifdef CONFIG_PM 296#define PM_SUSPENDED(card) (card->pm_suspended) 297#else 298#define PM_SUSPENDED(card) (0) 299#endif 300 301/* "software" or virtual channel, an instance of opened /dev/dsp */ 302struct i810_state { 303 unsigned int magic; 304 struct i810_card *card; /* Card info */ 305 306 /* single open lock mechanism, only used for recording */ 307 struct semaphore open_sem; 308 wait_queue_head_t open_wait; 309 310 /* file mode */ 311 mode_t open_mode; 312 313 /* virtual channel number */ 314 int virt; 315 316#ifdef CONFIG_PM 317 unsigned int pm_saved_dac_rate,pm_saved_adc_rate; 318#endif 319 struct dmabuf { 320 /* wave sample stuff */ 321 unsigned int rate; 322 unsigned char fmt, enable, trigger; 323 324 /* hardware channel */ 325 struct i810_channel *read_channel; 326 struct i810_channel *write_channel; 327 328 /* OSS buffer management stuff */ 329 void *rawbuf; 330 dma_addr_t dma_handle; 331 unsigned buforder; 332 unsigned numfrag; 333 unsigned fragshift; 334 335 /* our buffer acts like a circular ring */ 336 unsigned hwptr; /* where dma last started, updated by update_ptr */ 337 unsigned swptr; /* where driver last clear/filled, updated by read/write */ 338 int count; /* bytes to be consumed or been generated by dma machine */ 339 unsigned total_bytes; /* total bytes dmaed by hardware */ 340 341 unsigned error; /* number of over/underruns */ 342 wait_queue_head_t wait; /* put process on wait queue when no more space in buffer */ 343 344 /* redundant, but makes calculations easier */ 345 /* what the hardware uses */ 346 unsigned dmasize; 347 unsigned fragsize; 348 unsigned fragsamples; 349 350 /* what we tell the user to expect */ 351 unsigned userfrags; 352 unsigned userfragsize; 353 354 /* OSS stuff */ 355 unsigned mapped:1; 356 unsigned ready:1; 357 unsigned update_flag; 358 unsigned ossfragsize; 359 unsigned ossmaxfrags; 360 unsigned subdivision; 361 } dmabuf; 362}; 363 364 365struct i810_card { 366 struct i810_channel channel[3]; 367 unsigned int magic; 368 369 /* We keep i810 cards in a linked list */ 370 struct i810_card *next; 371 372 /* The i810 has a certain amount of cross channel interaction 373 so we use a single per card lock */ 374 spinlock_t lock; 375 376 /* PCI device stuff */ 377 struct pci_dev * pci_dev; 378 u16 pci_id; 379#ifdef CONFIG_PM 380 u16 pm_suspended; 381 u32 pm_save_state[64/sizeof(u32)]; 382 int pm_saved_mixer_settings[SOUND_MIXER_NRDEVICES][NR_AC97]; 383#endif 384 /* soundcore stuff */ 385 int dev_audio; 386 387 /* structures for abstraction of hardware facilities, codecs, banks and channels*/ 388 struct ac97_codec *ac97_codec[NR_AC97]; 389 struct i810_state *states[NR_HW_CH]; 390 391 u16 ac97_features; 392 u16 ac97_status; 393 u16 channels; 394 395 /* hardware resources */ 396 unsigned long iobase; 397 unsigned long ac97base; 398 u32 irq; 399 400 /* Function support */ 401 struct i810_channel *(*alloc_pcm_channel)(struct i810_card *); 402 struct i810_channel *(*alloc_rec_pcm_channel)(struct i810_card *); 403 struct i810_channel *(*alloc_rec_mic_channel)(struct i810_card *); 404 void (*free_pcm_channel)(struct i810_card *, int chan); 405 406 /* We have a *very* long init time possibly, so use this to block */ 407 /* attempts to open our devices before we are ready (stops oops'es) */ 408 int initializing; 409}; 410 411static struct i810_card *devs = NULL; 412 413static int i810_open_mixdev(struct inode *inode, struct file *file); 414static int i810_ioctl_mixdev(struct inode *inode, struct file *file, 415 unsigned int cmd, unsigned long arg); 416static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg); 417static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data); 418 419static struct i810_channel *i810_alloc_pcm_channel(struct i810_card *card) 420{ 421 if(card->channel[1].used==1) 422 return NULL; 423 card->channel[1].used=1; 424 return &card->channel[1]; 425} 426 427static struct i810_channel *i810_alloc_rec_pcm_channel(struct i810_card *card) 428{ 429 if(card->channel[0].used==1) 430 return NULL; 431 card->channel[0].used=1; 432 return &card->channel[0]; 433} 434 435static struct i810_channel *i810_alloc_rec_mic_channel(struct i810_card *card) 436{ 437 if(card->channel[2].used==1) 438 return NULL; 439 card->channel[2].used=1; 440 return &card->channel[2]; 441} 442 443static void i810_free_pcm_channel(struct i810_card *card, int channel) 444{ 445 card->channel[channel].used=0; 446} 447 448static int i810_valid_spdif_rate ( struct ac97_codec *codec, int rate ) 449{ 450 unsigned long id = 0L; 451 452 id = (i810_ac97_get(codec, AC97_VENDOR_ID1) << 16); 453 id |= i810_ac97_get(codec, AC97_VENDOR_ID2) & 0xffff; 454#ifdef DEBUG 455 printk ( "i810_audio: codec = %s, codec_id = 0x%08lx\n", codec->name, id); 456#endif 457 switch ( id ) { 458 case 0x41445361: /* AD1886 */ 459 if (rate == 48000) { 460 return 1; 461 } 462 break; 463 default: /* all other codecs, until we know otherwiae */ 464 if (rate == 48000 || rate == 44100 || rate == 32000) { 465 return 1; 466 } 467 break; 468 } 469 return (0); 470} 471 472/* i810_set_spdif_output 473 * 474 * Configure the S/PDIF output transmitter. When we turn on 475 * S/PDIF, we turn off the analog output. This may not be 476 * the right thing to do. 477 * 478 * Assumptions: 479 * The DSP sample rate must already be set to a supported 480 * S/PDIF rate (32kHz, 44.1kHz, or 48kHz) or we abort. 481 */ 482static void i810_set_spdif_output(struct i810_state *state, int slots, int rate) 483{ 484 int vol; 485 int aud_reg; 486 struct ac97_codec *codec = state->card->ac97_codec[0]; 487 488 if(!(state->card->ac97_features & 4)) { 489#ifdef DEBUG 490 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not available.\n"); 491#endif 492 state->card->ac97_status &= ~SPDIF_ON; 493 } else { 494 if ( slots == -1 ) { /* Turn off S/PDIF */ 495 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS); 496 i810_ac97_set(codec, AC97_EXTENDED_STATUS, (aud_reg & ~AC97_EA_SPDIF)); 497 498 /* If the volume wasn't muted before we turned on S/PDIF, unmute it */ 499 if ( !(state->card->ac97_status & VOL_MUTED) ) { 500 aud_reg = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO); 501 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (aud_reg & ~VOL_MUTED)); 502 } 503 state->card->ac97_status &= ~(VOL_MUTED | SPDIF_ON); 504 return; 505 } 506 507 vol = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO); 508 state->card->ac97_status = vol & VOL_MUTED; 509 510 /* Set S/PDIF transmitter sample rate */ 511 aud_reg = i810_ac97_get(codec, AC97_SPDIF_CONTROL); 512 switch ( rate ) { 513 case 32000: 514 aud_reg = (aud_reg & AC97_SC_SPSR_MASK) | AC97_SC_SPSR_32K; 515 break; 516 case 44100: 517 aud_reg = (aud_reg & AC97_SC_SPSR_MASK) | AC97_SC_SPSR_44K; 518 break; 519 case 48000: 520 aud_reg = (aud_reg & AC97_SC_SPSR_MASK) | AC97_SC_SPSR_48K; 521 break; 522 default: 523#ifdef DEBUG 524 printk(KERN_WARNING "i810_audio: %d sample rate not supported by S/PDIF.\n", rate); 525#endif 526 /* turn off S/PDIF */ 527 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS); 528 i810_ac97_set(codec, AC97_EXTENDED_STATUS, (aud_reg & ~AC97_EA_SPDIF)); 529 state->card->ac97_status &= ~SPDIF_ON; 530 return; 531 } 532 533 i810_ac97_set(codec, AC97_SPDIF_CONTROL, aud_reg); 534 535 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS); 536 aud_reg = (aud_reg & AC97_EA_SLOT_MASK) | slots | AC97_EA_VRA | AC97_EA_SPDIF; 537 i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg); 538 state->card->ac97_status |= SPDIF_ON; 539 540 /* Check to make sure the configuration is valid */ 541 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS); 542 if ( ! (aud_reg & 0x0400) ) { 543#ifdef DEBUG 544 printk(KERN_WARNING "i810_audio: S/PDIF transmitter configuration not valid (0x%04x).\n", aud_reg); 545#endif 546 547 /* turn off S/PDIF */ 548 i810_ac97_set(codec, AC97_EXTENDED_STATUS, (aud_reg & ~AC97_EA_SPDIF)); 549 state->card->ac97_status &= ~SPDIF_ON; 550 return; 551 } 552 /* Mute the analog output */ 553 /* Should this only mute the PCM volume??? */ 554 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (vol | VOL_MUTED)); 555 } 556} 557 558/* i810_set_dac_channels 559 * 560 * Configure the codec's multi-channel DACs 561 * 562 * The logic is backwards. Setting the bit to 1 turns off the DAC. 563 * 564 * What about the ICH? We currently configure it using the 565 * SNDCTL_DSP_CHANNELS ioctl. If we're turnning on the DAC, 566 * does that imply that we want the ICH set to support 567 * these channels? 568 * 569 * TODO: 570 * vailidate that the codec really supports these DACs 571 * before turning them on. 572 */ 573static void i810_set_dac_channels(struct i810_state *state, int channel) 574{ 575 int aud_reg; 576 struct ac97_codec *codec = state->card->ac97_codec[0]; 577 578 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS); 579 aud_reg |= AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK; 580 state->card->ac97_status &= ~(SURR_ON | CENTER_LFE_ON); 581 582 switch ( channel ) { 583 case 2: /* always enabled */ 584 break; 585 case 4: 586 aud_reg &= ~AC97_EA_PRJ; 587 state->card->ac97_status |= SURR_ON; 588 break; 589 case 6: 590 aud_reg &= ~(AC97_EA_PRJ | AC97_EA_PRI | AC97_EA_PRK); 591 state->card->ac97_status |= SURR_ON | CENTER_LFE_ON; 592 break; 593 default: 594 break; 595 } 596 i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg); 597 598} 599 600 601/* set playback sample rate */ 602static unsigned int i810_set_dac_rate(struct i810_state * state, unsigned int rate) 603{ 604 struct dmabuf *dmabuf = &state->dmabuf; 605 u32 new_rate; 606 struct ac97_codec *codec=state->card->ac97_codec[0]; 607 608 if(!(state->card->ac97_features&0x0001)) 609 { 610 dmabuf->rate = clocking; 611#ifdef DEBUG 612 printk("Asked for %d Hz, but ac97_features says we only do %dHz. Sorry!\n", 613 rate,clocking); 614#endif 615 return clocking; 616 } 617 618 if (rate > 48000) 619 rate = 48000; 620 if (rate < 8000) 621 rate = 8000; 622 dmabuf->rate = rate; 623 624 /* 625 * Adjust for misclocked crap 626 */ 627 rate = ( rate * clocking)/48000; 628 if(strict_clocking && rate < 8000) { 629 rate = 8000; 630 dmabuf->rate = (rate * 48000)/clocking; 631 } 632 633 new_rate=ac97_set_dac_rate(codec, rate); 634 if(new_rate != rate) { 635 dmabuf->rate = (new_rate * 48000)/clocking; 636 } 637#ifdef DEBUG 638 printk("i810_audio: called i810_set_dac_rate : asked for %d, got %d\n", rate, dmabuf->rate); 639#endif 640 rate = new_rate; 641 return dmabuf->rate; 642} 643 644/* set recording sample rate */ 645static unsigned int i810_set_adc_rate(struct i810_state * state, unsigned int rate) 646{ 647 struct dmabuf *dmabuf = &state->dmabuf; 648 u32 new_rate; 649 struct ac97_codec *codec=state->card->ac97_codec[0]; 650 651 if(!(state->card->ac97_features&0x0001)) 652 { 653 dmabuf->rate = clocking; 654 return clocking; 655 } 656 657 if (rate > 48000) 658 rate = 48000; 659 if (rate < 8000) 660 rate = 8000; 661 dmabuf->rate = rate; 662 663 /* 664 * Adjust for misclocked crap 665 */ 666 667 rate = ( rate * clocking)/48000; 668 if(strict_clocking && rate < 8000) { 669 rate = 8000; 670 dmabuf->rate = (rate * 48000)/clocking; 671 } 672 673 new_rate = ac97_set_adc_rate(codec, rate); 674 675 if(new_rate != rate) { 676 dmabuf->rate = (new_rate * 48000)/clocking; 677 rate = new_rate; 678 } 679#ifdef DEBUG 680 printk("i810_audio: called i810_set_adc_rate : rate = %d/%d\n", dmabuf->rate, rate); 681#endif 682 return dmabuf->rate; 683} 684 685/* get current playback/recording dma buffer pointer (byte offset from LBA), 686 called with spinlock held! */ 687 688static inline unsigned i810_get_dma_addr(struct i810_state *state, int rec) 689{ 690 struct dmabuf *dmabuf = &state->dmabuf; 691 unsigned int civ, offset, port, port_picb, bytes = 2; 692 693 if (!dmabuf->enable) 694 return 0; 695 696 if (rec) 697 port = state->card->iobase + dmabuf->read_channel->port; 698 else 699 port = state->card->iobase + dmabuf->write_channel->port; 700 701 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012) { 702 port_picb = port + OFF_SR; 703 bytes = 1; 704 } else 705 port_picb = port + OFF_PICB; 706 707 do { 708 civ = inb(port+OFF_CIV) & 31; 709 offset = inw(port_picb); 710 /* Must have a delay here! */ 711 if(offset == 0) 712 udelay(1); 713 /* Reread both registers and make sure that that total 714 * offset from the first reading to the second is 0. 715 * There is an issue with SiS hardware where it will count 716 * picb down to 0, then update civ to the next value, 717 * then set the new picb to fragsize bytes. We can catch 718 * it between the civ update and the picb update, making 719 * it look as though we are 1 fragsize ahead of where we 720 * are. The next to we get the address though, it will 721 * be back in the right place, and we will suddenly think 722 * we just went forward dmasize - fragsize bytes, causing 723 * totally stupid *huge* dma overrun messages. We are 724 * assuming that the 1us delay is more than long enough 725 * that we won't have to worry about the chip still being 726 * out of sync with reality ;-) 727 */ 728 } while (civ != (inb(port+OFF_CIV) & 31) || offset != inw(port_picb)); 729 730 return (((civ + 1) * dmabuf->fragsize - (bytes * offset)) 731 % dmabuf->dmasize); 732} 733 734/* Stop recording (lock held) */ 735static inline void __stop_adc(struct i810_state *state) 736{ 737 struct dmabuf *dmabuf = &state->dmabuf; 738 struct i810_card *card = state->card; 739 740 dmabuf->enable &= ~ADC_RUNNING; 741 outb(0, card->iobase + PI_CR); 742 // wait for the card to acknowledge shutdown 743 while( inb(card->iobase + PI_CR) != 0 ) ; 744 // now clear any latent interrupt bits (like the halt bit) 745 if(card->pci_id == PCI_DEVICE_ID_SI_7012) 746 outb( inb(card->iobase + PI_PICB), card->iobase + PI_PICB ); 747 else 748 outb( inb(card->iobase + PI_SR), card->iobase + PI_SR ); 749 outl( inl(card->iobase + GLOB_STA) & INT_PI, card->iobase + GLOB_STA); 750} 751 752static void stop_adc(struct i810_state *state) 753{ 754 struct i810_card *card = state->card; 755 unsigned long flags; 756 757 spin_lock_irqsave(&card->lock, flags); 758 __stop_adc(state); 759 spin_unlock_irqrestore(&card->lock, flags); 760} 761 762static inline void __start_adc(struct i810_state *state) 763{ 764 struct dmabuf *dmabuf = &state->dmabuf; 765 766 if (dmabuf->count < dmabuf->dmasize && dmabuf->ready && !dmabuf->enable && 767 (dmabuf->trigger & PCM_ENABLE_INPUT)) { 768 dmabuf->enable |= ADC_RUNNING; 769 outb((1<<4) | (1<<2) | 1, state->card->iobase + PI_CR); 770 } 771} 772 773static void start_adc(struct i810_state *state) 774{ 775 struct i810_card *card = state->card; 776 unsigned long flags; 777 778 spin_lock_irqsave(&card->lock, flags); 779 __start_adc(state); 780 spin_unlock_irqrestore(&card->lock, flags); 781} 782 783/* stop playback (lock held) */ 784static inline void __stop_dac(struct i810_state *state) 785{ 786 struct dmabuf *dmabuf = &state->dmabuf; 787 struct i810_card *card = state->card; 788 789 dmabuf->enable &= ~DAC_RUNNING; 790 outb(0, card->iobase + PO_CR); 791 // wait for the card to acknowledge shutdown 792 while( inb(card->iobase + PO_CR) != 0 ) ; 793 // now clear any latent interrupt bits (like the halt bit) 794 if(card->pci_id == PCI_DEVICE_ID_SI_7012) 795 outb( inb(card->iobase + PO_PICB), card->iobase + PO_PICB ); 796 else 797 outb( inb(card->iobase + PO_SR), card->iobase + PO_SR ); 798 outl( inl(card->iobase + GLOB_STA) & INT_PO, card->iobase + GLOB_STA); 799} 800 801static void stop_dac(struct i810_state *state) 802{ 803 struct i810_card *card = state->card; 804 unsigned long flags; 805 806 spin_lock_irqsave(&card->lock, flags); 807 __stop_dac(state); 808 spin_unlock_irqrestore(&card->lock, flags); 809} 810 811static inline void __start_dac(struct i810_state *state) 812{ 813 struct dmabuf *dmabuf = &state->dmabuf; 814 815 if (dmabuf->count > 0 && dmabuf->ready && !dmabuf->enable && 816 (dmabuf->trigger & PCM_ENABLE_OUTPUT)) { 817 dmabuf->enable |= DAC_RUNNING; 818 outb((1<<4) | (1<<2) | 1, state->card->iobase + PO_CR); 819 } 820} 821static void start_dac(struct i810_state *state) 822{ 823 struct i810_card *card = state->card; 824 unsigned long flags; 825 826 spin_lock_irqsave(&card->lock, flags); 827 __start_dac(state); 828 spin_unlock_irqrestore(&card->lock, flags); 829} 830 831#define DMABUF_DEFAULTORDER (16-PAGE_SHIFT) 832#define DMABUF_MINORDER 1 833 834/* allocate DMA buffer, playback and recording buffer should be allocated seperately */ 835static int alloc_dmabuf(struct i810_state *state) 836{ 837 struct dmabuf *dmabuf = &state->dmabuf; 838 void *rawbuf= NULL; 839 int order, size; 840 struct page *page, *pend; 841 842 /* If we don't have any oss frag params, then use our default ones */ 843 if(dmabuf->ossmaxfrags == 0) 844 dmabuf->ossmaxfrags = 4; 845 if(dmabuf->ossfragsize == 0) 846 dmabuf->ossfragsize = (PAGE_SIZE<<DMABUF_DEFAULTORDER)/dmabuf->ossmaxfrags; 847 size = dmabuf->ossfragsize * dmabuf->ossmaxfrags; 848 849 if(dmabuf->rawbuf && (PAGE_SIZE << dmabuf->buforder) == size) 850 return 0; 851 /* alloc enough to satisfy the oss params */ 852 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) { 853 if ( (PAGE_SIZE<<order) > size ) 854 continue; 855 if ((rawbuf = pci_alloc_consistent(state->card->pci_dev, 856 PAGE_SIZE << order, 857 &dmabuf->dma_handle))) 858 break; 859 } 860 if (!rawbuf) 861 return -ENOMEM; 862 863 864#ifdef DEBUG 865 printk("i810_audio: allocated %ld (order = %d) bytes at %p\n", 866 PAGE_SIZE << order, order, rawbuf); 867#endif 868 869 dmabuf->ready = dmabuf->mapped = 0; 870 dmabuf->rawbuf = rawbuf; 871 dmabuf->buforder = order; 872 873 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */ 874 pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1); 875 for (page = virt_to_page(rawbuf); page <= pend; page++) 876 mem_map_reserve(page); 877 878 return 0; 879} 880 881/* free DMA buffer */ 882static void dealloc_dmabuf(struct i810_state *state) 883{ 884 struct dmabuf *dmabuf = &state->dmabuf; 885 struct page *page, *pend; 886 887 if (dmabuf->rawbuf) { 888 /* undo marking the pages as reserved */ 889 pend = virt_to_page(dmabuf->rawbuf + (PAGE_SIZE << dmabuf->buforder) - 1); 890 for (page = virt_to_page(dmabuf->rawbuf); page <= pend; page++) 891 mem_map_unreserve(page); 892 pci_free_consistent(state->card->pci_dev, PAGE_SIZE << dmabuf->buforder, 893 dmabuf->rawbuf, dmabuf->dma_handle); 894 } 895 dmabuf->rawbuf = NULL; 896 dmabuf->mapped = dmabuf->ready = 0; 897} 898 899static int prog_dmabuf(struct i810_state *state, unsigned rec) 900{ 901 struct dmabuf *dmabuf = &state->dmabuf; 902 struct i810_channel *c; 903 struct sg_item *sg; 904 unsigned long flags; 905 int ret; 906 unsigned fragint; 907 int i; 908 909 spin_lock_irqsave(&state->card->lock, flags); 910 if(dmabuf->enable & DAC_RUNNING) 911 __stop_dac(state); 912 if(dmabuf->enable & ADC_RUNNING) 913 __stop_adc(state); 914 dmabuf->total_bytes = 0; 915 dmabuf->count = dmabuf->error = 0; 916 dmabuf->swptr = dmabuf->hwptr = 0; 917 spin_unlock_irqrestore(&state->card->lock, flags); 918 919 /* allocate DMA buffer, let alloc_dmabuf determine if we are already 920 * allocated well enough or if we should replace the current buffer 921 * (assuming one is already allocated, if it isn't, then allocate it). 922 */ 923 if ((ret = alloc_dmabuf(state))) 924 return ret; 925 926 /* I did, it now does what it should according to the OSS API. DL */ 927 /* We may not have realloced our dmabuf, but the fragment size to 928 * fragment number ratio may have changed, so go ahead and reprogram 929 * things 930 */ 931 dmabuf->dmasize = PAGE_SIZE << dmabuf->buforder; 932 dmabuf->numfrag = SG_LEN; 933 dmabuf->fragsize = dmabuf->dmasize/dmabuf->numfrag; 934 dmabuf->fragsamples = dmabuf->fragsize >> 1; 935 dmabuf->userfragsize = dmabuf->ossfragsize; 936 dmabuf->userfrags = dmabuf->dmasize/dmabuf->ossfragsize; 937 938 memset(dmabuf->rawbuf, 0, dmabuf->dmasize); 939 940 if(dmabuf->ossmaxfrags == 4) { 941 fragint = 8; 942 dmabuf->fragshift = 2; 943 } else if (dmabuf->ossmaxfrags == 8) { 944 fragint = 4; 945 dmabuf->fragshift = 3; 946 } else if (dmabuf->ossmaxfrags == 16) { 947 fragint = 2; 948 dmabuf->fragshift = 4; 949 } else { 950 fragint = 1; 951 dmabuf->fragshift = 5; 952 } 953 /* 954 * Now set up the ring 955 */ 956 if(dmabuf->read_channel) 957 c = dmabuf->read_channel; 958 else 959 c = dmabuf->write_channel; 960 while(c != NULL) { 961 sg=&c->sg[0]; 962 /* 963 * Load up 32 sg entries and take an interrupt at half 964 * way (we might want more interrupts later..) 965 */ 966 967 for(i=0;i<dmabuf->numfrag;i++) 968 { 969 sg->busaddr=virt_to_bus(dmabuf->rawbuf+dmabuf->fragsize*i); 970 // the card will always be doing 16bit stereo 971 sg->control=dmabuf->fragsamples; 972 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012) 973 sg->control <<= 1; 974 sg->control|=CON_BUFPAD; 975 // set us up to get IOC interrupts as often as needed to 976 // satisfy numfrag requirements, no more 977 if( ((i+1) % fragint) == 0) { 978 sg->control|=CON_IOC; 979 } 980 sg++; 981 } 982 spin_lock_irqsave(&state->card->lock, flags); 983 outb(2, state->card->iobase+c->port+OFF_CR); /* reset DMA machine */ 984 outl(virt_to_bus(&c->sg[0]), state->card->iobase+c->port+OFF_BDBAR); 985 outb(0, state->card->iobase+c->port+OFF_CIV); 986 outb(0, state->card->iobase+c->port+OFF_LVI); 987 988 spin_unlock_irqrestore(&state->card->lock, flags); 989 990 if(c != dmabuf->write_channel) 991 c = dmabuf->write_channel; 992 else 993 c = NULL; 994 } 995 996 /* set the ready flag for the dma buffer */ 997 dmabuf->ready = 1; 998 999#ifdef DEBUG 1000 printk("i810_audio: prog_dmabuf, sample rate = %d, format = %d,\n\tnumfrag = %d, " 1001 "fragsize = %d dmasize = %d\n", 1002 dmabuf->rate, dmabuf->fmt, dmabuf->numfrag, 1003 dmabuf->fragsize, dmabuf->dmasize); 1004#endif 1005 1006 return 0; 1007} 1008 1009static void __i810_update_lvi(struct i810_state *state, int rec) 1010{ 1011 struct dmabuf *dmabuf = &state->dmabuf; 1012 int x, port; 1013 1014 port = state->card->iobase; 1015 if(rec) 1016 port += dmabuf->read_channel->port; 1017 else 1018 port += dmabuf->write_channel->port; 1019 1020 /* if we are currently stopped, then our CIV is actually set to our 1021 * *last* sg segment and we are ready to wrap to the next. However, 1022 * if we set our LVI to the last sg segment, then it won't wrap to 1023 * the next sg segment, it won't even get a start. So, instead, when 1024 * we are stopped, we set both the LVI value and also we increment 1025 * the CIV value to the next sg segment to be played so that when 1026 * we call start_{dac,adc}, things will operate properly 1027 */ 1028 if (!dmabuf->enable && dmabuf->ready) { 1029 if(rec && dmabuf->count < dmabuf->dmasize && 1030 (dmabuf->trigger & PCM_ENABLE_INPUT)) 1031 { 1032 outb((inb(port+OFF_CIV)+1)&31, port+OFF_LVI); 1033 __start_adc(state); 1034 while( !(inb(port + OFF_CR) & ((1<<4) | (1<<2))) ) ; 1035 } else if (!rec && dmabuf->count && 1036 (dmabuf->trigger & PCM_ENABLE_OUTPUT)) 1037 { 1038 outb((inb(port+OFF_CIV)+1)&31, port+OFF_LVI); 1039 __start_dac(state); 1040 while( !(inb(port + OFF_CR) & ((1<<4) | (1<<2))) ) ; 1041 } 1042 } 1043 1044 /* swptr - 1 is the tail of our transfer */ 1045 x = (dmabuf->dmasize + dmabuf->swptr - 1) % dmabuf->dmasize; 1046 x /= dmabuf->fragsize; 1047 outb(x, port+OFF_LVI); 1048} 1049 1050static void i810_update_lvi(struct i810_state *state, int rec) 1051{ 1052 struct dmabuf *dmabuf = &state->dmabuf; 1053 unsigned long flags; 1054 1055 if(!dmabuf->ready) 1056 return; 1057 spin_lock_irqsave(&state->card->lock, flags); 1058 __i810_update_lvi(state, rec); 1059 spin_unlock_irqrestore(&state->card->lock, flags); 1060} 1061 1062/* update buffer manangement pointers, especially, dmabuf->count and dmabuf->hwptr */ 1063static void i810_update_ptr(struct i810_state *state) 1064{ 1065 struct dmabuf *dmabuf = &state->dmabuf; 1066 unsigned hwptr; 1067 int diff; 1068 1069 /* error handling and process wake up for DAC */ 1070 if (dmabuf->enable == ADC_RUNNING) { 1071 /* update hardware pointer */ 1072 hwptr = i810_get_dma_addr(state, 1); 1073 diff = (dmabuf->dmasize + hwptr - dmabuf->hwptr) % dmabuf->dmasize; 1074#if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP) 1075 printk("ADC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff); 1076#endif 1077 dmabuf->hwptr = hwptr; 1078 dmabuf->total_bytes += diff; 1079 dmabuf->count += diff; 1080 if (dmabuf->count > dmabuf->dmasize) { 1081 /* buffer underrun or buffer overrun */ 1082 /* this is normal for the end of a read */ 1083 /* only give an error if we went past the */ 1084 /* last valid sg entry */ 1085 if((inb(state->card->iobase + PI_CIV) & 31) != 1086 (inb(state->card->iobase + PI_LVI) & 31)) { 1087 printk(KERN_WARNING "i810_audio: DMA overrun on read\n"); 1088 dmabuf->error++; 1089 } 1090 } 1091 if (dmabuf->count > dmabuf->userfragsize) 1092 wake_up(&dmabuf->wait); 1093 } 1094 /* error handling and process wake up for DAC */ 1095 if (dmabuf->enable == DAC_RUNNING) { 1096 /* update hardware pointer */ 1097 hwptr = i810_get_dma_addr(state, 0); 1098 diff = (dmabuf->dmasize + hwptr - dmabuf->hwptr) % dmabuf->dmasize; 1099#if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP) 1100 printk("DAC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff); 1101#endif 1102 dmabuf->hwptr = hwptr; 1103 dmabuf->total_bytes += diff; 1104 dmabuf->count -= diff; 1105 if (dmabuf->count < 0) { 1106 /* buffer underrun or buffer overrun */ 1107 /* this is normal for the end of a write */ 1108 /* only give an error if we went past the */ 1109 /* last valid sg entry */ 1110 if((inb(state->card->iobase + PO_CIV) & 31) != 1111 (inb(state->card->iobase + PO_LVI) & 31)) { 1112 printk(KERN_WARNING "i810_audio: DMA overrun on write\n"); 1113 printk("i810_audio: CIV %d, LVI %d, hwptr %x, " 1114 "count %d\n", 1115 inb(state->card->iobase + PO_CIV) & 31, 1116 inb(state->card->iobase + PO_LVI) & 31, 1117 dmabuf->hwptr, dmabuf->count); 1118 dmabuf->error++; 1119 } 1120 } 1121 if (dmabuf->count < (dmabuf->dmasize-dmabuf->userfragsize)) 1122 wake_up(&dmabuf->wait); 1123 } 1124} 1125 1126static inline int i810_get_free_write_space(struct i810_state *state) 1127{ 1128 struct dmabuf *dmabuf = &state->dmabuf; 1129 int free; 1130 1131 i810_update_ptr(state); 1132 // catch underruns during playback 1133 if (dmabuf->count < 0) { 1134 dmabuf->count = 0; 1135 dmabuf->swptr = dmabuf->hwptr; 1136 } 1137 free = dmabuf->dmasize - dmabuf->count; 1138 free -= (dmabuf->hwptr % dmabuf->fragsize); 1139 if(free < 0) 1140 return(0); 1141 return(free); 1142} 1143 1144static inline int i810_get_available_read_data(struct i810_state *state) 1145{ 1146 struct dmabuf *dmabuf = &state->dmabuf; 1147 int avail; 1148 1149 i810_update_ptr(state); 1150 // catch overruns during record 1151 if (dmabuf->count > dmabuf->dmasize) { 1152 dmabuf->count = dmabuf->dmasize; 1153 dmabuf->swptr = dmabuf->hwptr; 1154 } 1155 avail = dmabuf->count; 1156 avail -= (dmabuf->hwptr % dmabuf->fragsize); 1157 if(avail < 0) 1158 return(0); 1159 return(avail); 1160} 1161 1162static int drain_dac(struct i810_state *state, int signals_allowed) 1163{ 1164 DECLARE_WAITQUEUE(wait, current); 1165 struct dmabuf *dmabuf = &state->dmabuf; 1166 unsigned long flags; 1167 unsigned long tmo; 1168 int count; 1169 1170 if (!dmabuf->ready) 1171 return 0; 1172 if(dmabuf->mapped) { 1173 stop_dac(state); 1174 return 0; 1175 } 1176 add_wait_queue(&dmabuf->wait, &wait); 1177 for (;;) { 1178 1179 spin_lock_irqsave(&state->card->lock, flags); 1180 i810_update_ptr(state); 1181 count = dmabuf->count; 1182 spin_unlock_irqrestore(&state->card->lock, flags); 1183 1184 if (count <= 0) 1185 break; 1186 1187 /* 1188 * This will make sure that our LVI is correct, that our 1189 * pointer is updated, and that the DAC is running. We 1190 * have to force the setting of dmabuf->trigger to avoid 1191 * any possible deadlocks. 1192 */ 1193 if(!dmabuf->enable) { 1194 dmabuf->trigger = PCM_ENABLE_OUTPUT; 1195 i810_update_lvi(state,0); 1196 } 1197 if (signal_pending(current) && signals_allowed) { 1198 break; 1199 } 1200 1201 /* It seems that we have to set the current state to 1202 * TASK_INTERRUPTIBLE every time to make the process 1203 * really go to sleep. This also has to be *after* the 1204 * update_ptr() call because update_ptr is likely to 1205 * do a wake_up() which will unset this before we ever 1206 * try to sleep, resuling in a tight loop in this code 1207 * instead of actually sleeping and waiting for an 1208 * interrupt to wake us up! 1209 */ 1210 set_current_state(TASK_INTERRUPTIBLE); 1211 /* 1212 * set the timeout to significantly longer than it *should* 1213 * take for the DAC to drain the DMA buffer 1214 */ 1215 tmo = (count * HZ) / (dmabuf->rate); 1216 if (!schedule_timeout(tmo >= 2 ? tmo : 2)){ 1217 printk(KERN_ERR "i810_audio: drain_dac, dma timeout?\n"); 1218 count = 0; 1219 break; 1220 } 1221 } 1222 set_current_state(TASK_RUNNING); 1223 remove_wait_queue(&dmabuf->wait, &wait); 1224 if(count > 0 && signal_pending(current) && signals_allowed) 1225 return -ERESTARTSYS; 1226 stop_dac(state); 1227 return 0; 1228} 1229 1230static void i810_channel_interrupt(struct i810_card *card) 1231{ 1232 int i, count; 1233 1234#ifdef DEBUG_INTERRUPTS 1235 printk("CHANNEL "); 1236#endif 1237 for(i=0;i<NR_HW_CH;i++) 1238 { 1239 struct i810_state *state = card->states[i]; 1240 struct i810_channel *c; 1241 struct dmabuf *dmabuf; 1242 unsigned long port = card->iobase; 1243 u16 status; 1244 1245 if(!state) 1246 continue; 1247 if(!state->dmabuf.ready) 1248 continue; 1249 dmabuf = &state->dmabuf; 1250 if(dmabuf->enable & DAC_RUNNING) { 1251 c=dmabuf->write_channel; 1252 } else if(dmabuf->enable & ADC_RUNNING) { 1253 c=dmabuf->read_channel; 1254 } else /* This can occur going from R/W to close */ 1255 continue; 1256 1257 port+=c->port; 1258 1259 if(card->pci_id == PCI_DEVICE_ID_SI_7012) 1260 status = inw(port + OFF_PICB); 1261 else 1262 status = inw(port + OFF_SR); 1263 1264#ifdef DEBUG_INTERRUPTS 1265 printk("NUM %d PORT %X IRQ ( ST%d ", c->num, c->port, status); 1266#endif 1267 if(status & DMA_INT_COMPLETE) 1268 { 1269 /* only wake_up() waiters if this interrupt signals 1270 * us being beyond a userfragsize of data open or 1271 * available, and i810_update_ptr() does that for 1272 * us 1273 */ 1274 i810_update_ptr(state); 1275#ifdef DEBUG_INTERRUPTS 1276 printk("COMP %d ", dmabuf->hwptr / 1277 dmabuf->fragsize); 1278#endif 1279 } 1280 if(status & (DMA_INT_LVI | DMA_INT_DCH)) 1281 { 1282 /* wake_up() unconditionally on LVI and DCH */ 1283 i810_update_ptr(state); 1284 wake_up(&dmabuf->wait); 1285#ifdef DEBUG_INTERRUPTS 1286 if(status & DMA_INT_LVI) 1287 printk("LVI "); 1288 if(status & DMA_INT_DCH) 1289 printk("DCH -"); 1290#endif 1291 if(dmabuf->enable & DAC_RUNNING) 1292 count = dmabuf->count; 1293 else 1294 count = dmabuf->dmasize - dmabuf->count; 1295 if(count > 0) { 1296 outb(inb(port+OFF_CR) | 1, port+OFF_CR); 1297#ifdef DEBUG_INTERRUPTS 1298 printk(" CONTINUE "); 1299#endif 1300 } else { 1301 if (dmabuf->enable & DAC_RUNNING) 1302 __stop_dac(state); 1303 if (dmabuf->enable & ADC_RUNNING) 1304 __stop_adc(state); 1305 dmabuf->enable = 0; 1306 wake_up(&dmabuf->wait); 1307#ifdef DEBUG_INTERRUPTS 1308 printk(" STOP "); 1309#endif 1310 } 1311 } 1312 if(card->pci_id == PCI_DEVICE_ID_SI_7012) 1313 outw(status & DMA_INT_MASK, port + OFF_PICB); 1314 else 1315 outw(status & DMA_INT_MASK, port + OFF_SR); 1316 } 1317#ifdef DEBUG_INTERRUPTS 1318 printk(")\n"); 1319#endif 1320} 1321 1322static void i810_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1323{ 1324 struct i810_card *card = (struct i810_card *)dev_id; 1325 u32 status; 1326 1327 spin_lock(&card->lock); 1328 1329 status = inl(card->iobase + GLOB_STA); 1330 1331 if(!(status & INT_MASK)) 1332 { 1333 spin_unlock(&card->lock); 1334 return; /* not for us */ 1335 } 1336 1337 if(status & (INT_PO|INT_PI|INT_MC)) 1338 i810_channel_interrupt(card); 1339 1340 /* clear 'em */ 1341 outl(status & INT_MASK, card->iobase + GLOB_STA); 1342 spin_unlock(&card->lock); 1343} 1344 1345/* in this loop, dmabuf.count signifies the amount of data that is 1346 waiting to be copied to the user's buffer. It is filled by the dma 1347 machine and drained by this loop. */ 1348 1349static ssize_t i810_read(struct file *file, char *buffer, size_t count, loff_t *ppos) 1350{ 1351 struct i810_state *state = (struct i810_state *)file->private_data; 1352 struct i810_card *card=state ? state->card : 0; 1353 struct dmabuf *dmabuf = &state->dmabuf; 1354 ssize_t ret; 1355 unsigned long flags; 1356 unsigned int swptr; 1357 int cnt; 1358 DECLARE_WAITQUEUE(waita, current); 1359 1360#ifdef DEBUG2 1361 printk("i810_audio: i810_read called, count = %d\n", count); 1362#endif 1363 1364 if (ppos != &file->f_pos) 1365 return -ESPIPE; 1366 if (dmabuf->mapped) 1367 return -ENXIO; 1368 if (dmabuf->enable & DAC_RUNNING) 1369 return -ENODEV; 1370 if (!dmabuf->read_channel) { 1371 dmabuf->ready = 0; 1372 dmabuf->read_channel = card->alloc_rec_pcm_channel(card); 1373 if (!dmabuf->read_channel) { 1374 return -EBUSY; 1375 } 1376 } 1377 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1))) 1378 return ret; 1379 if (!access_ok(VERIFY_WRITE, buffer, count)) 1380 return -EFAULT; 1381 ret = 0; 1382 1383 add_wait_queue(&dmabuf->wait, &waita); 1384 while (count > 0) { 1385 set_current_state(TASK_INTERRUPTIBLE); 1386 spin_lock_irqsave(&card->lock, flags); 1387 if (PM_SUSPENDED(card)) { 1388 spin_unlock_irqrestore(&card->lock, flags); 1389 schedule(); 1390 if (signal_pending(current)) { 1391 if (!ret) ret = -EAGAIN; 1392 break; 1393 } 1394 continue; 1395 } 1396 swptr = dmabuf->swptr; 1397 cnt = i810_get_available_read_data(state); 1398 // this is to make the copy_to_user simpler below 1399 if(cnt > (dmabuf->dmasize - swptr)) 1400 cnt = dmabuf->dmasize - swptr; 1401 spin_unlock_irqrestore(&card->lock, flags); 1402 1403 if (cnt > count) 1404 cnt = count; 1405 /* Lop off the last two bits to force the code to always 1406 * write in full samples. This keeps software that sets 1407 * O_NONBLOCK but doesn't check the return value of the 1408 * write call from getting things out of state where they 1409 * think a full 4 byte sample was written when really only 1410 * a portion was, resulting in odd sound and stereo 1411 * hysteresis. 1412 */ 1413 cnt &= ~0x3; 1414 if (cnt <= 0) { 1415 unsigned long tmo; 1416 /* 1417 * Don't let us deadlock. The ADC won't start if 1418 * dmabuf->trigger isn't set. A call to SETTRIGGER 1419 * could have turned it off after we set it to on 1420 * previously. 1421 */ 1422 dmabuf->trigger = PCM_ENABLE_INPUT; 1423 /* 1424 * This does three things. Updates LVI to be correct, 1425 * makes sure the ADC is running, and updates the 1426 * hwptr. 1427 */ 1428 i810_update_lvi(state,1); 1429 if (file->f_flags & O_NONBLOCK) { 1430 if (!ret) ret = -EAGAIN; 1431 goto done; 1432 } 1433 /* Set the timeout to how long it would take to fill 1434 * two of our buffers. If we haven't been woke up 1435 * by then, then we know something is wrong. 1436 */ 1437 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4); 1438 /* There are two situations when sleep_on_timeout returns, one is when 1439 the interrupt is serviced correctly and the process is waked up by 1440 ISR ON TIME. Another is when timeout is expired, which means that 1441 either interrupt is NOT serviced correctly (pending interrupt) or it 1442 is TOO LATE for the process to be scheduled to run (scheduler latency) 1443 which results in a (potential) buffer overrun. And worse, there is 1444 NOTHING we can do to prevent it. */ 1445 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) { 1446#ifdef DEBUG 1447 printk(KERN_ERR "i810_audio: recording schedule timeout, " 1448 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n", 1449 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count, 1450 dmabuf->hwptr, dmabuf->swptr); 1451#endif 1452 /* a buffer overrun, we delay the recovery until next time the 1453 while loop begin and we REALLY have space to record */ 1454 } 1455 if (signal_pending(current)) { 1456 ret = ret ? ret : -ERESTARTSYS; 1457 goto done; 1458 } 1459 continue; 1460 } 1461 1462 if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) { 1463 if (!ret) ret = -EFAULT; 1464 goto done; 1465 } 1466 1467 swptr = (swptr + cnt) % dmabuf->dmasize; 1468 1469 spin_lock_irqsave(&card->lock, flags); 1470 1471 if (PM_SUSPENDED(card)) { 1472 spin_unlock_irqrestore(&card->lock, flags); 1473 continue; 1474 } 1475 dmabuf->swptr = swptr; 1476 dmabuf->count -= cnt; 1477 spin_unlock_irqrestore(&card->lock, flags); 1478 1479 count -= cnt; 1480 buffer += cnt; 1481 ret += cnt; 1482 } 1483 done: 1484 i810_update_lvi(state,1); 1485 set_current_state(TASK_RUNNING); 1486 remove_wait_queue(&dmabuf->wait, &waita); 1487 1488 return ret; 1489} 1490 1491/* in this loop, dmabuf.count signifies the amount of data that is waiting to be dma to 1492 the soundcard. it is drained by the dma machine and filled by this loop. */ 1493static ssize_t i810_write(struct file *file, const char *buffer, size_t count, loff_t *ppos) 1494{ 1495 struct i810_state *state = (struct i810_state *)file->private_data; 1496 struct i810_card *card=state ? state->card : 0; 1497 struct dmabuf *dmabuf = &state->dmabuf; 1498 ssize_t ret; 1499 unsigned long flags; 1500 unsigned int swptr = 0; 1501 int cnt, x; 1502 DECLARE_WAITQUEUE(waita, current); 1503 1504#ifdef DEBUG2 1505 printk("i810_audio: i810_write called, count = %d\n", count); 1506#endif 1507 1508 if (ppos != &file->f_pos) 1509 return -ESPIPE; 1510 if (dmabuf->mapped) 1511 return -ENXIO; 1512 if (dmabuf->enable & ADC_RUNNING) 1513 return -ENODEV; 1514 if (!dmabuf->write_channel) { 1515 dmabuf->ready = 0; 1516 dmabuf->write_channel = card->alloc_pcm_channel(card); 1517 if(!dmabuf->write_channel) 1518 return -EBUSY; 1519 } 1520 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0))) 1521 return ret; 1522 if (!access_ok(VERIFY_READ, buffer, count)) 1523 return -EFAULT; 1524 ret = 0; 1525 1526 add_wait_queue(&dmabuf->wait, &waita); 1527 while (count > 0) { 1528 set_current_state(TASK_INTERRUPTIBLE); 1529 spin_lock_irqsave(&state->card->lock, flags); 1530 if (PM_SUSPENDED(card)) { 1531 spin_unlock_irqrestore(&card->lock, flags); 1532 schedule(); 1533 if (signal_pending(current)) { 1534 if (!ret) ret = -EAGAIN; 1535 break; 1536 } 1537 continue; 1538 } 1539 1540 swptr = dmabuf->swptr; 1541 cnt = i810_get_free_write_space(state); 1542 /* Bound the maximum size to how much we can copy to the 1543 * dma buffer before we hit the end. If we have more to 1544 * copy then it will get done in a second pass of this 1545 * loop starting from the beginning of the buffer. 1546 */ 1547 if(cnt > (dmabuf->dmasize - swptr)) 1548 cnt = dmabuf->dmasize - swptr; 1549 spin_unlock_irqrestore(&state->card->lock, flags); 1550 1551#ifdef DEBUG2 1552 printk(KERN_INFO "i810_audio: i810_write: %d bytes available space\n", cnt); 1553#endif 1554 if (cnt > count) 1555 cnt = count; 1556 /* Lop off the last two bits to force the code to always 1557 * write in full samples. This keeps software that sets 1558 * O_NONBLOCK but doesn't check the return value of the 1559 * write call from getting things out of state where they 1560 * think a full 4 byte sample was written when really only 1561 * a portion was, resulting in odd sound and stereo 1562 * hysteresis. 1563 */ 1564 cnt &= ~0x3; 1565 if (cnt <= 0) { 1566 unsigned long tmo; 1567 // There is data waiting to be played 1568 /* 1569 * Force the trigger setting since we would 1570 * deadlock with it set any other way 1571 */ 1572 dmabuf->trigger = PCM_ENABLE_OUTPUT; 1573 i810_update_lvi(state,0); 1574 if (file->f_flags & O_NONBLOCK) { 1575 if (!ret) ret = -EAGAIN; 1576 goto ret; 1577 } 1578 /* Not strictly correct but works */ 1579 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4); 1580 /* There are two situations when sleep_on_timeout returns, one is when 1581 the interrupt is serviced correctly and the process is waked up by 1582 ISR ON TIME. Another is when timeout is expired, which means that 1583 either interrupt is NOT serviced correctly (pending interrupt) or it 1584 is TOO LATE for the process to be scheduled to run (scheduler latency) 1585 which results in a (potential) buffer underrun. And worse, there is 1586 NOTHING we can do to prevent it. */ 1587 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) { 1588#ifdef DEBUG 1589 printk(KERN_ERR "i810_audio: playback schedule timeout, " 1590 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n", 1591 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count, 1592 dmabuf->hwptr, dmabuf->swptr); 1593#endif 1594 /* a buffer underrun, we delay the recovery until next time the 1595 while loop begin and we REALLY have data to play */ 1596 //return ret; 1597 } 1598 if (signal_pending(current)) { 1599 if (!ret) ret = -ERESTARTSYS; 1600 goto ret; 1601 } 1602 continue; 1603 } 1604 if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) { 1605 if (!ret) ret = -EFAULT; 1606 goto ret; 1607 } 1608 1609 swptr = (swptr + cnt) % dmabuf->dmasize; 1610 1611 spin_lock_irqsave(&state->card->lock, flags); 1612 if (PM_SUSPENDED(card)) { 1613 spin_unlock_irqrestore(&card->lock, flags); 1614 continue; 1615 } 1616 1617 dmabuf->swptr = swptr; 1618 dmabuf->count += cnt; 1619 1620 count -= cnt; 1621 buffer += cnt; 1622 ret += cnt; 1623 spin_unlock_irqrestore(&state->card->lock, flags); 1624 } 1625 if (swptr % dmabuf->fragsize) { 1626 x = dmabuf->fragsize - (swptr % dmabuf->fragsize); 1627 memset(dmabuf->rawbuf + swptr, '\0', x); 1628 } 1629ret: 1630 i810_update_lvi(state,0); 1631 set_current_state(TASK_RUNNING); 1632 remove_wait_queue(&dmabuf->wait, &waita); 1633 1634 return ret; 1635} 1636 1637/* No kernel lock - we have our own spinlock */ 1638static unsigned int i810_poll(struct file *file, struct poll_table_struct *wait) 1639{ 1640 struct i810_state *state = (struct i810_state *)file->private_data; 1641 struct dmabuf *dmabuf = &state->dmabuf; 1642 unsigned long flags; 1643 unsigned int mask = 0; 1644 1645 if(!dmabuf->ready) 1646 return 0; 1647 poll_wait(file, &dmabuf->wait, wait); 1648 spin_lock_irqsave(&state->card->lock, flags); 1649 if (dmabuf->enable & ADC_RUNNING || 1650 dmabuf->trigger & PCM_ENABLE_INPUT) { 1651 if (i810_get_available_read_data(state) >= 1652 (signed)dmabuf->userfragsize) 1653 mask |= POLLIN | POLLRDNORM; 1654 } 1655 if (dmabuf->enable & DAC_RUNNING || 1656 dmabuf->trigger & PCM_ENABLE_OUTPUT) { 1657 if (i810_get_free_write_space(state) >= 1658 (signed)dmabuf->userfragsize) 1659 mask |= POLLOUT | POLLWRNORM; 1660 } 1661 spin_unlock_irqrestore(&state->card->lock, flags); 1662 return mask; 1663} 1664 1665static int i810_mmap(struct file *file, struct vm_area_struct *vma) 1666{ 1667 struct i810_state *state = (struct i810_state *)file->private_data; 1668 struct dmabuf *dmabuf = &state->dmabuf; 1669 int ret = -EINVAL; 1670 unsigned long size; 1671 1672 lock_kernel(); 1673 if (vma->vm_flags & VM_WRITE) { 1674 if (!dmabuf->write_channel && 1675 (dmabuf->write_channel = 1676 state->card->alloc_pcm_channel(state->card)) == NULL) { 1677 ret = -EBUSY; 1678 goto out; 1679 } 1680 } 1681 if (vma->vm_flags & VM_READ) { 1682 if (!dmabuf->read_channel && 1683 (dmabuf->read_channel = 1684 state->card->alloc_rec_pcm_channel(state->card)) == NULL) { 1685 ret = -EBUSY; 1686 goto out; 1687 } 1688 } 1689 if ((ret = prog_dmabuf(state, 0)) != 0) 1690 goto out; 1691 1692 ret = -EINVAL; 1693 if (vma->vm_pgoff != 0) 1694 goto out; 1695 size = vma->vm_end - vma->vm_start; 1696 if (size > (PAGE_SIZE << dmabuf->buforder)) 1697 goto out; 1698 ret = -EAGAIN; 1699 if (remap_page_range(vma->vm_start, virt_to_phys(dmabuf->rawbuf), 1700 size, vma->vm_page_prot)) 1701 goto out; 1702 dmabuf->mapped = 1; 1703 dmabuf->trigger = 0; 1704 ret = 0; 1705#ifdef DEBUG_MMAP 1706 printk("i810_audio: mmap'ed %ld bytes of data space\n", size); 1707#endif 1708out: 1709 unlock_kernel(); 1710 return ret; 1711} 1712 1713static int i810_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) 1714{ 1715 struct i810_state *state = (struct i810_state *)file->private_data; 1716 struct i810_channel *c = NULL; 1717 struct dmabuf *dmabuf = &state->dmabuf; 1718 unsigned long flags; 1719 audio_buf_info abinfo; 1720 count_info cinfo; 1721 unsigned int i_glob_cnt; 1722 int val = 0, ret; 1723 struct ac97_codec *codec = state->card->ac97_codec[0]; 1724 1725#ifdef DEBUG 1726 printk("i810_audio: i810_ioctl, arg=0x%x, cmd=", arg ? *(int *)arg : 0); 1727#endif 1728 1729 switch (cmd) 1730 { 1731 case OSS_GETVERSION: 1732#ifdef DEBUG 1733 printk("OSS_GETVERSION\n"); 1734#endif 1735 return put_user(SOUND_VERSION, (int *)arg); 1736 1737 case SNDCTL_DSP_RESET: 1738#ifdef DEBUG 1739 printk("SNDCTL_DSP_RESET\n"); 1740#endif 1741 spin_lock_irqsave(&state->card->lock, flags); 1742 if (dmabuf->enable == DAC_RUNNING) { 1743 c = dmabuf->write_channel; 1744 __stop_dac(state); 1745 } 1746 if (dmabuf->enable == ADC_RUNNING) { 1747 c = dmabuf->read_channel; 1748 __stop_adc(state); 1749 } 1750 if (c != NULL) { 1751 outb(2, state->card->iobase+c->port+OFF_CR); /* reset DMA machine */ 1752 outl(virt_to_bus(&c->sg[0]), state->card->iobase+c->port+OFF_BDBAR); 1753 outb(0, state->card->iobase+c->port+OFF_CIV); 1754 outb(0, state->card->iobase+c->port+OFF_LVI); 1755 } 1756 1757 spin_unlock_irqrestore(&state->card->lock, flags); 1758 synchronize_irq(); 1759 dmabuf->ready = 0; 1760 dmabuf->swptr = dmabuf->hwptr = 0; 1761 dmabuf->count = dmabuf->total_bytes = 0; 1762 return 0; 1763 1764 case SNDCTL_DSP_SYNC: 1765#ifdef DEBUG 1766 printk("SNDCTL_DSP_SYNC\n"); 1767#endif 1768 if (dmabuf->enable != DAC_RUNNING || file->f_flags & O_NONBLOCK) 1769 return 0; 1770 if((val = drain_dac(state, 1))) 1771 return val; 1772 dmabuf->total_bytes = 0; 1773 return 0; 1774 1775 case SNDCTL_DSP_SPEED: /* set smaple rate */ 1776#ifdef DEBUG 1777 printk("SNDCTL_DSP_SPEED\n"); 1778#endif 1779 if (get_user(val, (int *)arg)) 1780 return -EFAULT; 1781 if (val >= 0) { 1782 if (file->f_mode & FMODE_WRITE) { 1783 if ( (state->card->ac97_status & SPDIF_ON) ) { /* S/PDIF Enabled */ 1784 /* AD1886 only supports 48000, need to check that */ 1785 if ( i810_valid_spdif_rate ( codec, val ) ) { 1786 /* Set DAC rate */ 1787 i810_set_spdif_output ( state, -1, 0 ); 1788 stop_dac(state); 1789 dmabuf->ready = 0; 1790 spin_lock_irqsave(&state->card->lock, flags); 1791 i810_set_dac_rate(state, val); 1792 spin_unlock_irqrestore(&state->card->lock, flags); 1793 /* Set S/PDIF transmitter rate. */ 1794 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, val ); 1795 if ( ! (state->card->ac97_status & SPDIF_ON) ) { 1796 val = dmabuf->rate; 1797 } 1798 } else { /* Not a valid rate for S/PDIF, ignore it */ 1799 val = dmabuf->rate; 1800 } 1801 } else { 1802 stop_dac(state); 1803 dmabuf->ready = 0; 1804 spin_lock_irqsave(&state->card->lock, flags); 1805 i810_set_dac_rate(state, val); 1806 spin_unlock_irqrestore(&state->card->lock, flags); 1807 } 1808 } 1809 if (file->f_mode & FMODE_READ) { 1810 stop_adc(state); 1811 dmabuf->ready = 0; 1812 spin_lock_irqsave(&state->card->lock, flags); 1813 i810_set_adc_rate(state, val); 1814 spin_unlock_irqrestore(&state->card->lock, flags); 1815 } 1816 } 1817 return put_user(dmabuf->rate, (int *)arg); 1818 1819 case SNDCTL_DSP_STEREO: /* set stereo or mono channel */ 1820#ifdef DEBUG 1821 printk("SNDCTL_DSP_STEREO\n"); 1822#endif 1823 if (dmabuf->enable & DAC_RUNNING) { 1824 stop_dac(state); 1825 } 1826 if (dmabuf->enable & ADC_RUNNING) { 1827 stop_adc(state); 1828 } 1829 return put_user(1, (int *)arg); 1830 1831 case SNDCTL_DSP_GETBLKSIZE: 1832 if (file->f_mode & FMODE_WRITE) { 1833 if (!dmabuf->ready && (val = prog_dmabuf(state, 0))) 1834 return val; 1835 } 1836 if (file->f_mode & FMODE_READ) { 1837 if (!dmabuf->ready && (val = prog_dmabuf(state, 1))) 1838 return val; 1839 } 1840#ifdef DEBUG 1841 printk("SNDCTL_DSP_GETBLKSIZE %d\n", dmabuf->userfragsize); 1842#endif 1843 return put_user(dmabuf->userfragsize, (int *)arg); 1844 1845 case SNDCTL_DSP_GETFMTS: /* Returns a mask of supported sample format*/ 1846#ifdef DEBUG 1847 printk("SNDCTL_DSP_GETFMTS\n"); 1848#endif 1849 return put_user(AFMT_S16_LE, (int *)arg); 1850 1851 case SNDCTL_DSP_SETFMT: /* Select sample format */ 1852#ifdef DEBUG 1853 printk("SNDCTL_DSP_SETFMT\n"); 1854#endif 1855 return put_user(AFMT_S16_LE, (int *)arg); 1856 1857 case SNDCTL_DSP_CHANNELS: 1858#ifdef DEBUG 1859 printk("SNDCTL_DSP_CHANNELS\n"); 1860#endif 1861 if (get_user(val, (int *)arg)) 1862 return -EFAULT; 1863 1864 if (val > 0) { 1865 if (dmabuf->enable & DAC_RUNNING) { 1866 stop_dac(state); 1867 } 1868 if (dmabuf->enable & ADC_RUNNING) { 1869 stop_adc(state); 1870 } 1871 } else { 1872 return put_user(state->card->channels, (int *)arg); 1873 } 1874 1875 /* ICH and ICH0 only support 2 channels */ 1876 if ( state->card->pci_id == 0x2415 || state->card->pci_id == 0x2425 ) 1877 return put_user(2, (int *)arg); 1878 1879 /* Multi-channel support was added with ICH2. Bits in */ 1880 /* Global Status and Global Control register are now */ 1881 /* used to indicate this. */ 1882 1883 i_glob_cnt = inl(state->card->iobase + GLOB_CNT); 1884 1885 /* Current # of channels enabled */ 1886 if ( i_glob_cnt & 0x0100000 ) 1887 ret = 4; 1888 else if ( i_glob_cnt & 0x0200000 ) 1889 ret = 6; 1890 else 1891 ret = 2; 1892 1893 switch ( val ) { 1894 case 2: /* 2 channels is always supported */ 1895 outl(state->card->iobase + GLOB_CNT, (i_glob_cnt & 0xcfffff)); 1896 /* Do we need to change mixer settings???? */ 1897 break; 1898 case 4: /* Supported on some chipsets, better check first */ 1899 if ( state->card->channels >= 4 ) { 1900 outl(state->card->iobase + GLOB_CNT, ((i_glob_cnt & 0xcfffff) | 0x0100000)); 1901 /* Do we need to change mixer settings??? */ 1902 } else { 1903 val = ret; 1904 } 1905 break; 1906 case 6: /* Supported on some chipsets, better check first */ 1907 if ( state->card->channels >= 6 ) { 1908 outl(state->card->iobase + GLOB_CNT, ((i_glob_cnt & 0xcfffff) | 0x0200000)); 1909 /* Do we need to change mixer settings??? */ 1910 } else { 1911 val = ret; 1912 } 1913 break; 1914 default: /* nothing else is ever supported by the chipset */ 1915 val = ret; 1916 break; 1917 } 1918 1919 return put_user(val, (int *)arg); 1920 1921 case SNDCTL_DSP_POST: /* the user has sent all data and is notifying us */ 1922 /* we update the swptr to the end of the last sg segment then return */ 1923#ifdef DEBUG 1924 printk("SNDCTL_DSP_POST\n"); 1925#endif 1926 if(!dmabuf->ready || (dmabuf->enable != DAC_RUNNING)) 1927 return 0; 1928 if((dmabuf->swptr % dmabuf->fragsize) != 0) { 1929 val = dmabuf->fragsize - (dmabuf->swptr % dmabuf->fragsize); 1930 dmabuf->swptr += val; 1931 dmabuf->count += val; 1932 } 1933 return 0; 1934 1935 case SNDCTL_DSP_SUBDIVIDE: 1936 if (dmabuf->subdivision) 1937 return -EINVAL; 1938 if (get_user(val, (int *)arg)) 1939 return -EFAULT; 1940 if (val != 1 && val != 2 && val != 4) 1941 return -EINVAL; 1942#ifdef DEBUG 1943 printk("SNDCTL_DSP_SUBDIVIDE %d\n", val); 1944#endif 1945 dmabuf->subdivision = val; 1946 dmabuf->ready = 0; 1947 return 0; 1948 1949 case SNDCTL_DSP_SETFRAGMENT: 1950 if (get_user(val, (int *)arg)) 1951 return -EFAULT; 1952 1953 dmabuf->ossfragsize = 1<<(val & 0xffff); 1954 dmabuf->ossmaxfrags = (val >> 16) & 0xffff; 1955 if (!dmabuf->ossfragsize || !dmabuf->ossmaxfrags) 1956 return -EINVAL; 1957 /* 1958 * Bound the frag size into our allowed range of 256 - 4096 1959 */ 1960 if (dmabuf->ossfragsize < 256) 1961 dmabuf->ossfragsize = 256; 1962 else if (dmabuf->ossfragsize > 4096) 1963 dmabuf->ossfragsize = 4096; 1964 /* 1965 * The numfrags could be something reasonable, or it could 1966 * be 0xffff meaning "Give me as much as possible". So, 1967 * we check the numfrags * fragsize doesn't exceed our 1968 * 64k buffer limit, nor is it less than our 8k minimum. 1969 * If it fails either one of these checks, then adjust the 1970 * number of fragments, not the size of them. It's OK if 1971 * our number of fragments doesn't equal 32 or anything 1972 * like our hardware based number now since we are using 1973 * a different frag count for the hardware. Before we get 1974 * into this though, bound the maxfrags to avoid overflow 1975 * issues. A reasonable bound would be 64k / 256 since our 1976 * maximum buffer size is 64k and our minimum frag size is 1977 * 256. On the other end, our minimum buffer size is 8k and 1978 * our maximum frag size is 4k, so the lower bound should 1979 * be 2. 1980 */ 1981 1982 if(dmabuf->ossmaxfrags > 256) 1983 dmabuf->ossmaxfrags = 256; 1984 else if (dmabuf->ossmaxfrags < 2) 1985 dmabuf->ossmaxfrags = 2; 1986 1987 val = dmabuf->ossfragsize * dmabuf->ossmaxfrags; 1988 while (val < 8192) { 1989 val <<= 1; 1990 dmabuf->ossmaxfrags <<= 1; 1991 } 1992 while (val > 65536) { 1993 val >>= 1; 1994 dmabuf->ossmaxfrags >>= 1; 1995 } 1996 dmabuf->ready = 0; 1997#ifdef DEBUG 1998 printk("SNDCTL_DSP_SETFRAGMENT 0x%x, %d, %d\n", val, 1999 dmabuf->ossfragsize, dmabuf->ossmaxfrags); 2000#endif 2001 2002 return 0; 2003 2004 case SNDCTL_DSP_GETOSPACE: 2005 if (!(file->f_mode & FMODE_WRITE)) 2006 return -EINVAL; 2007 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0) 2008 return val; 2009 spin_lock_irqsave(&state->card->lock, flags); 2010 i810_update_ptr(state); 2011 abinfo.fragsize = dmabuf->userfragsize; 2012 abinfo.fragstotal = dmabuf->userfrags; 2013 if (dmabuf->mapped) 2014 abinfo.bytes = dmabuf->dmasize; 2015 else 2016 abinfo.bytes = i810_get_free_write_space(state); 2017 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize; 2018 spin_unlock_irqrestore(&state->card->lock, flags); 2019#if defined(DEBUG) || defined(DEBUG_MMAP) 2020 printk("SNDCTL_DSP_GETOSPACE %d, %d, %d, %d\n", abinfo.bytes, 2021 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal); 2022#endif 2023 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; 2024 2025 case SNDCTL_DSP_GETOPTR: 2026 if (!(file->f_mode & FMODE_WRITE)) 2027 return -EINVAL; 2028 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0) 2029 return val; 2030 spin_lock_irqsave(&state->card->lock, flags); 2031 val = i810_get_free_write_space(state); 2032 cinfo.bytes = dmabuf->total_bytes; 2033 cinfo.ptr = dmabuf->hwptr; 2034 cinfo.blocks = val/dmabuf->userfragsize; 2035 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_OUTPUT)) { 2036 dmabuf->count += val; 2037 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize; 2038 __i810_update_lvi(state, 0); 2039 } 2040 spin_unlock_irqrestore(&state->card->lock, flags); 2041#if defined(DEBUG) || defined(DEBUG_MMAP) 2042 printk("SNDCTL_DSP_GETOPTR %d, %d, %d, %d\n", cinfo.bytes, 2043 cinfo.blocks, cinfo.ptr, dmabuf->count); 2044#endif 2045 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0; 2046 2047 case SNDCTL_DSP_GETISPACE: 2048 if (!(file->f_mode & FMODE_READ)) 2049 return -EINVAL; 2050 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)) != 0) 2051 return val; 2052 spin_lock_irqsave(&state->card->lock, flags); 2053 abinfo.bytes = i810_get_available_read_data(state); 2054 abinfo.fragsize = dmabuf->userfragsize; 2055 abinfo.fragstotal = dmabuf->userfrags; 2056 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize; 2057 spin_unlock_irqrestore(&state->card->lock, flags); 2058#if defined(DEBUG) || defined(DEBUG_MMAP) 2059 printk("SNDCTL_DSP_GETISPACE %d, %d, %d, %d\n", abinfo.bytes, 2060 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal); 2061#endif 2062 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; 2063 2064 case SNDCTL_DSP_GETIPTR: 2065 if (!(file->f_mode & FMODE_READ)) 2066 return -EINVAL; 2067 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0) 2068 return val; 2069 spin_lock_irqsave(&state->card->lock, flags); 2070 val = i810_get_available_read_data(state); 2071 cinfo.bytes = dmabuf->total_bytes; 2072 cinfo.blocks = val/dmabuf->userfragsize; 2073 cinfo.ptr = dmabuf->hwptr; 2074 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_INPUT)) { 2075 dmabuf->count -= val; 2076 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize; 2077 __i810_update_lvi(state, 1); 2078 } 2079 spin_unlock_irqrestore(&state->card->lock, flags); 2080#if defined(DEBUG) || defined(DEBUG_MMAP) 2081 printk("SNDCTL_DSP_GETIPTR %d, %d, %d, %d\n", cinfo.bytes, 2082 cinfo.blocks, cinfo.ptr, dmabuf->count); 2083#endif 2084 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0; 2085 2086 case SNDCTL_DSP_NONBLOCK: 2087#ifdef DEBUG 2088 printk("SNDCTL_DSP_NONBLOCK\n"); 2089#endif 2090 file->f_flags |= O_NONBLOCK; 2091 return 0; 2092 2093 case SNDCTL_DSP_GETCAPS: 2094#ifdef DEBUG 2095 printk("SNDCTL_DSP_GETCAPS\n"); 2096#endif 2097 return put_user(DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP|DSP_CAP_BIND, 2098 (int *)arg); 2099 2100 case SNDCTL_DSP_GETTRIGGER: 2101 val = 0; 2102#ifdef DEBUG 2103 printk("SNDCTL_DSP_GETTRIGGER 0x%x\n", dmabuf->trigger); 2104#endif 2105 return put_user(dmabuf->trigger, (int *)arg); 2106 2107 case SNDCTL_DSP_SETTRIGGER: 2108 if (get_user(val, (int *)arg)) 2109 return -EFAULT; 2110#if defined(DEBUG) || defined(DEBUG_MMAP) 2111 printk("SNDCTL_DSP_SETTRIGGER 0x%x\n", val); 2112#endif 2113 if( !(val & PCM_ENABLE_INPUT) && dmabuf->enable == ADC_RUNNING) { 2114 stop_adc(state); 2115 } 2116 if( !(val & PCM_ENABLE_OUTPUT) && dmabuf->enable == DAC_RUNNING) { 2117 stop_dac(state); 2118 } 2119 dmabuf->trigger = val; 2120 if(val & PCM_ENABLE_OUTPUT && !(dmabuf->enable & DAC_RUNNING)) { 2121 if (!dmabuf->write_channel) { 2122 dmabuf->ready = 0; 2123 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card); 2124 if (!dmabuf->write_channel) 2125 return -EBUSY; 2126 } 2127 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0))) 2128 return ret; 2129 if (dmabuf->mapped) { 2130 spin_lock_irqsave(&state->card->lock, flags); 2131 i810_update_ptr(state); 2132 dmabuf->count = 0; 2133 dmabuf->swptr = dmabuf->hwptr; 2134 dmabuf->count = i810_get_free_write_space(state); 2135 dmabuf->swptr = (dmabuf->swptr + dmabuf->count) % dmabuf->dmasize; 2136 __i810_update_lvi(state, 0); 2137 spin_unlock_irqrestore(&state->card->lock, flags); 2138 } else 2139 start_dac(state); 2140 } 2141 if(val & PCM_ENABLE_INPUT && !(dmabuf->enable & ADC_RUNNING)) { 2142 if (!dmabuf->read_channel) { 2143 dmabuf->ready = 0; 2144 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card); 2145 if (!dmabuf->read_channel) 2146 return -EBUSY; 2147 } 2148 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1))) 2149 return ret; 2150 if (dmabuf->mapped) { 2151 spin_lock_irqsave(&state->card->lock, flags); 2152 i810_update_ptr(state); 2153 dmabuf->swptr = dmabuf->hwptr; 2154 dmabuf->count = 0; 2155 spin_unlock_irqrestore(&state->card->lock, flags); 2156 } 2157 i810_update_lvi(state, 1); 2158 start_adc(state); 2159 } 2160 return 0; 2161 2162 case SNDCTL_DSP_SETDUPLEX: 2163#ifdef DEBUG 2164 printk("SNDCTL_DSP_SETDUPLEX\n"); 2165#endif 2166 return -EINVAL; 2167 2168 case SNDCTL_DSP_GETODELAY: 2169 if (!(file->f_mode & FMODE_WRITE)) 2170 return -EINVAL; 2171 spin_lock_irqsave(&state->card->lock, flags); 2172 i810_update_ptr(state); 2173 val = dmabuf->count; 2174 spin_unlock_irqrestore(&state->card->lock, flags); 2175#ifdef DEBUG 2176 printk("SNDCTL_DSP_GETODELAY %d\n", dmabuf->count); 2177#endif 2178 return put_user(val, (int *)arg); 2179 2180 case SOUND_PCM_READ_RATE: 2181#ifdef DEBUG 2182 printk("SOUND_PCM_READ_RATE %d\n", dmabuf->rate); 2183#endif 2184 return put_user(dmabuf->rate, (int *)arg); 2185 2186 case SOUND_PCM_READ_CHANNELS: 2187#ifdef DEBUG 2188 printk("SOUND_PCM_READ_CHANNELS\n"); 2189#endif 2190 return put_user(2, (int *)arg); 2191 2192 case SOUND_PCM_READ_BITS: 2193#ifdef DEBUG 2194 printk("SOUND_PCM_READ_BITS\n"); 2195#endif 2196 return put_user(AFMT_S16_LE, (int *)arg); 2197 2198 case SNDCTL_DSP_SETSPDIF: /* Set S/PDIF Control register */ 2199#ifdef DEBUG 2200 printk("SNDCTL_DSP_SETSPDIF\n"); 2201#endif 2202 if (get_user(val, (int *)arg)) 2203 return -EFAULT; 2204 2205 /* Check to make sure the codec supports S/PDIF transmitter */ 2206 2207 if((state->card->ac97_features & 4)) { 2208 /* mask out the transmitter speed bits so the user can't set them */ 2209 val &= ~0x3000; 2210 2211 /* Add the current transmitter speed bits to the passed value */ 2212 ret = i810_ac97_get(codec, AC97_SPDIF_CONTROL); 2213 val |= (ret & 0x3000); 2214 2215 i810_ac97_set(codec, AC97_SPDIF_CONTROL, val); 2216 if(i810_ac97_get(codec, AC97_SPDIF_CONTROL) != val ) { 2217 printk(KERN_ERR "i810_audio: Unable to set S/PDIF configuration to 0x%04x.\n", val); 2218 return -EFAULT; 2219 } 2220 } 2221#ifdef DEBUG 2222 else 2223 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n"); 2224#endif 2225 return put_user(val, (int *)arg); 2226 2227 case SNDCTL_DSP_GETSPDIF: /* Get S/PDIF Control register */ 2228#ifdef DEBUG 2229 printk("SNDCTL_DSP_GETSPDIF\n"); 2230#endif 2231 if (get_user(val, (int *)arg)) 2232 return -EFAULT; 2233 2234 /* Check to make sure the codec supports S/PDIF transmitter */ 2235 2236 if(!(state->card->ac97_features & 4)) { 2237#ifdef DEBUG 2238 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n"); 2239#endif 2240 val = 0; 2241 } else { 2242 val = i810_ac97_get(codec, AC97_SPDIF_CONTROL); 2243 } 2244 //return put_user((val & 0xcfff), (int *)arg); 2245 return put_user(val, (int *)arg); 2246 2247 case SNDCTL_DSP_GETCHANNELMASK: 2248#ifdef DEBUG 2249 printk("SNDCTL_DSP_GETCHANNELMASK\n"); 2250#endif 2251 if (get_user(val, (int *)arg)) 2252 return -EFAULT; 2253 2254 /* Based on AC'97 DAC support, not ICH hardware */ 2255 val = DSP_BIND_FRONT; 2256 if ( state->card->ac97_features & 0x0004 ) 2257 val |= DSP_BIND_SPDIF; 2258 2259 if ( state->card->ac97_features & 0x0080 ) 2260 val |= DSP_BIND_SURR; 2261 if ( state->card->ac97_features & 0x0140 ) 2262 val |= DSP_BIND_CENTER_LFE; 2263 2264 return put_user(val, (int *)arg); 2265 2266 case SNDCTL_DSP_BIND_CHANNEL: 2267#ifdef DEBUG 2268 printk("SNDCTL_DSP_BIND_CHANNEL\n"); 2269#endif 2270 if (get_user(val, (int *)arg)) 2271 return -EFAULT; 2272 if ( val == DSP_BIND_QUERY ) { 2273 val = DSP_BIND_FRONT; /* Always report this as being enabled */ 2274 if ( state->card->ac97_status & SPDIF_ON ) 2275 val |= DSP_BIND_SPDIF; 2276 else { 2277 if ( state->card->ac97_status & SURR_ON ) 2278 val |= DSP_BIND_SURR; 2279 if ( state->card->ac97_status & CENTER_LFE_ON ) 2280 val |= DSP_BIND_CENTER_LFE; 2281 } 2282 } else { /* Not a query, set it */ 2283 if (!(file->f_mode & FMODE_WRITE)) 2284 return -EINVAL; 2285 if ( dmabuf->enable == DAC_RUNNING ) { 2286 stop_dac(state); 2287 } 2288 if ( val & DSP_BIND_SPDIF ) { /* Turn on SPDIF */ 2289 /* Ok, this should probably define what slots 2290 * to use. For now, we'll only set it to the 2291 * defaults: 2292 * 2293 * non multichannel codec maps to slots 3&4 2294 * 2 channel codec maps to slots 7&8 2295 * 4 channel codec maps to slots 6&9 2296 * 6 channel codec maps to slots 10&11 2297 * 2298 * there should be some way for the app to 2299 * select the slot assignment. 2300 */ 2301 2302 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, dmabuf->rate ); 2303 if ( !(state->card->ac97_status & SPDIF_ON) ) 2304 val &= ~DSP_BIND_SPDIF; 2305 } else { 2306 int mask; 2307 int channels; 2308 2309 /* Turn off S/PDIF if it was on */ 2310 if ( state->card->ac97_status & SPDIF_ON ) 2311 i810_set_spdif_output ( state, -1, 0 ); 2312 2313 mask = val & (DSP_BIND_FRONT | DSP_BIND_SURR | DSP_BIND_CENTER_LFE); 2314 switch (mask) { 2315 case DSP_BIND_FRONT: 2316 channels = 2; 2317 break; 2318 case DSP_BIND_FRONT|DSP_BIND_SURR: 2319 channels = 4; 2320 break; 2321 case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE: 2322 channels = 6; 2323 break; 2324 default: 2325 val = DSP_BIND_FRONT; 2326 channels = 2; 2327 break; 2328 } 2329 i810_set_dac_channels ( state, channels ); 2330 2331 /* check that they really got turned on */ 2332 if ( !state->card->ac97_status & SURR_ON ) 2333 val &= ~DSP_BIND_SURR; 2334 if ( !state->card->ac97_status & CENTER_LFE_ON ) 2335 val &= ~DSP_BIND_CENTER_LFE; 2336 } 2337 } 2338 return put_user(val, (int *)arg); 2339 2340 case SNDCTL_DSP_MAPINBUF: 2341 case SNDCTL_DSP_MAPOUTBUF: 2342 case SNDCTL_DSP_SETSYNCRO: 2343 case SOUND_PCM_WRITE_FILTER: 2344 case SOUND_PCM_READ_FILTER: 2345#ifdef DEBUG 2346 printk("SNDCTL_* -EINVAL\n"); 2347#endif 2348 return -EINVAL; 2349 } 2350 return -EINVAL; 2351} 2352 2353static int i810_open(struct inode *inode, struct file *file) 2354{ 2355 int i = 0; 2356 struct i810_card *card = devs; 2357 struct i810_state *state = NULL; 2358 struct dmabuf *dmabuf = NULL; 2359 2360 /* find an avaiable virtual channel (instance of /dev/dsp) */ 2361 while (card != NULL) { 2362 /* 2363 * If we are initializing and then fail, card could go 2364 * away unuexpectedly while we are in the for() loop. 2365 * So, check for card on each iteration before we check 2366 * for card->initializing to avoid a possible oops. 2367 * This usually only matters for times when the driver is 2368 * autoloaded by kmod. 2369 */ 2370 for (i = 0; i < 50 && card && card->initializing; i++) { 2371 set_current_state(TASK_UNINTERRUPTIBLE); 2372 schedule_timeout(HZ/20); 2373 } 2374 for (i = 0; i < NR_HW_CH && card && !card->initializing; i++) { 2375 if (card->states[i] == NULL) { 2376 state = card->states[i] = (struct i810_state *) 2377 kmalloc(sizeof(struct i810_state), GFP_KERNEL); 2378 if (state == NULL) 2379 return -ENOMEM; 2380 memset(state, 0, sizeof(struct i810_state)); 2381 dmabuf = &state->dmabuf; 2382 goto found_virt; 2383 } 2384 } 2385 card = card->next; 2386 } 2387 /* no more virtual channel avaiable */ 2388 if (!state) 2389 return -ENODEV; 2390 2391found_virt: 2392 /* initialize the virtual channel */ 2393 state->virt = i; 2394 state->card = card; 2395 state->magic = I810_STATE_MAGIC; 2396 init_waitqueue_head(&dmabuf->wait); 2397 init_MUTEX(&state->open_sem); 2398 file->private_data = state; 2399 dmabuf->trigger = 0; 2400 2401 /* allocate hardware channels */ 2402 if(file->f_mode & FMODE_READ) { 2403 if((dmabuf->read_channel = card->alloc_rec_pcm_channel(card)) == NULL) { 2404 kfree (card->states[i]); 2405 card->states[i] = NULL;; 2406 return -EBUSY; 2407 } 2408 dmabuf->trigger |= PCM_ENABLE_INPUT; 2409 i810_set_adc_rate(state, 8000); 2410 } 2411 if(file->f_mode & FMODE_WRITE) { 2412 if((dmabuf->write_channel = card->alloc_pcm_channel(card)) == NULL) { 2413 kfree (card->states[i]); 2414 card->states[i] = NULL;; 2415 return -EBUSY; 2416 } 2417 /* Initialize to 8kHz? What if we don't support 8kHz? */ 2418 /* Let's change this to check for S/PDIF stuff */ 2419 2420 dmabuf->trigger |= PCM_ENABLE_OUTPUT; 2421 if ( spdif_locked ) { 2422 i810_set_dac_rate(state, spdif_locked); 2423 i810_set_spdif_output(state, AC97_EA_SPSA_3_4, spdif_locked); 2424 } else { 2425 i810_set_dac_rate(state, 8000); 2426 } 2427 } 2428 2429 /* set default sample format. According to OSS Programmer's Guide /dev/dsp 2430 should be default to unsigned 8-bits, mono, with sample rate 8kHz and 2431 /dev/dspW will accept 16-bits sample, but we don't support those so we 2432 set it immediately to stereo and 16bit, which is all we do support */ 2433 dmabuf->fmt |= I810_FMT_16BIT | I810_FMT_STEREO; 2434 dmabuf->ossfragsize = 0; 2435 dmabuf->ossmaxfrags = 0; 2436 dmabuf->subdivision = 0; 2437 2438 state->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); 2439 2440 return 0; 2441} 2442 2443static int i810_release(struct inode *inode, struct file *file) 2444{ 2445 struct i810_state *state = (struct i810_state *)file->private_data; 2446 struct i810_card *card = state->card; 2447 struct dmabuf *dmabuf = &state->dmabuf; 2448 unsigned long flags; 2449 2450 lock_kernel(); 2451 2452 /* stop DMA state machine and free DMA buffers/channels */ 2453 if(dmabuf->trigger & PCM_ENABLE_OUTPUT) { 2454 drain_dac(state, 0); 2455 } 2456 if(dmabuf->trigger & PCM_ENABLE_INPUT) { 2457 stop_adc(state); 2458 } 2459 spin_lock_irqsave(&card->lock, flags); 2460 dealloc_dmabuf(state); 2461 if (file->f_mode & FMODE_WRITE) { 2462 state->card->free_pcm_channel(state->card, dmabuf->write_channel->num); 2463 } 2464 if (file->f_mode & FMODE_READ) { 2465 state->card->free_pcm_channel(state->card, dmabuf->read_channel->num); 2466 } 2467 2468 state->card->states[state->virt] = NULL; 2469 kfree(state); 2470 spin_unlock_irqrestore(&card->lock, flags); 2471 unlock_kernel(); 2472 2473 return 0; 2474} 2475 2476static /*const*/ struct file_operations i810_audio_fops = { 2477 owner: THIS_MODULE, 2478 llseek: no_llseek, 2479 read: i810_read, 2480 write: i810_write, 2481 poll: i810_poll, 2482 ioctl: i810_ioctl, 2483 mmap: i810_mmap, 2484 open: i810_open, 2485 release: i810_release, 2486}; 2487 2488/* Write AC97 codec registers */ 2489 2490static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg) 2491{ 2492 struct i810_card *card = dev->private_data; 2493 int count = 100; 2494 u8 reg_set = ((dev->id)?((reg&0x7f)|0x80):(reg&0x7f)); 2495 2496 while(count-- && (inb(card->iobase + CAS) & 1)) 2497 udelay(1); 2498 2499 return inw(card->ac97base + reg_set); 2500} 2501 2502static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data) 2503{ 2504 struct i810_card *card = dev->private_data; 2505 int count = 100; 2506 u8 reg_set = ((dev->id)?((reg&0x7f)|0x80):(reg&0x7f)); 2507 2508 while(count-- && (inb(card->iobase + CAS) & 1)) 2509 udelay(1); 2510 outw(data, card->ac97base + reg_set); 2511} 2512 2513 2514/* OSS /dev/mixer file operation methods */ 2515 2516static int i810_open_mixdev(struct inode *inode, struct file *file) 2517{ 2518 int i; 2519 int minor = MINOR(inode->i_rdev); 2520 struct i810_card *card = devs; 2521 2522 for (card = devs; card != NULL; card = card->next) { 2523 /* 2524 * If we are initializing and then fail, card could go 2525 * away unuexpectedly while we are in the for() loop. 2526 * So, check for card on each iteration before we check 2527 * for card->initializing to avoid a possible oops. 2528 * This usually only matters for times when the driver is 2529 * autoloaded by kmod. 2530 */ 2531 for (i = 0; i < 50 && card && card->initializing; i++) { 2532 set_current_state(TASK_UNINTERRUPTIBLE); 2533 schedule_timeout(HZ/20); 2534 } 2535 for (i = 0; i < NR_AC97 && card && !card->initializing; i++) 2536 if (card->ac97_codec[i] != NULL && 2537 card->ac97_codec[i]->dev_mixer == minor) { 2538 file->private_data = card->ac97_codec[i]; 2539 return 0; 2540 } 2541 } 2542 return -ENODEV; 2543} 2544 2545static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, 2546 unsigned long arg) 2547{ 2548 struct ac97_codec *codec = (struct ac97_codec *)file->private_data; 2549 2550 return codec->mixer_ioctl(codec, cmd, arg); 2551} 2552 2553static /*const*/ struct file_operations i810_mixer_fops = { 2554 owner: THIS_MODULE, 2555 llseek: no_llseek, 2556 ioctl: i810_ioctl_mixdev, 2557 open: i810_open_mixdev, 2558}; 2559 2560/* AC97 codec initialisation. These small functions exist so we don't 2561 duplicate code between module init and apm resume */ 2562 2563static inline int i810_ac97_exists(struct i810_card *card,int ac97_number) 2564{ 2565 u32 reg = inl(card->iobase + GLOB_STA); 2566 return (reg & (0x100 << ac97_number)); 2567} 2568 2569static inline int i810_ac97_enable_variable_rate(struct ac97_codec *codec) 2570{ 2571 i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9); 2572 i810_ac97_set(codec,AC97_EXTENDED_STATUS, 2573 i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800); 2574 2575 return (i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1); 2576} 2577 2578 2579static int i810_ac97_probe_and_powerup(struct i810_card *card,struct ac97_codec *codec) 2580{ 2581 /* Returns 0 on failure */ 2582 int i; 2583 2584 if (ac97_probe_codec(codec) == 0) return 0; 2585 2586 /* power it all up */ 2587 i810_ac97_set(codec, AC97_POWER_CONTROL, 2588 i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00); 2589 /* wait for analog ready */ 2590 for (i=10; 2591 i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf); 2592 i--) 2593 { 2594 set_current_state(TASK_UNINTERRUPTIBLE); 2595 schedule_timeout(HZ/20); 2596 } 2597 return i; 2598} 2599 2600/* if I knew what this did, I'd give it a better name */ 2601static int i810_ac97_random_init_stuff(struct i810_card *card) 2602{ 2603 u32 reg = inl(card->iobase + GLOB_CNT); 2604 int i; 2605 2606 if((reg&2)==0) /* Cold required */ 2607 reg|=2; 2608 else 2609 reg|=4; /* Warm */ 2610 2611 reg&=~8; /* ACLink on */ 2612 outl(reg , card->iobase + GLOB_CNT); 2613 2614 for(i=0;i<10;i++) 2615 { 2616 if((inl(card->iobase+GLOB_CNT)&4)==0) 2617 break; 2618 2619 set_current_state(TASK_UNINTERRUPTIBLE); 2620 schedule_timeout(HZ/20); 2621 } 2622 if(i==10) 2623 { 2624 printk(KERN_ERR "i810_audio: AC'97 reset failed.\n"); 2625 return 0; 2626 } 2627 2628 set_current_state(TASK_UNINTERRUPTIBLE); 2629 schedule_timeout(HZ/2); 2630 reg = inl(card->iobase + GLOB_STA); 2631 inw(card->ac97base); 2632 return 1; 2633} 2634 2635static int __init i810_ac97_init(struct i810_card *card) 2636{ 2637 int num_ac97 = 0; 2638 int total_channels = 0; 2639 struct ac97_codec *codec; 2640 u16 eid; 2641 u32 reg; 2642 2643 if(!i810_ac97_random_init_stuff(card)) return 0; 2644 2645 /* Number of channels supported */ 2646 /* What about the codec? Just because the ICH supports */ 2647 /* multiple channels doesn't mean the codec does. */ 2648 /* we'll have to modify this in the codec section below */ 2649 /* to reflect what the codec has. */ 2650 /* ICH and ICH0 only support 2 channels so don't bother */ 2651 /* to check.... */ 2652 2653 card->channels = 2; 2654 reg = inl(card->iobase + GLOB_STA); 2655 if ( reg & 0x0200000 ) 2656 card->channels = 6; 2657 else if ( reg & 0x0100000 ) 2658 card->channels = 4; 2659 printk("i810_audio: Audio Controller supports %d channels.\n", card->channels); 2660 2661 inw(card->ac97base); 2662 2663 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) { 2664 2665 /* Assume codec isn't available until we go through the 2666 * gauntlet below */ 2667 card->ac97_codec[num_ac97] = NULL; 2668 2669 /* The ICH programmer's reference says you should */ 2670 /* check the ready status before probing. So we chk */ 2671 /* What do we do if it's not ready? Wait and try */ 2672 /* again, or abort? */ 2673 if (!i810_ac97_exists(card,num_ac97)) { 2674 if(num_ac97 == 0) 2675 printk(KERN_ERR "i810_audio: Primary codec not ready.\n"); 2676 break; /* I think this works, if not ready stop */ 2677 } 2678 2679 if ((codec = kmalloc(sizeof(struct ac97_codec), GFP_KERNEL)) == NULL) 2680 return -ENOMEM; 2681 memset(codec, 0, sizeof(struct ac97_codec)); 2682 2683 /* initialize some basic codec information, other fields will be filled 2684 in ac97_probe_codec */ 2685 codec->private_data = card; 2686 codec->id = num_ac97; 2687 2688 codec->codec_read = i810_ac97_get; 2689 codec->codec_write = i810_ac97_set; 2690 2691 if(!i810_ac97_probe_and_powerup(card,codec)) { 2692 printk("i810_audio: timed out waiting for codec %d analog ready.\n", num_ac97); 2693 kfree(codec); 2694 break; /* it didn't work */ 2695 } 2696 /* Store state information about S/PDIF transmitter */ 2697 card->ac97_status = 0; 2698 2699 /* Don't attempt to get eid until powerup is complete */ 2700 eid = i810_ac97_get(codec, AC97_EXTENDED_ID); 2701 2702 if(eid==0xFFFFFF) 2703 { 2704 printk(KERN_WARNING "i810_audio: no codec attached ?\n"); 2705 kfree(codec); 2706 break; 2707 } 2708 2709 codec->codec_write(codec, AC97_EXTENDED_MODEM_ID, 0L); 2710 if(codec->codec_read(codec, AC97_EXTENDED_MODEM_ID)) 2711 { 2712 printk(KERN_WARNING "i810_audio: codec %d is a softmodem - skipping.\n", num_ac97); 2713 kfree(codec); 2714 continue; 2715 } 2716 2717 card->ac97_features = eid; 2718 2719 /* Now check the codec for useful features to make up for 2720 the dumbness of the 810 hardware engine */ 2721 2722 if(!(eid&0x0001)) 2723 printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n"); 2724 else 2725 { 2726 if(!i810_ac97_enable_variable_rate(codec)) { 2727 printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n"); 2728 card->ac97_features&=~1; 2729 } 2730 } 2731 2732 /* Determine how many channels the codec(s) support */ 2733 /* - The primary codec always supports 2 */ 2734 /* - If the codec supports AMAP, surround DACs will */ 2735 /* automaticlly get assigned to slots. */ 2736 /* * Check for surround DACs and increment if */ 2737 /* found. */ 2738 /* - Else check if the codec is revision 2.2 */ 2739 /* * If surround DACs exist, assign them to slots */ 2740 /* and increment channel count. */ 2741 2742 /* All of this only applies to ICH2 and above. ICH */ 2743 /* and ICH0 only support 2 channels. ICH2 will only */ 2744 /* support multiple codecs in a "split audio" config. */ 2745 /* as described above. */ 2746 2747 /* TODO: Remove all the debugging messages! */ 2748 2749 if((eid & 0xc000) == 0) /* primary codec */ 2750 total_channels += 2; 2751 2752 if(eid & 0x200) { /* GOOD, AMAP support */ 2753 if (eid & 0x0080) /* L/R Surround channels */ 2754 total_channels += 2; 2755 if (eid & 0x0140) /* LFE and Center channels */ 2756 total_channels += 2; 2757 printk("i810_audio: AC'97 codec %d supports AMAP, total channels = %d\n", num_ac97, total_channels); 2758 } else if (eid & 0x0400) { /* this only works on 2.2 compliant codecs */ 2759 eid &= 0xffcf; 2760 if((eid & 0xc000) != 0) { 2761 switch ( total_channels ) { 2762 case 2: 2763 /* Set dsa1, dsa0 to 01 */ 2764 eid |= 0x0010; 2765 break; 2766 case 4: 2767 /* Set dsa1, dsa0 to 10 */ 2768 eid |= 0x0020; 2769 break; 2770 case 6: 2771 /* Set dsa1, dsa0 to 11 */ 2772 eid |= 0x0030; 2773 break; 2774 } 2775 total_channels += 2; 2776 } 2777 i810_ac97_set(codec, AC97_EXTENDED_ID, eid); 2778 eid = i810_ac97_get(codec, AC97_EXTENDED_ID); 2779 printk("i810_audio: AC'97 codec %d, new EID value = 0x%04x\n", num_ac97, eid); 2780 if (eid & 0x0080) /* L/R Surround channels */ 2781 total_channels += 2; 2782 if (eid & 0x0140) /* LFE and Center channels */ 2783 total_channels += 2; 2784 printk("i810_audio: AC'97 codec %d, DAC map configured, total channels = %d\n", num_ac97, total_channels); 2785 } else { 2786 printk("i810_audio: AC'97 codec %d Unable to map surround DAC's (or DAC's not present), total channels = %d\n", num_ac97, total_channels); 2787 } 2788 2789 if ((codec->dev_mixer = register_sound_mixer(&i810_mixer_fops, -1)) < 0) { 2790 printk(KERN_ERR "i810_audio: couldn't register mixer!\n"); 2791 kfree(codec); 2792 break; 2793 } 2794 2795 card->ac97_codec[num_ac97] = codec; 2796 } 2797 2798 /* pick the minimum of channels supported by ICHx or codec(s) */ 2799 card->channels = (card->channels > total_channels)?total_channels:card->channels; 2800 2801 return num_ac97; 2802} 2803 2804static void __init i810_configure_clocking (void) 2805{ 2806 struct i810_card *card; 2807 struct i810_state *state; 2808 struct dmabuf *dmabuf; 2809 unsigned int i, offset, new_offset; 2810 unsigned long flags; 2811 2812 card = devs; 2813 /* We could try to set the clocking for multiple cards, but can you even have 2814 * more than one i810 in a machine? Besides, clocking is global, so unless 2815 * someone actually thinks more than one i810 in a machine is possible and 2816 * decides to rewrite that little bit, setting the rate for more than one card 2817 * is a waste of time. 2818 */ 2819 if(card != NULL) { 2820 state = card->states[0] = (struct i810_state *) 2821 kmalloc(sizeof(struct i810_state), GFP_KERNEL); 2822 if (state == NULL) 2823 return; 2824 memset(state, 0, sizeof(struct i810_state)); 2825 dmabuf = &state->dmabuf; 2826 2827 dmabuf->write_channel = card->alloc_pcm_channel(card); 2828 state->virt = 0; 2829 state->card = card; 2830 state->magic = I810_STATE_MAGIC; 2831 init_waitqueue_head(&dmabuf->wait); 2832 init_MUTEX(&state->open_sem); 2833 dmabuf->fmt = I810_FMT_STEREO | I810_FMT_16BIT; 2834 dmabuf->trigger = PCM_ENABLE_OUTPUT; 2835 i810_set_dac_rate(state, 48000); 2836 if(prog_dmabuf(state, 0) != 0) { 2837 goto config_out_nodmabuf; 2838 } 2839 if(dmabuf->dmasize < 16384) { 2840 goto config_out; 2841 } 2842 dmabuf->count = dmabuf->dmasize; 2843 outb(31,card->iobase+dmabuf->write_channel->port+OFF_LVI); 2844 save_flags(flags); 2845 cli(); 2846 start_dac(state); 2847 offset = i810_get_dma_addr(state, 0); 2848 mdelay(50); 2849 new_offset = i810_get_dma_addr(state, 0); 2850 stop_dac(state); 2851 outb(2,card->iobase+dmabuf->write_channel->port+OFF_CR); 2852 restore_flags(flags); 2853 i = new_offset - offset; 2854#ifdef DEBUG 2855 printk("i810_audio: %d bytes in 50 milliseconds\n", i); 2856#endif 2857 if(i == 0) 2858 goto config_out; 2859 i = i / 4 * 20; 2860 if (i > 48500 || i < 47500) { 2861 clocking = clocking * clocking / i; 2862 printk("i810_audio: setting clocking to %d\n", clocking); 2863 } 2864config_out: 2865 dealloc_dmabuf(state); 2866config_out_nodmabuf: 2867 state->card->free_pcm_channel(state->card,state->dmabuf.write_channel->num); 2868 kfree(state); 2869 card->states[0] = NULL; 2870 } 2871} 2872 2873/* install the driver, we do not allocate hardware channel nor DMA buffer now, they are defered 2874 until "ACCESS" time (in prog_dmabuf called by open/read/write/ioctl/mmap) */ 2875 2876static int __init i810_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id) 2877{ 2878 struct i810_card *card; 2879 2880 if (pci_enable_device(pci_dev)) 2881 return -EIO; 2882 2883 if (pci_set_dma_mask(pci_dev, I810_DMA_MASK)) { 2884 printk(KERN_ERR "intel810: architecture does not support" 2885 " 32bit PCI busmaster DMA\n"); 2886 return -ENODEV; 2887 } 2888 2889 if ((card = kmalloc(sizeof(struct i810_card), GFP_KERNEL)) == NULL) { 2890 printk(KERN_ERR "i810_audio: out of memory\n"); 2891 return -ENOMEM; 2892 } 2893 memset(card, 0, sizeof(*card)); 2894 2895 card->initializing = 1; 2896 card->iobase = pci_resource_start (pci_dev, 1); 2897 card->ac97base = pci_resource_start (pci_dev, 0); 2898 card->pci_dev = pci_dev; 2899 card->pci_id = pci_id->device; 2900 card->irq = pci_dev->irq; 2901 card->next = devs; 2902 card->magic = I810_CARD_MAGIC; 2903#ifdef CONFIG_PM 2904 card->pm_suspended=0; 2905#endif 2906 spin_lock_init(&card->lock); 2907 devs = card; 2908 2909 pci_set_master(pci_dev); 2910 2911 printk(KERN_INFO "i810: %s found at IO 0x%04lx and 0x%04lx, IRQ %d\n", 2912 card_names[pci_id->driver_data], card->iobase, card->ac97base, 2913 card->irq); 2914 2915 card->alloc_pcm_channel = i810_alloc_pcm_channel; 2916 card->alloc_rec_pcm_channel = i810_alloc_rec_pcm_channel; 2917 card->alloc_rec_mic_channel = i810_alloc_rec_mic_channel; 2918 card->free_pcm_channel = i810_free_pcm_channel; 2919 card->channel[0].offset = 0; 2920 card->channel[0].port = 0x00; 2921 card->channel[0].num=0; 2922 card->channel[1].offset = 0; 2923 card->channel[1].port = 0x10; 2924 card->channel[1].num=1; 2925 card->channel[2].offset = 0; 2926 card->channel[2].port = 0x20; 2927 card->channel[2].num=2; 2928 2929 /* claim our iospace and irq */ 2930 request_region(card->iobase, 64, card_names[pci_id->driver_data]); 2931 request_region(card->ac97base, 256, card_names[pci_id->driver_data]); 2932 2933 if (request_irq(card->irq, &i810_interrupt, SA_SHIRQ, 2934 card_names[pci_id->driver_data], card)) { 2935 printk(KERN_ERR "i810_audio: unable to allocate irq %d\n", card->irq); 2936 release_region(card->iobase, 64); 2937 release_region(card->ac97base, 256); 2938 kfree(card); 2939 return -ENODEV; 2940 } 2941 2942 /* initialize AC97 codec and register /dev/mixer */ 2943 if (i810_ac97_init(card) <= 0) { 2944 release_region(card->iobase, 64); 2945 release_region(card->ac97base, 256); 2946 free_irq(card->irq, card); 2947 kfree(card); 2948 return -ENODEV; 2949 } 2950 pci_set_drvdata(pci_dev, card); 2951 2952 if(clocking == 0) { 2953 clocking = 48000; 2954 i810_configure_clocking(); 2955 } 2956 2957 /* register /dev/dsp */ 2958 if ((card->dev_audio = register_sound_dsp(&i810_audio_fops, -1)) < 0) { 2959 int i; 2960 printk(KERN_ERR "i810_audio: couldn't register DSP device!\n"); 2961 release_region(card->iobase, 64); 2962 release_region(card->ac97base, 256); 2963 free_irq(card->irq, card); 2964 for (i = 0; i < NR_AC97; i++) 2965 if (card->ac97_codec[i] != NULL) { 2966 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer); 2967 kfree (card->ac97_codec[i]); 2968 } 2969 kfree(card); 2970 return -ENODEV; 2971 } 2972 card->initializing = 0; 2973 return 0; 2974} 2975 2976static void __devexit i810_remove(struct pci_dev *pci_dev) 2977{ 2978 int i; 2979 struct i810_card *card = pci_get_drvdata(pci_dev); 2980 /* free hardware resources */ 2981 free_irq(card->irq, devs); 2982 release_region(card->iobase, 64); 2983 release_region(card->ac97base, 256); 2984 2985 /* unregister audio devices */ 2986 for (i = 0; i < NR_AC97; i++) 2987 if (card->ac97_codec[i] != NULL) { 2988 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer); 2989 kfree (card->ac97_codec[i]); 2990 card->ac97_codec[i] = NULL; 2991 } 2992 unregister_sound_dsp(card->dev_audio); 2993 kfree(card); 2994} 2995 2996#ifdef CONFIG_PM 2997static int i810_pm_suspend(struct pci_dev *dev, u32 pm_state) 2998{ 2999 struct i810_card *card = pci_get_drvdata(dev); 3000 struct i810_state *state; 3001 unsigned long flags; 3002 struct dmabuf *dmabuf; 3003 int i,num_ac97; 3004#ifdef DEBUG 3005 printk("i810_audio: i810_pm_suspend called\n"); 3006#endif 3007 if(!card) return 0; 3008 spin_lock_irqsave(&card->lock, flags); 3009 card->pm_suspended=1; 3010 for(i=0;i<NR_HW_CH;i++) { 3011 state = card->states[i]; 3012 if(!state) continue; 3013 /* this happens only if there are open files */ 3014 dmabuf = &state->dmabuf; 3015 if(dmabuf->enable & DAC_RUNNING || 3016 (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) { 3017 state->pm_saved_dac_rate=dmabuf->rate; 3018 stop_dac(state); 3019 } else { 3020 state->pm_saved_dac_rate=0; 3021 } 3022 if(dmabuf->enable & ADC_RUNNING) { 3023 state->pm_saved_adc_rate=dmabuf->rate; 3024 stop_adc(state); 3025 } else { 3026 state->pm_saved_adc_rate=0; 3027 } 3028 dmabuf->ready = 0; 3029 dmabuf->swptr = dmabuf->hwptr = 0; 3030 dmabuf->count = dmabuf->total_bytes = 0; 3031 } 3032 3033 spin_unlock_irqrestore(&card->lock, flags); 3034 3035 /* save mixer settings */ 3036 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) { 3037 struct ac97_codec *codec = card->ac97_codec[num_ac97]; 3038 if(!codec) continue; 3039 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) { 3040 if((supported_mixer(codec,i)) && 3041 (codec->read_mixer)) { 3042 card->pm_saved_mixer_settings[i][num_ac97]= 3043 codec->read_mixer(codec,i); 3044 } 3045 } 3046 } 3047 pci_save_state(dev,card->pm_save_state); 3048 pci_disable_device(dev); /* disable busmastering */ 3049 pci_set_power_state(dev,3); /* Zzz. */ 3050 3051 return 0; 3052} 3053 3054 3055static int i810_pm_resume(struct pci_dev *dev) 3056{ 3057 int num_ac97,i=0; 3058 struct i810_card *card=pci_get_drvdata(dev); 3059 pci_enable_device(dev); 3060 pci_restore_state (dev,card->pm_save_state); 3061 3062 /* observation of a toshiba portege 3440ct suggests that the 3063 hardware has to be more or less completely reinitialized from 3064 scratch after an apm suspend. Works For Me. -dan */ 3065 3066 i810_ac97_random_init_stuff(card); 3067 3068 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) { 3069 struct ac97_codec *codec = card->ac97_codec[num_ac97]; 3070 /* check they haven't stolen the hardware while we were 3071 away */ 3072 if(!codec || !i810_ac97_exists(card,num_ac97)) { 3073 if(num_ac97) continue; 3074 else BUG(); 3075 } 3076 if(!i810_ac97_probe_and_powerup(card,codec)) BUG(); 3077 3078 if((card->ac97_features&0x0001)) { 3079 /* at probe time we found we could do variable 3080 rates, but APM suspend has made it forget 3081 its magical powers */ 3082 if(!i810_ac97_enable_variable_rate(codec)) BUG(); 3083 } 3084 /* we lost our mixer settings, so restore them */ 3085 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) { 3086 if(supported_mixer(codec,i)){ 3087 int val=card-> 3088 pm_saved_mixer_settings[i][num_ac97]; 3089 codec->mixer_state[i]=val; 3090 codec->write_mixer(codec,i, 3091 (val & 0xff) , 3092 ((val >> 8) & 0xff) ); 3093 } 3094 } 3095 } 3096 3097 /* we need to restore the sample rate from whatever it was */ 3098 for(i=0;i<NR_HW_CH;i++) { 3099 struct i810_state * state=card->states[i]; 3100 if(state) { 3101 if(state->pm_saved_adc_rate) 3102 i810_set_adc_rate(state,state->pm_saved_adc_rate); 3103 if(state->pm_saved_dac_rate) 3104 i810_set_dac_rate(state,state->pm_saved_dac_rate); 3105 } 3106 } 3107 3108 3109 card->pm_suspended = 0; 3110 3111 /* any processes that were reading/writing during the suspend 3112 probably ended up here */ 3113 for(i=0;i<NR_HW_CH;i++) { 3114 struct i810_state *state = card->states[i]; 3115 if(state) wake_up(&state->dmabuf.wait); 3116 } 3117 3118 return 0; 3119} 3120#endif /* CONFIG_PM */ 3121 3122MODULE_AUTHOR(""); 3123MODULE_DESCRIPTION("Intel 810 audio support"); 3124MODULE_LICENSE("GPL"); 3125MODULE_PARM(ftsodell, "i"); 3126MODULE_PARM(clocking, "i"); 3127MODULE_PARM(strict_clocking, "i"); 3128MODULE_PARM(spdif_locked, "i"); 3129 3130#define I810_MODULE_NAME "intel810_audio" 3131 3132static struct pci_driver i810_pci_driver = { 3133 name: I810_MODULE_NAME, 3134 id_table: i810_pci_tbl, 3135 probe: i810_probe, 3136 remove: __devexit_p(i810_remove), 3137#ifdef CONFIG_PM 3138 suspend: i810_pm_suspend, 3139 resume: i810_pm_resume, 3140#endif /* CONFIG_PM */ 3141}; 3142 3143 3144static int __init i810_init_module (void) 3145{ 3146 if (!pci_present()) /* No PCI bus in this machine! */ 3147 return -ENODEV; 3148 3149 printk(KERN_INFO "Intel 810 + AC97 Audio, version " 3150 DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n"); 3151 3152 if (!pci_register_driver(&i810_pci_driver)) { 3153 pci_unregister_driver(&i810_pci_driver); 3154 return -ENODEV; 3155 } 3156 if(ftsodell != 0) { 3157 printk("i810_audio: ftsodell is now a deprecated option.\n"); 3158 } 3159 if(spdif_locked > 0 ) { 3160 if(spdif_locked == 32000 || spdif_locked == 44100 || spdif_locked == 48000) { 3161 printk("i810_audio: Enabling S/PDIF at sample rate %dHz.\n", spdif_locked); 3162 } else { 3163 printk("i810_audio: S/PDIF can only be locked to 32000, 44100, or 48000Hz.\n"); 3164 spdif_locked = 0; 3165 } 3166 } 3167 3168 return 0; 3169} 3170 3171static void __exit i810_cleanup_module (void) 3172{ 3173 pci_unregister_driver(&i810_pci_driver); 3174} 3175 3176module_init(i810_init_module); 3177module_exit(i810_cleanup_module); 3178 3179/* 3180Local Variables: 3181c-basic-offset: 8 3182End: 3183*/ 3184