1/*
2 *    wd33c93.h -  Linux device driver definitions for the
3 *                 Commodore Amiga A2091/590 SCSI controller card
4 *
5 *    IMPORTANT: This file is for version 1.25 - 09/Jul/1997
6 *
7 * Copyright (c) 1996 John Shifflett, GeoLog Consulting
8 *    john@geolog.com
9 *    jshiffle@netcom.com
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 */
22#ifndef WD33C93_H
23#define WD33C93_H
24
25#define PROC_INTERFACE
26#ifdef  PROC_INTERFACE
27#define PROC_STATISTICS    /* add code for keeping various real time stats */
28#endif
29
30#define SYNC_DEBUG         /* extra info on sync negotiation printed */
31#define DEBUGGING_ON       /* enable command-line debugging bitmask */
32#define DEBUG_DEFAULTS 0   /* default debugging bitmask */
33
34
35#ifdef DEBUGGING_ON
36#define DB(f,a) if (hostdata->args & (f)) a;
37#else
38#define DB(f,a)
39#endif
40
41#define uchar unsigned char
42
43
44/* wd register names */
45#define WD_OWN_ID    0x00
46#define WD_CONTROL      0x01
47#define WD_TIMEOUT_PERIOD  0x02
48#define WD_CDB_1     0x03
49#define WD_CDB_2     0x04
50#define WD_CDB_3     0x05
51#define WD_CDB_4     0x06
52#define WD_CDB_5     0x07
53#define WD_CDB_6     0x08
54#define WD_CDB_7     0x09
55#define WD_CDB_8     0x0a
56#define WD_CDB_9     0x0b
57#define WD_CDB_10    0x0c
58#define WD_CDB_11    0x0d
59#define WD_CDB_12    0x0e
60#define WD_TARGET_LUN      0x0f
61#define WD_COMMAND_PHASE   0x10
62#define WD_SYNCHRONOUS_TRANSFER 0x11
63#define WD_TRANSFER_COUNT_MSB 0x12
64#define WD_TRANSFER_COUNT  0x13
65#define WD_TRANSFER_COUNT_LSB 0x14
66#define WD_DESTINATION_ID  0x15
67#define WD_SOURCE_ID    0x16
68#define WD_SCSI_STATUS     0x17
69#define WD_COMMAND      0x18
70#define WD_DATA      0x19
71#define WD_QUEUE_TAG    0x1a
72#define WD_AUXILIARY_STATUS   0x1f
73
74/* WD commands */
75#define WD_CMD_RESET    0x00
76#define WD_CMD_ABORT    0x01
77#define WD_CMD_ASSERT_ATN  0x02
78#define WD_CMD_NEGATE_ACK  0x03
79#define WD_CMD_DISCONNECT  0x04
80#define WD_CMD_RESELECT    0x05
81#define WD_CMD_SEL_ATN     0x06
82#define WD_CMD_SEL      0x07
83#define WD_CMD_SEL_ATN_XFER   0x08
84#define WD_CMD_SEL_XFER    0x09
85#define WD_CMD_RESEL_RECEIVE  0x0a
86#define WD_CMD_RESEL_SEND  0x0b
87#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
88#define WD_CMD_TRANS_ADDR  0x18
89#define WD_CMD_TRANS_INFO  0x20
90#define WD_CMD_TRANSFER_PAD   0x21
91#define WD_CMD_SBT_MODE    0x80
92
93/* ASR register */
94#define ASR_INT         (0x80)
95#define ASR_LCI         (0x40)
96#define ASR_BSY         (0x20)
97#define ASR_CIP         (0x10)
98#define ASR_PE          (0x02)
99#define ASR_DBR         (0x01)
100
101/* SCSI Bus Phases */
102#define PHS_DATA_OUT    0x00
103#define PHS_DATA_IN     0x01
104#define PHS_COMMAND     0x02
105#define PHS_STATUS      0x03
106#define PHS_MESS_OUT    0x06
107#define PHS_MESS_IN     0x07
108
109/* Command Status Register definitions */
110
111  /* reset state interrupts */
112#define CSR_RESET    0x00
113#define CSR_RESET_AF    0x01
114
115  /* successful completion interrupts */
116#define CSR_RESELECT    0x10
117#define CSR_SELECT      0x11
118#define CSR_SEL_XFER_DONE  0x16
119#define CSR_XFER_DONE      0x18
120
121  /* paused or aborted interrupts */
122#define CSR_MSGIN    0x20
123#define CSR_SDP         0x21
124#define CSR_SEL_ABORT      0x22
125#define CSR_RESEL_ABORT    0x25
126#define CSR_RESEL_ABORT_AM 0x27
127#define CSR_ABORT    0x28
128
129  /* terminated interrupts */
130#define CSR_INVALID     0x40
131#define CSR_UNEXP_DISC     0x41
132#define CSR_TIMEOUT     0x42
133#define CSR_PARITY      0x43
134#define CSR_PARITY_ATN     0x44
135#define CSR_BAD_STATUS     0x45
136#define CSR_UNEXP    0x48
137
138  /* service required interrupts */
139#define CSR_RESEL    0x80
140#define CSR_RESEL_AM    0x81
141#define CSR_DISC     0x85
142#define CSR_SRV_REQ     0x88
143
144   /* Own ID/CDB Size register */
145#define OWNID_EAF    0x08
146#define OWNID_EHP    0x10
147#define OWNID_RAF    0x20
148#define OWNID_FS_8   0x00
149#define OWNID_FS_12  0x40
150#define OWNID_FS_16  0x80
151
152   /* define these so we don't have to change a2091.c, etc. */
153#define WD33C93_FS_8_10  OWNID_FS_8
154#define WD33C93_FS_12_15 OWNID_FS_12
155#define WD33C93_FS_16_20 OWNID_FS_16
156
157   /* Control register */
158#define CTRL_HSP     0x01
159#define CTRL_HA      0x02
160#define CTRL_IDI     0x04
161#define CTRL_EDI     0x08
162#define CTRL_HHP     0x10
163#define CTRL_POLLED  0x00
164#define CTRL_BURST   0x20
165#define CTRL_BUS     0x40
166#define CTRL_DMA     0x80
167
168   /* Timeout Period register */
169#define TIMEOUT_PERIOD_VALUE  20    /* 20 = 200 ms */
170
171   /* Synchronous Transfer Register */
172#define STR_FSS      0x80
173
174   /* Destination ID register */
175#define DSTID_DPD    0x40
176#define DATA_OUT_DIR 0
177#define DATA_IN_DIR  1
178#define DSTID_SCC    0x80
179
180   /* Source ID register */
181#define SRCID_MASK   0x07
182#define SRCID_SIV    0x08
183#define SRCID_DSP    0x20
184#define SRCID_ES     0x40
185#define SRCID_ER     0x80
186
187   /* This is what the 3393 chip looks like to us */
188typedef struct {
189   volatile unsigned char  *SASR;
190   volatile unsigned char  *SCMD;
191} wd33c93_regs;
192
193
194typedef int (*dma_setup_t) (Scsi_Cmnd *SCpnt, int dir_in);
195typedef void (*dma_stop_t) (struct Scsi_Host *instance, Scsi_Cmnd *SCpnt,
196             int status);
197
198
199#define ILLEGAL_STATUS_BYTE   0xff
200
201#define DEFAULT_SX_PER   376     /* (ns) fairly safe */
202#define DEFAULT_SX_OFF   0       /* aka async */
203
204#define OPTIMUM_SX_PER   252     /* (ns) best we can do (mult-of-4) */
205#define OPTIMUM_SX_OFF   12      /* size of wd3393 fifo */
206
207struct sx_period {
208   unsigned int   period_ns;
209   uchar          reg_value;
210   };
211
212/* FEF: defines for hostdata->dma_buffer_pool */
213
214#define BUF_CHIP_ALLOCED 0
215#define BUF_SCSI_ALLOCED 1
216
217struct WD33C93_hostdata {
218    struct Scsi_Host *next;
219    wd33c93_regs     regs;
220    uchar            clock_freq;
221    uchar            chip;             /* what kind of wd33c93? */
222    uchar            microcode;        /* microcode rev */
223    uchar            dma_buffer_pool;  /* FEF: buffer from chip_ram? */
224    int              dma_dir;          /* data transfer dir. */
225    dma_setup_t      dma_setup;
226    dma_stop_t       dma_stop;
227    unsigned int     dma_xfer_mask;
228    uchar            *dma_bounce_buffer;
229    unsigned int     dma_bounce_len;
230    volatile uchar   busy[8];          /* index = target, bit = lun */
231    volatile Scsi_Cmnd *input_Q;       /* commands waiting to be started */
232    volatile Scsi_Cmnd *selecting;     /* trying to select this command */
233    volatile Scsi_Cmnd *connected;     /* currently connected command */
234    volatile Scsi_Cmnd *disconnected_Q;/* commands waiting for reconnect */
235    uchar            state;            /* what we are currently doing */
236    uchar            dma;              /* current state of DMA (on/off) */
237    uchar            level2;           /* extent to which Level-2 commands are used */
238    uchar            disconnect;       /* disconnect/reselect policy */
239    unsigned int     args;             /* set from command-line argument */
240    uchar            incoming_msg[8];  /* filled during message_in phase */
241    int              incoming_ptr;     /* mainly used with EXTENDED messages */
242    uchar            outgoing_msg[8];  /* send this during next message_out */
243    int              outgoing_len;     /* length of outgoing message */
244    unsigned int     default_sx_per;   /* default transfer period for SCSI bus */
245    uchar            sync_xfer[8];     /* sync_xfer reg settings per target */
246    uchar            sync_stat[8];     /* status of sync negotiation per target */
247    uchar            no_sync;          /* bitmask: don't do sync on these targets */
248    uchar            no_dma;           /* set this flag to disable DMA */
249#ifdef PROC_INTERFACE
250    uchar            proc;             /* bitmask: what's in proc output */
251#ifdef PROC_STATISTICS
252    unsigned long    cmd_cnt[8];       /* # of commands issued per target */
253    unsigned long    int_cnt;          /* # of interrupts serviced */
254    unsigned long    pio_cnt;          /* # of pio data transfers */
255    unsigned long    dma_cnt;          /* # of DMA data transfers */
256    unsigned long    disc_allowed_cnt[8]; /* # of disconnects allowed per target */
257    unsigned long    disc_done_cnt[8]; /* # of disconnects done per target*/
258#endif
259#endif
260    };
261
262
263/* defines for hostdata->chip */
264
265#define C_WD33C93       0
266#define C_WD33C93A      1
267#define C_WD33C93B      2
268#define C_UNKNOWN_CHIP  100
269
270/* defines for hostdata->state */
271
272#define S_UNCONNECTED         0
273#define S_SELECTING           1
274#define S_RUNNING_LEVEL2      2
275#define S_CONNECTED           3
276#define S_PRE_TMP_DISC        4
277#define S_PRE_CMP_DISC        5
278
279/* defines for hostdata->dma */
280
281#define D_DMA_OFF          0
282#define D_DMA_RUNNING      1
283
284/* defines for hostdata->level2 */
285/* NOTE: only the first 3 are implemented so far */
286
287#define L2_NONE      1  /* no combination commands - we get lots of ints */
288#define L2_SELECT    2  /* start with SEL_ATN_XFER, but never resume it */
289#define L2_BASIC     3  /* resume after STATUS ints & RDP messages */
290#define L2_DATA      4  /* resume after DATA_IN/OUT ints */
291#define L2_MOST      5  /* resume after anything except a RESELECT int */
292#define L2_RESELECT  6  /* resume after everything, including RESELECT ints */
293#define L2_ALL       7  /* always resume */
294
295/* defines for hostdata->disconnect */
296
297#define DIS_NEVER    0
298#define DIS_ADAPTIVE 1
299#define DIS_ALWAYS   2
300
301/* defines for hostdata->args */
302
303#define DB_TEST1              1<<0
304#define DB_TEST2              1<<1
305#define DB_QUEUE_COMMAND      1<<2
306#define DB_EXECUTE            1<<3
307#define DB_INTR               1<<4
308#define DB_TRANSFER           1<<5
309#define DB_MASK               0x3f
310
311/* defines for hostdata->sync_stat[] */
312
313#define SS_UNSET     0
314#define SS_FIRST     1
315#define SS_WAITING   2
316#define SS_SET       3
317
318/* defines for hostdata->proc */
319
320#define PR_VERSION   1<<0
321#define PR_INFO      1<<1
322#define PR_STATISTICS 1<<2
323#define PR_CONNECTED 1<<3
324#define PR_INPUTQ    1<<4
325#define PR_DISCQ     1<<5
326#define PR_TEST      1<<6
327#define PR_STOP      1<<7
328
329
330void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
331         dma_setup_t setup, dma_stop_t stop, int clock_freq);
332int wd33c93_abort (Scsi_Cmnd *cmd);
333int wd33c93_queuecommand (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
334void wd33c93_intr (struct Scsi_Host *instance);
335int wd33c93_proc_info(char *, char **, off_t, int, int, int);
336int wd33c93_reset (Scsi_Cmnd *, unsigned int);
337void wd33c93_release(void);
338
339#endif /* WD33C93_H */
340