1/************************************************************************* 2 * QLOGIC LINUX SOFTWARE 3 * 4 * QLogic ISP1x80/1x160 device driver for Linux 2.3.x (redhat 6.x). 5 * 6 * COPYRIGHT (C) 1996-2000 QLOGIC CORPORATION 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the Qlogic's Linux Software License. 10 * 11 * This program is WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 18 * 1. Redistribution's or source code must retain the above copyright 19 * notice, this list of conditions, and the following disclaimer, 20 * without modification, immediately at the beginning of the file. 21 * 2. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 *****************************************************************************/ 25 26/************************************************************************************* 27 QLOGIC CORPORATION SOFTWARE 28 "GNU" GENERAL PUBLIC LICENSE 29 TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION 30 AND MODIFICATION 31 32This GNU General Public License ("License") applies solely to QLogic Linux 33Software ("Software") and may be distributed under the terms of this License. 34 351. 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Any attempt otherwise to copy, modify, sublicense or 104distribute the Software is void, and will automatically terminate your rights under this 105License. However, parties who have received copies, or rights, from you under this License 106will not have their licenses terminated so long as such parties remain in full compliance. 107 1085. This license grants you world wide, royalty free non-exclusive rights to modify or 109distribute the Software or its derivative works. These actions are prohibited by law 110if you do not accept this License. Therefore, by modifying or distributing the Software 111(or any work based on the Software), you indicate your acceptance of this License to do 112so, and all its terms and conditions for copying, distributing or modifying the Software 113or works based on it. 114 1156. Each time you redistribute the Software (or any work based on the Software), the 116recipient automatically receives a license from the original licensor to copy, distribute 117or modify the Software subject to these terms and conditions. You may not impose any 118further restrictions on the recipients' exercise of the rights granted herein. You are 119not responsible for enforcing compliance by third parties to this License. 120 1217. If, as a consequence of a court judgment or allegation of patent infringement or for 122any other reason (not limited to patent issues), conditions are imposed on you 123(whether by court order, agreement or otherwise) that contradict the conditions of this 124License, they do not excuse you from the conditions of this License. If you cannot 125distribute so as to satisfy simultaneously your obligations under this License 126and any other pertinent obligations, then as a consequence you may not distribute the 127Software at all. 128 129If any portion of this section is held invalid or unenforceable under any particular 130circumstance, the balance of the section is intended to apply and the section as a whole 131is intended to apply in other circumstances. 132NO WARRANTY 133 13411. THE SOFTWARE IS PROVIDED WITHOUT A WARRANTY OF ANY KIND. THERE IS NO 135WARRANTY FOR THE SOFTWARE, TO THE EXTENT PERMITTED BY APPLICABLE LAW. 136EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR 137OTHER PARTIES PROVIDE THE SOFTWARE "AS IS" WITHOUT WARRANTY OF ANY KIND, 138EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 139WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE 140ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE SOFTWARE IS WITH YOU. 141SHOULD THE SOFTWARE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL 142NECESSARY SERVICING, REPAIR OR CORRECTION. 143 14412. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 145WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR 146REDISTRIBUTE THE SOFTWARE AS PERMITTED ABOVE, BE LIABLE TO YOU FOR 147DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL 148DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE SOFTWARE (INCLUDING 149BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR 150LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE SOFTWARE TO 151OPERATE WITH ANY OTHER SOFTWARES), EVEN IF SUCH HOLDER OR OTHER PARTY HAS 152BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 153END OF TERMS AND CONDITIONS 154 155*************************************************************************************/ 156 157 158#ifndef _IO_HBA_QLA1280_H /* wrapper symbol for kernel use */ 159#define _IO_HBA_QLA1280_H /* subject to change without notice */ 160 161#if defined(__cplusplus) 162extern "C" { 163#endif 164 165#include <linux/version.h> 166 167/* 168 * Enable define statement to ignore Data Underrun Errors, 169 * remove define statement to enable detection. 170 */ 171/* #define DATA_UNDERRUN_ERROR_DISABLE */ 172 173/* 174 * Driver debug definitions. 175 */ 176/* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM2. */ 177/* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM2. */ 178/* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM2. */ 179/* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM2. */ 180/* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM2. */ 181/* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM2. */ 182/* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM2. */ 183 184#define QL_DEBUG_CONSOLE /* Output to console instead of COM2. */ 185 186#ifndef TRUE 187# define TRUE 1 188#endif 189#ifndef FALSE 190# define FALSE 0 191#endif 192 193 194#ifndef KERNEL_VERSION 195# define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z)) 196#endif 197 198#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,92) 199# if defined(__sparc_v9__) || defined(__powerpc__) 200# error "PPC and Sparc platforms are only support under 2.1.92 and above" 201# endif 202#endif 203 204 205/* 206 * Locking 207 */ 208#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0) 209# include <linux/spinlock.h> 210# include <linux/smp.h> 211# define cpuid smp_processor_id() 212# if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) 213# define DRIVER_LOCK_INIT \ 214 spin_lock_init(&ha->spin_lock); 215# define DRIVER_LOCK \ 216 if(!ha->cpu_lock_count[cpuid]) { \ 217 spin_lock_irqsave(&ha->spin_lock, cpu_flags); \ 218 ha->cpu_lock_count[cpuid]++; \ 219 } else { \ 220 ha->cpu_lock_count[cpuid]++; \ 221 } 222# define DRIVER_UNLOCK \ 223 if(--ha->cpu_lock_count[cpuid] == 0) \ 224 spin_unlock_irqrestore(&ha->spin_lock, cpu_flags); 225# else 226# define DRIVER_LOCK_INIT 227# define DRIVER_LOCK 228# define DRIVER_UNLOCK 229# endif 230#else 231# define cpuid 0 232# define DRIVER_LOCK_INIT 233# define DRIVER_LOCK \ 234 save_flags(cpu_flags); \ 235 cli(); 236# define DRIVER_UNLOCK \ 237 restore_flags(cpu_flags); 238# define le32_to_cpu(x) (x) 239# define cpu_to_le32(x) (x) 240#endif 241 242/* 243 * Data bit definitions. 244 */ 245#define BIT_0 0x1 246#define BIT_1 0x2 247#define BIT_2 0x4 248#define BIT_3 0x8 249#define BIT_4 0x10 250#define BIT_5 0x20 251#define BIT_6 0x40 252#define BIT_7 0x80 253#define BIT_8 0x100 254#define BIT_9 0x200 255#define BIT_10 0x400 256#define BIT_11 0x800 257#define BIT_12 0x1000 258#define BIT_13 0x2000 259#define BIT_14 0x4000 260#define BIT_15 0x8000 261#define BIT_16 0x10000 262#define BIT_17 0x20000 263#define BIT_18 0x40000 264#define BIT_19 0x80000 265#define BIT_20 0x100000 266#define BIT_21 0x200000 267#define BIT_22 0x400000 268#define BIT_23 0x800000 269#define BIT_24 0x1000000 270#define BIT_25 0x2000000 271#define BIT_26 0x4000000 272#define BIT_27 0x8000000 273#define BIT_28 0x10000000 274#define BIT_29 0x20000000 275#define BIT_30 0x40000000 276#define BIT_31 0x80000000 277 278/* 279 * Common size type definitions 280 */ 281#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0) 282typedef unsigned char uint8_t; 283typedef unsigned short uint16_t; 284typedef unsigned long uint32_t; 285typedef char int8_t; 286typedef short int16_t; 287typedef long int32_t; 288#endif 289 290/* 291 * Local Macro Definitions. 292 */ 293#if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \ 294 defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \ 295 defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \ 296 defined(QL_DEBUG_LEVEL_7) 297 #define QL_DEBUG_ROUTINES 298#endif 299 300/* 301 * I/O port macros 302*/ 303#define LINUX_IOPORTS /* Linux in/out routines are define*/ 304 /* differently from other OSs */ 305/* #define MEMORY_MAPPED_IO */ /* Enable memory mapped I/O */ 306#undef MEMORY_MAPPED_IO /* Disable memory mapped I/O */ 307 308#ifdef QL_DEBUG_LEVEL_1 309#define RD_REG_BYTE(addr) qla1280_getbyte((uint8_t *)addr) 310#define RD_REG_WORD(addr) qla1280_getword((uint16_t *)addr) 311#define RD_REG_DWORD(addr) qla1280_getdword((uint32_t *)addr) 312#define WRT_REG_BYTE(addr, data) qla1280_putbyte((uint8_t *)addr, data) 313#define WRT_REG_WORD(addr, data) qla1280_putword((uint16_t *)addr, data) 314#define WRT_REG_DWORD(addr, data) qla1280_putdword((uint32_t *)addr, data) 315#else /* QL_DEBUG_LEVEL_1 */ 316#ifdef MEMORY_MAPPED_IO 317 #define RD_REG_BYTE(addr) readb((unsigned long) (addr) 318 #define RD_REG_WORD(addr) readw((unsigned long) (addr) 319 #define RD_REG_DWORD(addr) readl((unsigned long) (addr) 320 #define WRT_REG_BYTE(addr, data) writeb((data), (unsigned long) (addr)) 321 #define WRT_REG_WORD(addr, data) writew((data), (unsigned long) (addr)) 322 #define WRT_REG_DWORD(addr, data) writel((data), (unsigned long) (addr)) 323#else /* MEMORY_MAPPED_IO */ 324#define RD_REG_BYTE(addr) (inb((unsigned long)addr)) 325#define RD_REG_WORD(addr) (inw((unsigned long)addr)) 326#define RD_REG_DWORD(addr) (inl((unsigned long)addr)) 327#ifdef LINUX_IOPORTS 328/* Parameters are reversed in Linux */ 329#define WRT_REG_BYTE(addr, data) (outb(data,(unsigned long)addr)) 330#define WRT_REG_WORD(addr, data) (outw(data,(unsigned long)addr)) 331#define WRT_REG_DWORD(addr, data) (outl(data,(unsigned long)addr)) 332#else 333#define WRT_REG_BYTE(addr, data) (outb((unsigned long)addr, data)) 334#define WRT_REG_WORD(addr, data) (outw((unsigned long)addr, data)) 335#define WRT_REG_DWORD(addr, data) (outl((unsigned long)addr, data)) 336#endif 337#endif /* MEMORY_MAPPED_IO */ 338#endif /* QL_DEBUG_LEVEL_1 */ 339 340/* 341 * Host adapter default definitions. 342 */ 343#define MAX_BUSES 2 /* 2 */ 344#define MAX_B_BITS 1 345 346#define MAX_TARGETS 16 /* 16 */ 347#define MAX_T_BITS 4 /* 4 */ 348 349#define MAX_LUNS 8 /* 32 */ 350#define MAX_L_BITS 3 /* 5 */ 351 352/* 353 * Watchdog time quantum 354 */ 355#define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */ 356 357/* Command retry count (0-65535) */ 358#define COMMAND_RETRY_COUNT 255 359 360/* Maximum outstanding commands in ISP queues (1-65535) */ 361#define MAX_OUTSTANDING_COMMANDS 512 362 363/* ISP request and response entry counts (37-65535) */ 364#define REQUEST_ENTRY_CNT 256 /* Number of request entries. */ 365#define RESPONSE_ENTRY_CNT 16 /* Number of response entries. */ 366 367/* Maximum equipage per controller */ 368#define MAX_EQ (MAX_BUSES * MAX_TARGETS * MAX_LUNS) 369 370/* Number of segments 1 - 65535 */ 371#define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */ 372 373 374/* 375 * SCSI Request Block structure 376 */ 377typedef struct srb 378{ 379 Scsi_Cmnd *cmd; /* (4) SCSI command block */ 380 struct srb *s_next; /* (4) Next block on LU queue */ 381 struct srb *s_prev; /* (4) Previous block on LU queue */ 382 uint8_t flags; /* (1) Status flags. */ 383 uint8_t dir; /* direction of transfer */ 384 uint8_t unused[2]; 385 u_long r_start; /* jiffies at start of request */ 386 u_long u_start; /* jiffies when sent to F/W */ 387}srb_t; 388 389/* 390 * SRB flag definitions 391 */ 392#define SRB_TIMEOUT BIT_0 /* Command timed out */ 393#define SRB_SENT BIT_1 /* Command sent to ISP */ 394#define SRB_ABORT_PENDING BIT_2 /* Command abort sent to device */ 395#define SRB_ABORTED BIT_3 /* Command aborted command already */ 396 397 398/* 399 * Logical Unit Queue structure 400 */ 401typedef struct scsi_lu 402{ 403 srb_t *q_first; /* First block on LU queue */ 404 srb_t *q_last; /* Last block on LU queue */ 405 uint8_t q_flag; /* LU queue state flags */ 406 uint8_t q_sense[16]; /* sense data */ 407 u_long io_cnt; /* total xfer count */ 408 u_long resp_time; /* total response time (start - finish) */ 409 u_long act_time; /* total actived time (minus queuing time) */ 410 u_long w_cnt; /* total writes */ 411 u_long r_cnt; /* total reads */ 412 uint16_t q_outcnt; /* Pending jobs for this LU */ 413#if QL1280_TARGET_MODE_SUPPORT 414 void (*q_func)(); /* Target driver event handler */ 415 int32_t q_param; /* Target driver event param */ 416 uint8_t q_lock; /* Device Queue Lock */ 417#endif 418}scsi_lu_t; 419 420/* 421 * Logical Unit flags 422 */ 423#define QLA1280_QBUSY BIT_0 424#define QLA1280_QWAIT BIT_1 425#define QLA1280_QSUSP BIT_2 426#define QLA1280_QSENSE BIT_3 /* Sense data cache valid */ 427#define QLA1280_QRESET BIT_4 428#define QLA1280_QHBA BIT_5 429#define QLA1280_BSUSP BIT_6 /* controller is suspended */ 430#define QLA1280_BREM BIT_7 /* controller is removed */ 431 432/* 433 * ISP PCI Configuration Register Set 434 */ 435typedef volatile struct 436{ 437 uint16_t vendor_id; /* 0x0 */ 438 uint16_t device_id; /* 0x2 */ 439 uint16_t command; /* 0x4 */ 440 uint16_t status; /* 0x6 */ 441 uint8_t revision_id; /* 0x8 */ 442 uint8_t programming_interface; /* 0x9 */ 443 uint8_t sub_class; /* 0xa */ 444 uint8_t base_class; /* 0xb */ 445 uint8_t cache_line; /* 0xc */ 446 uint8_t latency_timer; /* 0xd */ 447 uint8_t header_type; /* 0xe */ 448 uint8_t bist; /* 0xf */ 449 uint32_t base_port; /* 0x10 */ 450 uint32_t mem_base_addr; /* 0x14 */ 451 uint32_t base_addr[4]; /* 0x18-0x24 */ 452 uint32_t reserved_1[2]; /* 0x28-0x2c */ 453 uint16_t expansion_rom; /* 0x30 */ 454 uint32_t reserved_2[2]; /* 0x34-0x38 */ 455 uint8_t interrupt_line; /* 0x3c */ 456 uint8_t interrupt_pin; /* 0x3d */ 457 uint8_t min_grant; /* 0x3e */ 458 uint8_t max_latency; /* 0x3f */ 459}config_reg_t; 460 461/* 462 * ISP I/O Register Set structure definitions. 463 */ 464typedef volatile struct 465{ 466 uint16_t id_l; /* ID low */ 467 uint16_t id_h; /* ID high */ 468 uint16_t cfg_0; /* Configuration 0 */ 469 uint16_t cfg_1; /* Configuration 1 */ 470 uint16_t ictrl; /* Interface control */ 471 #define ISP_RESET BIT_0 /* ISP soft reset */ 472 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */ 473 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */ 474 uint16_t istatus; /* Interface status */ 475 #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */ 476 #define RISC_INT BIT_2 /* RISC interrupt */ 477 #define PCI_INT BIT_1 /* PCI interrupt */ 478 uint16_t semaphore; /* Semaphore */ 479 uint16_t nvram; /* NVRAM register. */ 480 #define NV_DESELECT 0 481 #define NV_CLOCK BIT_0 482 #define NV_SELECT BIT_1 483 #define NV_DATA_OUT BIT_2 484 #define NV_DATA_IN BIT_3 485 uint16_t flash_data; /* Flash BIOS data */ 486 uint16_t flash_address; /* Flash BIOS address */ 487 488 uint16_t unused_1[0x2e]; /* 0x14-0x6f Gap */ 489 490 uint16_t mailbox0; /* Mailbox 0 */ 491 uint16_t mailbox1; /* Mailbox 1 */ 492 uint16_t mailbox2; /* Mailbox 2 */ 493 uint16_t mailbox3; /* Mailbox 3 */ 494 uint16_t mailbox4; /* Mailbox 4 */ 495 uint16_t mailbox5; /* Mailbox 5 */ 496 uint16_t mailbox6; /* Mailbox 6 */ 497 uint16_t mailbox7; /* Mailbox 7 */ 498 499 uint16_t unused_2[0x20]; /* 0x80-0xbf Gap */ 500 501 uint16_t host_cmd; /* Host command and control */ 502 #define HOST_INT BIT_7 /* host interrupt bit */ 503 #define BIOS_ENABLE BIT_0 504 505 uint16_t unused_6[0x5]; /* 0xc2-0xcb Gap */ 506 507 uint16_t gpio_data; 508 uint16_t gpio_enable; 509 510 uint16_t unused_7[0x11]; /* d0-f0 */ 511 uint16_t scsiControlPins; /* f2 */ 512 513}device_reg_t; 514 515#define MAILBOX_REGISTER_COUNT 8 516 517/* 518 * ISP product identification definitions in mailboxes after reset. 519 */ 520#define PROD_ID_1 0x4953 521#define PROD_ID_2 0x0000 522#define PROD_ID_2a 0x5020 523#define PROD_ID_3 0x2020 524#define PROD_ID_4 0x1 525 526/* 527 * ISP host command and control register command definitions 528 */ 529#define HC_RESET_RISC 0x1000 /* Reset RISC */ 530#define HC_PAUSE_RISC 0x2000 /* Pause RISC */ 531#define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 532#define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ 533#define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 534#define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 535#define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */ 536 537/* 538 * ISP mailbox Self-Test status codes 539 */ 540#define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 541#define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 542#define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */ 543#define MBS_BUSY 4 /* Busy. */ 544 545/* 546 * ISP mailbox command complete status codes 547 */ 548#define MBS_CMD_CMP 0x4000 /* Command Complete. */ 549#define MBS_INV_CMD 0x4001 /* Invalid Command. */ 550#define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */ 551#define MBS_TEST_FAILED 0x4003 /* Test Failed. */ 552#define MBS_CMD_ERR 0x4005 /* Command Error. */ 553#define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */ 554 555/* 556 * ISP mailbox asynchronous event status codes 557 */ 558#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 559#define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */ 560#define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 561#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 562#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 563#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 564#define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */ 565#define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */ 566#define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */ 567#define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */ 568 569/* 570 * ISP mailbox commands 571 */ 572#define MBC_NOP 0 /* No Operation. */ 573#define MBC_LOAD_RAM 1 /* Load RAM. */ 574#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 575#define MBC_WRITE_RAM_WORD 4 /* Write ram word. */ 576#define MBC_READ_RAM_WORD 5 /* Read ram word. */ 577#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 578#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 579#define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision. */ 580#define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue. */ 581#define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue. */ 582#define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command. */ 583#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 584#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 585#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 586#define MBC_BUS_RESET 0x18 /* SCSI bus reset. */ 587#define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay. */ 588#define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters. */ 589#define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID. */ 590#define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout. */ 591#define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay. */ 592#define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit. */ 593#define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate. */ 594#define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state. */ 595#define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time. */ 596#define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters. */ 597#define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters. */ 598#define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */ 599#define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word. */ 600#define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word. */ 601#define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */ 602#define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64. */ 603#define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode. */ 604 605/* 606 * ISP Get/Set Target Parameters mailbox command control flags. 607 */ 608#define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */ 609#define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */ 610#define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */ 611#define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */ 612#define TP_SYNC BIT_12 /* Synchronous data transfers. */ 613#define TP_WIDE BIT_13 /* Wide data transfers. */ 614#define TP_PARITY BIT_14 /* Parity checking. */ 615#define TP_DISCONNECT BIT_15 /* Disconnect privilege. */ 616 617/* 618 * NVRAM Command values. 619 */ 620#define NV_START_BIT BIT_2 621#define NV_WRITE_OP (BIT_26+BIT_24) 622#define NV_READ_OP (BIT_26+BIT_25) 623#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 624#define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 625#define NV_DELAY_COUNT 10 626 627/* 628 * QLogic ISP1280 NVRAM structure definition. 629 */ 630typedef struct 631{ 632 uint8_t id[4]; /* 0, 1, 2, 3 */ 633 uint8_t version; /* 4 */ 634 635 struct 636 { 637 uint8_t bios_configuration_mode :2; 638 uint8_t bios_disable :1; 639 uint8_t selectable_scsi_boot_enable :1; 640 uint8_t cd_rom_boot_enable :1; 641 uint8_t disable_loading_risc_code :1; 642 uint8_t enable_64bit_addressing :1; 643 uint8_t unused_7 :1; 644 }cntr_flags_1; /* 5 */ 645 646 struct 647 { 648 uint8_t boot_lun_number :5; 649 uint8_t scsi_bus_number :1; 650 uint8_t unused_6 :1; 651 uint8_t unused_7 :1; 652 uint8_t boot_target_number :4; 653 uint8_t unused_12 :1; 654 uint8_t unused_13 :1; 655 uint8_t unused_14 :1; 656 uint8_t unused_15 :1; 657 }cntr_flags_2; /* 6, 7 */ 658 659 uint16_t unused_8; /* 8, 9 */ 660 uint16_t unused_10; /* 10, 11 */ 661 uint16_t unused_12; /* 12, 13 */ 662 uint16_t unused_14; /* 14, 15 */ 663 664 union 665 { 666 uint8_t c; 667 struct 668 { 669 uint8_t reserved :2; 670 uint8_t burst_enable :1; 671 uint8_t reserved_1 :1; 672 uint8_t fifo_threshold :4; 673 }f; 674 }isp_config; /* 16 */ 675 676 /* Termination 677 * 0 = Disable, 1 = high only, 3 = Auto term 678 */ 679 union 680 { 681 uint8_t c; 682 struct 683 { 684 uint8_t scsi_bus_1_control :2; 685 uint8_t scsi_bus_0_control :2; 686 uint8_t unused_0 :1; 687 uint8_t unused_1 :1; 688 uint8_t unused_2 :1; 689 uint8_t auto_term_support :1; 690 }f; 691 }termination; /* 17 */ 692 693 uint16_t isp_parameter; /* 18, 19 */ 694 695 union 696 { 697 uint16_t w; 698 struct 699 { 700 uint8_t enable_fast_posting :1; 701 uint8_t report_lvd_bus_transition :1; 702 uint8_t unused_2 :1; 703 uint8_t unused_3 :1; 704 uint8_t unused_4 :1; 705 uint8_t unused_5 :1; 706 uint8_t unused_6 :1; 707 uint8_t unused_7 :1; 708 uint8_t unused_8 :1; 709 uint8_t unused_9 :1; 710 uint8_t unused_10 :1; 711 uint8_t unused_11 :1; 712 uint8_t unused_12 :1; 713 uint8_t unused_13 :1; 714 uint8_t unused_14 :1; 715 uint8_t unused_15 :1; 716 }f; 717 }firmware_feature; /* 20, 21 */ 718 719 uint16_t unused_22; /* 22, 23 */ 720 721 struct 722 { 723 struct 724 { 725 uint8_t initiator_id :4; 726 uint8_t scsi_reset_disable :1; 727 uint8_t scsi_bus_size :1; 728 uint8_t scsi_bus_type :1; 729 uint8_t unused_7 :1; 730 }config_1; /* 24 */ 731 732 uint8_t bus_reset_delay; /* 25 */ 733 uint8_t retry_count; /* 26 */ 734 uint8_t retry_delay; /* 27 */ 735 736 struct 737 { 738 uint8_t async_data_setup_time :4; 739 uint8_t req_ack_active_negation :1; 740 uint8_t data_line_active_negation :1; 741 uint8_t unused_6 :1; 742 uint8_t unused_7 :1; 743 }config_2; /* 28 */ 744 745 uint8_t unused_29; /* 29 */ 746 747 uint16_t selection_timeout; /* 30, 31 */ 748 uint16_t max_queue_depth; /* 32, 33 */ 749 750 uint16_t unused_34; /* 34, 35 */ 751 uint16_t unused_36; /* 36, 37 */ 752 uint16_t unused_38; /* 38, 39 */ 753 754 struct 755 { 756 union 757 { 758 uint8_t c; 759 struct 760 { 761 uint8_t renegotiate_on_error :1; 762 uint8_t stop_queue_on_check :1; 763 uint8_t auto_request_sense :1; 764 uint8_t tag_queuing :1; 765 uint8_t sync_data_transfers :1; 766 uint8_t wide_data_transfers :1; 767 uint8_t parity_checking :1; 768 uint8_t disconnect_allowed :1; 769 }f; 770 }parameter; /* 40 */ 771 772 uint8_t execution_throttle; /* 41 */ 773 uint8_t sync_period; /* 42 */ 774 775 struct 776 { 777 uint8_t sync_offset :4; 778 uint8_t device_enable :1; 779 uint8_t lun_disable :1; 780 uint8_t unused_6 :1; 781 uint8_t unused_7 :1; 782 }flags; /* 43 */ 783 784 uint16_t unused_44; /* 44, 45 */ 785 }target[MAX_TARGETS]; 786 }bus[MAX_BUSES]; 787 788 uint16_t unused_248; /* 248, 249 */ 789 790 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */ 791 792 uint8_t unused_254; /* 254 */ 793 794 uint8_t chksum; /* 255 */ 795}nvram_t; 796 797/* 798 * QLogic ISP12160 NVRAM structure definition. 799 */ 800typedef struct 801{ 802 uint8_t id[4]; /* 0, 1, 2, 3 */ 803 uint8_t version; /* 4 */ 804 /* Host/Bios Flags */ 805 struct 806 { 807 uint8_t bios_configuration_mode :2; 808 uint8_t bios_disable :1; 809 uint8_t selectable_scsi_boot_enable :1; 810 uint8_t cd_rom_boot_enable :1; 811 uint8_t disable_loading_risc_code :1; 812 uint8_t unused_6 :1; 813 uint8_t unused_7 :1; 814 }cntr_flags_1; /* 5 */ 815 /* Selectable Boot Support */ 816 struct 817 { 818 uint8_t boot_lun_number :5; 819 uint8_t scsi_bus_number :1; 820 uint8_t unused_6 :1; 821 uint8_t unused_7 :1; 822 uint8_t boot_target_number :4; 823 uint8_t unused_12 :1; 824 uint8_t unused_13 :1; 825 uint8_t unused_14 :1; 826 uint8_t unused_15 :1; 827 }cntr_flags_2; /* 6, 7 */ 828 829 uint16_t unused_8; /* 8, 9 */ 830 uint16_t unused_10; /* 10, 11 */ 831 uint16_t unused_12; /* 12, 13 */ 832 uint16_t unused_14; /* 14, 15 */ 833 834 /* ISP Config Parameters */ 835 union 836 { 837 uint8_t c; 838 struct 839 { 840 uint8_t reserved :2; 841 uint8_t burst_enable :1; 842 uint8_t reserved_1 :1; 843 uint8_t fifo_threshold :4; 844 }f; 845 }isp_config; /* 16 */ 846 847 /* Termination 848 * 0 = Disable, 1 = high only, 3 = Auto term 849 */ 850 union 851 { 852 uint8_t c; 853 struct 854 { 855 uint8_t scsi_bus_1_control :2; 856 uint8_t scsi_bus_0_control :2; 857 uint8_t unused_0 :1; 858 uint8_t unused_1 :1; 859 uint8_t unused_2 :1; 860 uint8_t auto_term_support :1; 861 }f; 862 }termination; /* 17 */ 863 /* Auto Term - 3 */ 864 /* High Only - 1 (GPIO2 = 1 & GPIO3 = 0) */ 865 /* Disable - 0 (GPIO2 = 0 & GPIO3 = X) */ 866 867 uint16_t isp_parameter; /* 18, 19 */ 868 869 union 870 { 871 uint16_t w; 872 struct 873 { 874 uint8_t enable_fast_posting :1; 875 uint8_t report_lvd_bus_transition :1; 876 uint8_t unused_2 :1; 877 uint8_t unused_3 :1; 878 uint8_t unused_4 :1; 879 uint8_t unused_5 :1; 880 uint8_t unused_6 :1; 881 uint8_t unused_7 :1; 882 uint8_t unused_8 :1; 883 uint8_t unused_9 :1; 884 uint8_t unused_10 :1; 885 uint8_t unused_11 :1; 886 uint8_t unused_12 :1; 887 uint8_t unused_13 :1; 888 uint8_t unused_14 :1; 889 uint8_t unused_15 :1; 890 }f; 891 }firmware_feature; /* 20, 21 */ 892 893 uint16_t unused_22; /* 22, 23 */ 894 895 struct 896 { 897 struct 898 { 899 uint8_t initiator_id :4; 900 uint8_t scsi_reset_disable :1; 901 uint8_t scsi_bus_size :1; 902 uint8_t scsi_bus_type :1; 903 uint8_t unused_7 :1; 904 }config_1; /* 24 */ 905 906 uint8_t bus_reset_delay; /* 25 */ 907 uint8_t retry_count; /* 26 */ 908 uint8_t retry_delay; /* 27 */ 909 /* Adapter Capabilities bits */ 910 struct 911 { 912 uint8_t async_data_setup_time :4; 913 uint8_t req_ack_active_negation :1; 914 uint8_t data_line_active_negation :1; 915 uint8_t unused_6 :1; 916 uint8_t unused_7 :1; 917 }config_2; /* 28 */ 918 919 uint8_t unused_29; /* 29 */ 920 921 uint16_t selection_timeout; /* 30, 31 */ 922 uint16_t max_queue_depth; /* 32, 33 */ 923 924 uint16_t unused_34; /* 34, 35 */ 925 uint16_t unused_36; /* 36, 37 */ 926 uint16_t unused_38; /* 38, 39 */ 927 928 struct 929 { 930 union 931 { 932 uint8_t c; 933 struct 934 { 935 uint8_t renegotiate_on_error :1; 936 uint8_t stop_queue_on_check :1; 937 uint8_t auto_request_sense :1; 938 uint8_t tag_queuing :1; 939 uint8_t sync_data_transfers :1; 940 uint8_t wide_data_transfers :1; 941 uint8_t parity_checking :1; 942 uint8_t disconnect_allowed :1; 943 }f; 944 }parameter; /* 40 */ 945 946 uint8_t execution_throttle; /* 41 */ 947 uint8_t sync_period; /* 42 */ 948 949 struct 950 { 951 uint8_t sync_offset :5; 952 uint8_t device_enable :1; 953 uint8_t unused_6 :1; 954 uint8_t unused_7 :1; 955 uint8_t ppr_options :4; 956 uint8_t ppr_bus_width :2; 957 uint8_t unused_8 :1; 958 uint8_t enable_ppr :1; 959 }flags; /* 43, 44 */ 960 961 uint8_t unused_45; /* 45 */ 962 }target[MAX_TARGETS]; 963 }bus[MAX_BUSES]; 964 965 uint16_t unused_248; /* 248, 249 */ 966 967 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */ 968 969 uint8_t System_Id_Pointer; /* 254 */ 970 971 uint8_t chksum; /* 255 */ 972}nvram160_t; 973 974/* 975 * ISP queue - command entry structure definition. 976 */ 977#define MAX_CMDSZ 12 /* SCSI maximum CDB size. */ 978typedef struct 979{ 980 uint8_t entry_type; /* Entry type. */ 981 #define COMMAND_TYPE 1 /* Command entry */ 982 uint8_t entry_count; /* Entry count. */ 983 uint8_t sys_define; /* System defined. */ 984 uint8_t entry_status; /* Entry Status. */ 985 uint32_t handle; /* System handle. */ 986 uint8_t lun; /* SCSI LUN */ 987 uint8_t target; /* SCSI ID */ 988 uint16_t cdb_len; /* SCSI command length. */ 989 uint16_t control_flags; /* Control flags. */ 990 uint16_t reserved; 991 uint16_t timeout; /* Command timeout. */ 992 uint16_t dseg_count; /* Data segment count. */ 993 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 994 uint32_t dseg_0_address; /* Data segment 0 address. */ 995 uint32_t dseg_0_length; /* Data segment 0 length. */ 996 uint32_t dseg_1_address; /* Data segment 1 address. */ 997 uint32_t dseg_1_length; /* Data segment 1 length. */ 998 uint32_t dseg_2_address; /* Data segment 2 address. */ 999 uint32_t dseg_2_length; /* Data segment 2 length. */ 1000 uint32_t dseg_3_address; /* Data segment 3 address. */ 1001 uint32_t dseg_3_length; /* Data segment 3 length. */ 1002}cmd_entry_t; 1003 1004/* 1005 * ISP queue - continuation entry structure definition. 1006 */ 1007typedef struct 1008{ 1009 uint8_t entry_type; /* Entry type. */ 1010 #define CONTINUE_TYPE 2 /* Continuation entry. */ 1011 uint8_t entry_count; /* Entry count. */ 1012 uint8_t sys_define; /* System defined. */ 1013 uint8_t entry_status; /* Entry Status. */ 1014 uint32_t reserved; /* Reserved */ 1015 uint32_t dseg_0_address; /* Data segment 0 address. */ 1016 uint32_t dseg_0_length; /* Data segment 0 length. */ 1017 uint32_t dseg_1_address; /* Data segment 1 address. */ 1018 uint32_t dseg_1_length; /* Data segment 1 length. */ 1019 uint32_t dseg_2_address; /* Data segment 2 address. */ 1020 uint32_t dseg_2_length; /* Data segment 2 length. */ 1021 uint32_t dseg_3_address; /* Data segment 3 address. */ 1022 uint32_t dseg_3_length; /* Data segment 3 length. */ 1023 uint32_t dseg_4_address; /* Data segment 4 address. */ 1024 uint32_t dseg_4_length; /* Data segment 4 length. */ 1025 uint32_t dseg_5_address; /* Data segment 5 address. */ 1026 uint32_t dseg_5_length; /* Data segment 5 length. */ 1027 uint32_t dseg_6_address; /* Data segment 6 address. */ 1028 uint32_t dseg_6_length; /* Data segment 6 length. */ 1029}cont_entry_t; 1030 1031/* 1032 * ISP queue - status entry structure definition. 1033 */ 1034typedef struct 1035{ 1036 uint8_t entry_type; /* Entry type. */ 1037 #define STATUS_TYPE 3 /* Status entry. */ 1038 uint8_t entry_count; /* Entry count. */ 1039 uint8_t sys_define; /* System defined. */ 1040 uint8_t entry_status; /* Entry Status. */ 1041 #define RF_CONT BIT_0 /* Continuation. */ 1042 #define RF_FULL BIT_1 /* Full */ 1043 #define RF_BAD_HEADER BIT_2 /* Bad header. */ 1044 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */ 1045 uint32_t handle; /* System handle. */ 1046 uint16_t scsi_status; /* SCSI status. */ 1047 uint16_t comp_status; /* Completion status. */ 1048 uint16_t state_flags; /* State flags. */ 1049 #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */ 1050 #define SF_GOT_SENSE BIT_13 /* Got Sense */ 1051 #define SF_GOT_STATUS BIT_12 /* Got Status */ 1052 #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */ 1053 #define SF_SENT_CDB BIT_10 /* Send CDB */ 1054 #define SF_GOT_TARGET BIT_9 /* */ 1055 #define SF_GOT_BUS BIT_8 /* */ 1056 uint16_t status_flags; /* Status flags. */ 1057 uint16_t time; /* Time. */ 1058 uint16_t req_sense_length; /* Request sense data length. */ 1059 uint32_t residual_length; /* Residual transfer length. */ 1060 uint16_t reserved[4]; 1061 uint8_t req_sense_data[32]; /* Request sense data. */ 1062}sts_entry_t, response_t; 1063 1064/* 1065 * ISP queue - marker entry structure definition. 1066 */ 1067typedef struct 1068{ 1069 uint8_t entry_type; /* Entry type. */ 1070 #define MARKER_TYPE 4 /* Marker entry. */ 1071 uint8_t entry_count; /* Entry count. */ 1072 uint8_t sys_define; /* System defined. */ 1073 uint8_t entry_status; /* Entry Status. */ 1074 uint32_t reserved; 1075 uint8_t lun; /* SCSI LUN */ 1076 uint8_t target; /* SCSI ID */ 1077 uint8_t modifier; /* Modifier (7-0). */ 1078 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1079 #define MK_SYNC_ID 1 /* Synchronize ID */ 1080 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1081 uint8_t reserved_1[53]; 1082}mrk_entry_t; 1083 1084/* 1085 * ISP queue - extended command entry structure definition. 1086 */ 1087typedef struct 1088{ 1089 uint8_t entry_type; /* Entry type. */ 1090 #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */ 1091 uint8_t entry_count; /* Entry count. */ 1092 uint8_t sys_define; /* System defined. */ 1093 uint8_t entry_status; /* Entry Status. */ 1094 uint32_t handle; /* System handle. */ 1095 uint8_t lun; /* SCSI LUN */ 1096 uint8_t target; /* SCSI ID */ 1097 uint16_t cdb_len; /* SCSI command length. */ 1098 uint16_t control_flags; /* Control flags. */ 1099 uint16_t reserved; 1100 uint16_t timeout; /* Command timeout. */ 1101 uint16_t dseg_count; /* Data segment count. */ 1102 uint8_t scsi_cdb[88]; /* SCSI command words. */ 1103}ecmd_entry_t; 1104 1105/* 1106 * ISP queue - 64-Bit addressing, command entry structure definition. 1107 */ 1108typedef struct 1109{ 1110 uint8_t entry_type; /* Entry type. */ 1111 #define COMMAND_A64_TYPE 9 /* Command A64 entry */ 1112 uint8_t entry_count; /* Entry count. */ 1113 uint8_t sys_define; /* System defined. */ 1114 uint8_t entry_status; /* Entry Status. */ 1115 uint32_t handle; /* System handle. */ 1116 uint8_t lun; /* SCSI LUN */ 1117 uint8_t target; /* SCSI ID */ 1118 uint16_t cdb_len; /* SCSI command length. */ 1119 uint16_t control_flags; /* Control flags. */ 1120 uint16_t reserved; 1121 uint16_t timeout; /* Command timeout. */ 1122 uint16_t dseg_count; /* Data segment count. */ 1123 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1124 uint32_t reserved_1[2]; /* unused */ 1125 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1126 uint32_t dseg_0_length; /* Data segment 0 length. */ 1127 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1128 uint32_t dseg_1_length; /* Data segment 1 length. */ 1129}cmd_a64_entry_t, request_t; 1130 1131/* 1132 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1133 */ 1134typedef struct 1135{ 1136 uint8_t entry_type; /* Entry type. */ 1137 #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */ 1138 uint8_t entry_count; /* Entry count. */ 1139 uint8_t sys_define; /* System defined. */ 1140 uint8_t entry_status; /* Entry Status. */ 1141 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1142 uint32_t dseg_0_length; /* Data segment 0 length. */ 1143 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1144 uint32_t dseg_1_length; /* Data segment 1 length. */ 1145 uint32_t dseg_2_address[2]; /* Data segment 2 address. */ 1146 uint32_t dseg_2_length; /* Data segment 2 length. */ 1147 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1148 uint32_t dseg_3_length; /* Data segment 3 length. */ 1149 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1150 uint32_t dseg_4_length; /* Data segment 4 length. */ 1151}cont_a64_entry_t; 1152 1153/* 1154 * ISP queue - enable LUN entry structure definition. 1155 */ 1156typedef struct 1157{ 1158 uint8_t entry_type; /* Entry type. */ 1159 #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */ 1160 uint8_t entry_count; /* Entry count. */ 1161 uint8_t reserved_1; 1162 uint8_t entry_status; /* Entry Status not used. */ 1163 uint32_t reserved_2; 1164 uint16_t lun; /* Bit 15 is bus number. */ 1165 uint16_t reserved_4; 1166 uint32_t option_flags; 1167 uint8_t status; 1168 uint8_t reserved_5; 1169 uint8_t command_count; /* Number of ATIOs allocated. */ 1170 uint8_t immed_notify_count; /* Number of Immediate Notify */ 1171 /* entries allocated. */ 1172 uint8_t group_6_length; /* SCSI CDB length for group 6 */ 1173 /* commands (2-26). */ 1174 uint8_t group_7_length; /* SCSI CDB length for group 7 */ 1175 /* commands (2-26). */ 1176 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 1177 uint16_t reserved_6[20]; 1178}elun_entry_t; 1179 1180/* 1181 * ISP queue - modify LUN entry structure definition. 1182 */ 1183typedef struct 1184{ 1185 uint8_t entry_type; /* Entry type. */ 1186 #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */ 1187 uint8_t entry_count; /* Entry count. */ 1188 uint8_t reserved_1; 1189 uint8_t entry_status; /* Entry Status. */ 1190 uint32_t reserved_2; 1191 uint8_t lun; /* SCSI LUN */ 1192 uint8_t reserved_3; 1193 uint8_t operators; 1194 uint8_t reserved_4; 1195 uint32_t option_flags; 1196 uint8_t status; 1197 uint8_t reserved_5; 1198 uint8_t command_count; /* Number of ATIOs allocated. */ 1199 uint8_t immed_notify_count; /* Number of Immediate Notify */ 1200 /* entries allocated. */ 1201 uint16_t reserved_6; 1202 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 1203 uint16_t reserved_7[20]; 1204}modify_lun_entry_t; 1205 1206/* 1207 * ISP queue - immediate notify entry structure definition. 1208 */ 1209typedef struct 1210{ 1211 uint8_t entry_type; /* Entry type. */ 1212 #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */ 1213 uint8_t entry_count; /* Entry count. */ 1214 uint8_t reserved_1; 1215 uint8_t entry_status; /* Entry Status. */ 1216 uint32_t reserved_2; 1217 uint8_t lun; 1218 uint8_t initiator_id; 1219 uint8_t reserved_3; 1220 uint8_t target_id; 1221 uint32_t option_flags; 1222 uint8_t status; 1223 uint8_t reserved_4; 1224 uint8_t tag_value; /* Received queue tag message value */ 1225 uint8_t tag_type; /* Received queue tag message type */ 1226 /* entries allocated. */ 1227 uint16_t seq_id; 1228 uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */ 1229 uint16_t reserved_5[8]; 1230 uint8_t sense_data[18]; 1231}notify_entry_t; 1232 1233/* 1234 * ISP queue - notify acknowledge entry structure definition. 1235 */ 1236typedef struct 1237{ 1238 uint8_t entry_type; /* Entry type. */ 1239 #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */ 1240 uint8_t entry_count; /* Entry count. */ 1241 uint8_t reserved_1; 1242 uint8_t entry_status; /* Entry Status. */ 1243 uint32_t reserved_2; 1244 uint8_t lun; 1245 uint8_t initiator_id; 1246 uint8_t reserved_3; 1247 uint8_t target_id; 1248 uint32_t option_flags; 1249 uint8_t status; 1250 uint8_t event; 1251 uint16_t seq_id; 1252 uint16_t reserved_4[22]; 1253}nack_entry_t; 1254 1255/* 1256 * ISP queue - Accept Target I/O (ATIO) entry structure definition. 1257 */ 1258typedef struct 1259{ 1260 uint8_t entry_type; /* Entry type. */ 1261 #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */ 1262 uint8_t entry_count; /* Entry count. */ 1263 uint8_t reserved_1; 1264 uint8_t entry_status; /* Entry Status. */ 1265 uint32_t reserved_2; 1266 uint8_t lun; 1267 uint8_t initiator_id; 1268 uint8_t cdb_len; 1269 uint8_t target_id; 1270 uint32_t option_flags; 1271 uint8_t status; 1272 uint8_t scsi_status; 1273 uint8_t tag_value; /* Received queue tag message value */ 1274 uint8_t tag_type; /* Received queue tag message type */ 1275 uint8_t cdb[26]; 1276 uint8_t sense_data[18]; 1277}atio_entry_t; 1278 1279/* 1280 * ISP queue - Continue Target I/O (CTIO) entry structure definition. 1281 */ 1282typedef struct 1283{ 1284 uint8_t entry_type; /* Entry type. */ 1285 #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */ 1286 uint8_t entry_count; /* Entry count. */ 1287 uint8_t reserved_1; 1288 uint8_t entry_status; /* Entry Status. */ 1289 uint32_t reserved_2; 1290 uint8_t lun; /* SCSI LUN */ 1291 uint8_t initiator_id; 1292 uint8_t reserved_3; 1293 uint8_t target_id; 1294 uint32_t option_flags; 1295 uint8_t status; 1296 uint8_t scsi_status; 1297 uint8_t tag_value; /* Received queue tag message value */ 1298 uint8_t tag_type; /* Received queue tag message type */ 1299 uint32_t transfer_length; 1300 uint32_t residual; 1301 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 1302 uint16_t dseg_count; /* Data segment count. */ 1303 uint32_t dseg_0_address; /* Data segment 0 address. */ 1304 uint32_t dseg_0_length; /* Data segment 0 length. */ 1305 uint32_t dseg_1_address; /* Data segment 1 address. */ 1306 uint32_t dseg_1_length; /* Data segment 1 length. */ 1307 uint32_t dseg_2_address; /* Data segment 2 address. */ 1308 uint32_t dseg_2_length; /* Data segment 2 length. */ 1309 uint32_t dseg_3_address; /* Data segment 3 address. */ 1310 uint32_t dseg_3_length; /* Data segment 3 length. */ 1311}ctio_entry_t; 1312 1313/* 1314 * ISP queue - CTIO returned entry structure definition. 1315 */ 1316typedef struct 1317{ 1318 uint8_t entry_type; /* Entry type. */ 1319 #define CTIO_RET_TYPE 7 /* CTIO return entry */ 1320 uint8_t entry_count; /* Entry count. */ 1321 uint8_t reserved_1; 1322 uint8_t entry_status; /* Entry Status. */ 1323 uint32_t reserved_2; 1324 uint8_t lun; /* SCSI LUN */ 1325 uint8_t initiator_id; 1326 uint8_t reserved_3; 1327 uint8_t target_id; 1328 uint32_t option_flags; 1329 uint8_t status; 1330 uint8_t scsi_status; 1331 uint8_t tag_value; /* Received queue tag message value */ 1332 uint8_t tag_type; /* Received queue tag message type */ 1333 uint32_t transfer_length; 1334 uint32_t residual; 1335 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 1336 uint16_t dseg_count; /* Data segment count. */ 1337 uint32_t dseg_0_address; /* Data segment 0 address. */ 1338 uint32_t dseg_0_length; /* Data segment 0 length. */ 1339 uint32_t dseg_1_address; /* Data segment 1 address. */ 1340 uint16_t dseg_1_length; /* Data segment 1 length. */ 1341 uint8_t sense_data[18]; 1342}ctio_ret_entry_t; 1343 1344/* 1345 * ISP queue - CTIO A64 entry structure definition. 1346 */ 1347typedef struct 1348{ 1349 uint8_t entry_type; /* Entry type. */ 1350 #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */ 1351 uint8_t entry_count; /* Entry count. */ 1352 uint8_t reserved_1; 1353 uint8_t entry_status; /* Entry Status. */ 1354 uint32_t reserved_2; 1355 uint8_t lun; /* SCSI LUN */ 1356 uint8_t initiator_id; 1357 uint8_t reserved_3; 1358 uint8_t target_id; 1359 uint32_t option_flags; 1360 uint8_t status; 1361 uint8_t scsi_status; 1362 uint8_t tag_value; /* Received queue tag message value */ 1363 uint8_t tag_type; /* Received queue tag message type */ 1364 uint32_t transfer_length; 1365 uint32_t residual; 1366 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 1367 uint16_t dseg_count; /* Data segment count. */ 1368 uint32_t reserved_4[2]; 1369 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1370 uint32_t dseg_0_length; /* Data segment 0 length. */ 1371 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1372 uint32_t dseg_1_length; /* Data segment 1 length. */ 1373}ctio_a64_entry_t; 1374 1375/* 1376 * ISP queue - CTIO returned entry structure definition. 1377 */ 1378typedef struct 1379{ 1380 uint8_t entry_type; /* Entry type. */ 1381 #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */ 1382 uint8_t entry_count; /* Entry count. */ 1383 uint8_t reserved_1; 1384 uint8_t entry_status; /* Entry Status. */ 1385 uint32_t reserved_2; 1386 uint8_t lun; /* SCSI LUN */ 1387 uint8_t initiator_id; 1388 uint8_t reserved_3; 1389 uint8_t target_id; 1390 uint32_t option_flags; 1391 uint8_t status; 1392 uint8_t scsi_status; 1393 uint8_t tag_value; /* Received queue tag message value */ 1394 uint8_t tag_type; /* Received queue tag message type */ 1395 uint32_t transfer_length; 1396 uint32_t residual; 1397 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 1398 uint16_t dseg_count; /* Data segment count. */ 1399 uint16_t reserved_4[7]; 1400 uint8_t sense_data[18]; 1401}ctio_a64_ret_entry_t; 1402 1403/* 1404 * ISP request and response queue entry sizes 1405 */ 1406#define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1407#define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1408 1409/* 1410 * ISP status entry - completion status definitions. 1411 */ 1412#define CS_COMPLETE 0x0 /* No errors */ 1413#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1414#define CS_DMA 0x2 /* A DMA direction error. */ 1415#define CS_TRANSPORT 0x3 /* Transport error. */ 1416#define CS_RESET 0x4 /* SCSI bus reset occurred */ 1417#define CS_ABORTED 0x5 /* System aborted command. */ 1418#define CS_TIMEOUT 0x6 /* Timeout error. */ 1419#define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1420#define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */ 1421#define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */ 1422#define CS_BAD_MSG 0xA /* Bad msg after status phase. */ 1423#define CS_NO_MSG_OUT 0xB /* No msg out after selection. */ 1424#define CS_EXTENDED_ID 0xC /* Extended ID failed. */ 1425#define CS_IDE_MSG 0xD /* Target rejected IDE msg. */ 1426#define CS_ABORT_MSG 0xE /* Target rejected abort msg. */ 1427#define CS_REJECT_MSG 0xF /* Target rejected reject msg. */ 1428#define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */ 1429#define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */ 1430#define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */ 1431#define CS_ID_MSG 0x13 /* Target rejected ID msg. */ 1432#define CS_FREE 0x14 /* Unexpected bus free. */ 1433#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1434#define CS_TRANACTION_1 0x18 /* Transaction error 1 */ 1435#define CS_TRANACTION_2 0x19 /* Transaction error 2 */ 1436#define CS_TRANACTION_3 0x1a /* Transaction error 3 */ 1437#define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */ 1438#define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */ 1439#define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */ 1440#define CS_ARS_FAILED 0x1e /* ARS failed */ 1441#define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */ 1442#define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1443#define CS_UNKNOWN 0x81 /* Driver defined */ 1444#define CS_RETRY 0x82 /* Driver defined */ 1445 1446/* 1447 * ISP status entry - SCSI status byte bit definitions. 1448 */ 1449#define SS_CHECK_CONDITION BIT_1 1450#define SS_CONDITION_MET BIT_2 1451#define SS_BUSY_CONDITION BIT_3 1452#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1453 1454/* 1455 * ISP target entries - Option flags bit definitions. 1456 */ 1457#define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */ 1458#define OF_DATA_IN BIT_6 /* Data in to initiator */ 1459 /* (data from target to initiator) */ 1460#define OF_DATA_OUT BIT_7 /* Data out from initiator */ 1461 /* (data from initiator to target) */ 1462#define OF_NO_DATA (BIT_7 | BIT_6) 1463#define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */ 1464#define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */ 1465#define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */ 1466#define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */ 1467#define OF_SSTS BIT_31 /* Send SCSI status */ 1468 1469#if QL1280_TARGET_MODE_SUPPORT 1470/* 1471 * Target Read/Write buffer structure. 1472 */ 1473#define TARGET_DATA_OFFSET 4 1474#define TARGET_DATA_SIZE 0x2000 /* 8K */ 1475#define TARGET_INQ_OFFSET (TARGET_DATA_OFFSET + TARGET_DATA_SIZE) 1476#define TARGET_SENSE_SIZE 18 1477#define TARGET_BUF_SIZE 36 1478 1479typedef struct 1480{ 1481 uint8_t hdr[4]; 1482 uint8_t data[TARGET_DATA_SIZE]; 1483 struct ident inq; 1484}tgt_t; 1485#endif 1486 1487/* 1488 * BUS parameters/settings structure 1489 */ 1490typedef struct 1491{ 1492 uint8_t id; /* Host adapter SCSI id */ 1493 uint8_t bus_reset_delay; /* SCSI bus reset delay. */ 1494 uint8_t failed_reset_count; /* number of time reset failed */ 1495 uint8_t unused; 1496 uint16_t device_enables; /* Device enable bits. */ 1497 uint16_t lun_disables; /* LUN disable bits. */ 1498 uint16_t qtag_enables; /* Tag queue enables. */ 1499 uint16_t hiwat; /* High water mark per device. */ 1500 uint8_t reset_marker :1; 1501 uint8_t disable_scsi_reset :1; 1502 uint8_t scsi_bus_dead :1; /* SCSI Bus is Dead, when 5 back to back resets failed */ 1503 1504}bus_param_t; 1505 1506/* 1507 * Linux Host Adapter structure 1508 */ 1509typedef struct scsi_qla_host 1510{ 1511 /* Linux adapter configuration data */ 1512 struct Scsi_Host *host; /* pointer to host data */ 1513 struct scsi_qla_host *next; 1514 device_reg_t *iobase; /* Base Memory-mapped I/O address */ 1515 uint8_t pci_bus; 1516 uint8_t pci_device_fn; 1517 uint8_t devnum; 1518#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) 1519 struct pci_dev *pdev; 1520#endif 1521 volatile unsigned char *mmpbase; /* memory mapped address */ 1522 unsigned long host_no; 1523 unsigned long instance; 1524 uint8_t revision; 1525 uint8_t ports; 1526#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0) 1527 spinlock_t spin_lock; 1528#endif 1529 volatile unsigned char cpu_lock_count[NR_CPUS]; 1530 unsigned long actthreads; 1531 unsigned long qthreads; 1532 unsigned long isr_count; /* Interrupt count */ 1533 unsigned long spurious_int; 1534 1535 uint32_t device_id; 1536 1537 /* Outstandings ISP commands. */ 1538 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; 1539 1540 /* BUS configuration data */ 1541 bus_param_t bus_settings[MAX_BUSES]; 1542 1543 /* Device LUN queues. */ 1544 scsi_lu_t *dev[MAX_EQ]; /* Logical unit queues */ 1545 1546#ifdef UNUSED 1547 /* Interrupt lock, and data */ 1548 uint8_t intr_lock; /* Lock for interrupt locking */ 1549#endif 1550 1551 /* bottom half run queue */ 1552 struct tq_struct run_qla_bh; 1553 1554 /* Received ISP mailbox data. */ 1555 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 1556 1557#ifdef UNUSED 1558 /* ISP ring lock, rings, and indexes */ 1559 uint8_t ring_lock; /* ISP ring lock */ 1560 struct timer_list dev_timer[MAX_TARGETS]; 1561#endif 1562 1563 request_t req[REQUEST_ENTRY_CNT+1]; 1564 response_t res[RESPONSE_ENTRY_CNT+1]; 1565 unsigned long request_dma; /* Physical address. */ 1566 request_t *request_ring; /* Base virtual address */ 1567 request_t *request_ring_ptr; /* Current address. */ 1568 uint16_t req_ring_index; /* Current index. */ 1569 uint16_t req_q_cnt; /* Number of available entries. */ 1570 1571 unsigned long response_dma; /* Physical address. */ 1572 response_t *response_ring; /* Base virtual address */ 1573 response_t *response_ring_ptr; /* Current address. */ 1574 uint16_t rsp_ring_index; /* Current index. */ 1575 1576#if QL1280_TARGET_MODE_SUPPORT 1577 /* Target buffer and sense data. */ 1578 uint32_t tbuf_dma; /* Physical address. */ 1579 tgt_t *tbuf; 1580 uint32_t tsense_dma; /* Physical address. */ 1581 uint8_t *tsense; 1582#endif 1583 1584#if WATCHDOGTIMER 1585 /* Watchdog queue, lock and total timer */ 1586 uint8_t watchdog_q_lock; /* Lock for watchdog queue */ 1587 srb_t *wdg_q_first; /* First job on watchdog queue */ 1588 srb_t *wdg_q_last; /* Last job on watchdog queue */ 1589 uint32_t total_timeout; /* Total timeout (quantum count) */ 1590 uint32_t watchdogactive; 1591#endif 1592 1593 srb_t *done_q_first; /* First job on done queue */ 1594 srb_t *done_q_last; /* Last job on done queue */ 1595 1596 volatile struct 1597 { 1598 uint32_t watchdog_enabled :1; /* 0 */ 1599 uint32_t mbox_int :1; /* 1 */ 1600 uint32_t mbox_busy :1; /* 2 */ 1601 uint32_t online :1; /* 3 */ 1602 uint32_t reset_marker :1; /* 4 */ 1603 uint32_t isp_abort_needed :1; /* 5 */ 1604 uint32_t pci_64bit_slot :1; /* 6 */ 1605 uint32_t disable_host_adapter :1; /* 7 */ 1606 uint32_t reset_active :1; /* 8 */ 1607 uint32_t abort_isp_active :1; /* 9 */ 1608 uint32_t disable_risc_code_load :1; /* 10 */ 1609 uint32_t enable_64bit_addressing :1; /* 11 */ 1610#define QLA1280_IN_ISR_BIT 12 1611 uint32_t in_isr :1; /* 12 */ 1612 uint32_t in_abort :1; /* 13 */ 1613 uint32_t in_reset :1; /* 14 */ 1614 uint32_t dpc :1; /* 15 */ 1615 uint32_t dpc_sched :1; /* 16 */ 1616 uint32_t interrupts_on :1; /* 17 */ 1617 }flags; 1618 1619}scsi_qla_host_t; 1620 1621/* 1622 * Macros to help code, maintain, etc. 1623 */ 1624#define SUBDEV(b, t, l) ( (b << (MAX_T_BITS + MAX_L_BITS)) | (t << MAX_L_BITS) | l) 1625#define LU_Q(ha, b, t, l) (ha->dev[SUBDEV(b, t, l)]) 1626 1627/* 1628 * Locking Macro Definitions 1629 * 1630 * LOCK/UNLOCK definitions are lock/unlock primitives for multi-processor 1631 * or spl/splx for uniprocessor. 1632 */ 1633#define QLA1280_HIER HBA_HIER_BASE /* Locking hierarchy base for hba */ 1634 1635#define QLA1280_WATCHDOG_Q_LOCK(ha, p) 1636#define QLA1280_WATCHDOG_Q_UNLOCK(ha, p) 1637 1638#define QLA1280_SCSILU_LOCK(q) 1639#define QLA1280_SCSILU_UNLOCK(q) 1640 1641#define QLA1280_INTR_LOCK(ha) 1642#define QLA1280_INTR_UNLOCK(ha) 1643 1644#define QLA1280_RING_LOCK(ha) 1645#define QLA1280_RING_UNLOCK(ha) 1646 1647#if defined(__cplusplus) 1648} 1649#endif 1650/* 1651 * Linux - SCSI Driver Interface Function Prototypes. 1652 */ 1653int qla1280_proc_info ( char *, char **, off_t, int, int, int); 1654const char * qla1280_info(struct Scsi_Host *host); 1655int qla1280_detect(Scsi_Host_Template *); 1656int qla1280_release(struct Scsi_Host *); 1657const char * qla1280_info(struct Scsi_Host *); 1658int qla1280_queuecommand(Scsi_Cmnd *, void (* done)(Scsi_Cmnd *)); 1659int qla1280_abort(Scsi_Cmnd *); 1660int qla1280_reset(Scsi_Cmnd *, unsigned int); 1661int qla1280_biosparam(Disk *, kdev_t, int[]); 1662void qla1280_intr_handler(int, void *, struct pt_regs *); 1663void qla1280_setup(char *s, int *dummy); 1664#if defined(__386__) 1665# define QLA1280_BIOSPARAM qla1280_biosparam 1666#else 1667# define QLA1280_BIOSPARAM NULL 1668#endif 1669 1670/* 1671 * Scsi_Host_template (see hosts.h) 1672 * Device driver Interfaces to mid-level SCSI driver. 1673 */ 1674#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) 1675/* This interface is now obsolete !!! */ 1676#define QLA1280_LINUX_TEMPLATE { \ 1677 next: NULL, \ 1678 usage_count: NULL, \ 1679 proc_dir: NULL, \ 1680 proc_info: NULL, \ 1681 name: "Qlogic ISP 1280", \ 1682 detect: qla1280_detect, \ 1683 release: qla1280_release, \ 1684 info: qla1280_info, \ 1685 command: NULL, \ 1686 queuecommand: qla1280_queuecommand, \ 1687 abort: qla1280_abort, \ 1688 reset: qla1280_reset, \ 1689 slave_attach: NULL, \ 1690 bios_param: QLA1280_BIOSPARAM, \ 1691 can_queue: 255, /* MAX_OUTSTANDING_COMMANDS */ \ 1692 this_id: -1, /* scsi id of host adapter */ \ 1693 sg_tablesize: SG_ALL, \ 1694 cmd_per_lun: 3, /* max commands per lun */ \ 1695 present: 0, /* number of 1280s present */ \ 1696 unchecked_isa_dma: 0, /* no memeory DMA restrictions */ \ 1697 use_clustering: ENABLE_CLUSTERING \ 1698} 1699#else 1700 1701#define QLA1280_LINUX_TEMPLATE { \ 1702 next: NULL, \ 1703 module: NULL, \ 1704 proc_dir: NULL, \ 1705 proc_info: qla1280_proc_info, \ 1706 name: "Qlogic ISP 1280\1080", \ 1707 detect: qla1280_detect, \ 1708 release: qla1280_release, \ 1709 info: qla1280_info, \ 1710 ioctl: NULL, \ 1711 command: NULL, \ 1712 queuecommand: qla1280_queuecommand, \ 1713 eh_strategy_handler: NULL, \ 1714 eh_abort_handler: NULL, \ 1715 eh_device_reset_handler: NULL, \ 1716 eh_bus_reset_handler: NULL, \ 1717 eh_host_reset_handler: NULL, \ 1718 abort: qla1280_abort, \ 1719 reset: qla1280_reset, \ 1720 slave_attach: NULL, \ 1721 bios_param: QLA1280_BIOSPARAM, \ 1722 can_queue: 255, /* max simultaneous cmds */\ 1723 this_id: -1, /* scsi id of host adapter */\ 1724 sg_tablesize: SG_ALL, /* max scatter-gather cmds */\ 1725 cmd_per_lun: 3, /* cmds per lun (linked cmds) */\ 1726 present: 0, /* number of 7xxx's present */\ 1727 unchecked_isa_dma: 0, /* no memory DMA restrictions */\ 1728 use_clustering: ENABLE_CLUSTERING, \ 1729 use_new_eh_code: 0, \ 1730 emulated: 0 \ 1731} 1732#endif 1733 1734 1735#endif /* _IO_HBA_QLA1280_H */ 1736